(2+1) D Temperature Mapping of Stacked Silicon Dies from X-Ray Diffraction Intensities

The increase in power density of processors has led to an increase in the occurrence of thermal hot spots in computer processors. Tracking of the hot spots is important as most failure mechanisms in the processors have strong temperature dependence. In 3D integrated circuits, conventional surface techniques like infrared thermometry are unable to measure 3D temperature distribution, and optical and magnetic resonance techniques are difficult to apply due to the presence of metals and large current densities. X-rays offer high penetration depth and can be used to probe 3D structures. We report a method utilizing the temperature dependence of x-rays diffraction intensity via the Debye-Waller factor to simultaneously map the temperature of several silicon dies in a stack. Utilizing beamline 1-ID-E beamline at the Advanced Photon Source (Argonne), we show for each individual silicon die, a temperature resolution of 3.5 K, a spatial resolution of 100 µm x 400 µm and a spatial resolution of 20 s. Utilizing high intensity sources from liquid anode sources, this method can be scaled down to laboratories for (2+1) D temperature mapping of 3D integrated circuits.