Vertically Extended Channel Thin-Film Transistors Using Dry Etched Tungsten Gate for Ultra-High-Resolution Display

The significance of backplane devices for ultra-high-resolution (UHR) displays has increased with the recent development of augmented reality (AR) and virtual reality (VR) devices. Since the human visual resolution can distinguish up to 60 pixels per degree (PPD), the AR/VR device panel needs at least 3000 pixels per inch (PPI) to exceed the human retina resolution limit for a clear display without screen effect. As a result, the unit pixel pitch of thin film transistor (TFT) for UHR display should not be only smaller than a few micrometers (~3 μm), but TFT channel length should also be sub-micrometers level. In active-matrix organic light emitting diode (AMOLED) display type, self-aligned top gate (SATG) TFT has been widely used as a planar backplane device structure because of its low parasitic capacitance and tolerance of illumination degradation caused by the light from emitting layer [1-2]. However, SATG TFT has fundamental disadvantages for device miniaturization due to its essentially required area of metallization region for reducing contact resistance and scaling limit of channel induced by carrier diffusion shrinking effective channel length. For this reason, we suggested a size-tunable oxide channel VTFT structure that can achieve a high pixel density on account of structural benefit on device footprint.<br/>In this work, we fabricated scalable amorphous indium gallium zinc oxide (a-IGZO) based VTFT with a dry etched gate layer. In the previously published VTFT structure, the channel length is determined by the thickness of the spacer between the source and drain electrodes [3]. Owing to the spacer etching process, uneven backchannel roughness and high off current have become well-known issues of VTFT. On the contrary, the proposed vertically extended channel (VEC) TFT structure has controllability of an effective channel aspect ratio because the source and drain electrodes could be patterned by a photolithography process. Also, VEC TFT has a small device footprint (4.5 F²), so it is suitable for high-density applications. Furthermore, since the sidewall profile of the dry-etched tungsten gate was optimized by several etchants such as fluorine-based and chlorine-based gases, the electrical performance of the vertical channel could be improved by the anisotropically etched gate metal.<br/>To sum up, we not only realized the oxide channel VTFT that meets high performance for AR/VR display, but opened new application possibilities to UHR electronic devices platform.<br/><br/>[1]. Kang, Dong Han, et al. "Self-aligned coplanar a-IGZO TFTs and application to high-speed circuits." IEEE electron device letters 32.10 (2011): 1385-1387.<br/>[2]. Wang, Guoying, et al. "8.3: High Stability Against Light and Heat Based on the Top Gate Self-Aligned a-IGZO TFTs under OLED Dislplay." <i>SID Symposium Digest of Technical Papers</i>. Vol. 49. 2018.<br/>[3]. Petti, Luisa, et al. "Flexible quasi-vertical In-Ga-Zn-O thin-film transistor with 300-nm channel length." <i>IEEE Electron Device Letters</i> 36.5 (2015): 475-477.