Catherine Dubourdieu1,2,Keerthana Nair1,2,Marco Holzer1,2,Veeresh Deshpande1
Helmholtz Zentrum Berlin1,Freie Universität Berlin2
Catherine Dubourdieu1,2,Keerthana Nair1,2,Marco Holzer1,2,Veeresh Deshpande1
Helmholtz Zentrum Berlin1,Freie Universität Berlin2
Hafnium dioxide-based ferroelectrics are enabling the integration of ferroelectric devices into CMOS technology due to their stable ferroelectric phase at nanometer thickness. The low-temperature crystallization (around 400°C) further allows Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub> (HZO) based devices to be integrated into the back-end-of-line of CMOS technology. Among the ferroelectric memory devices, ferroelectric tunnel junctions (FTJ) are well-suited for neuromorphic applications due to their ultra-low power consumption and potential to attain multiple resistance states through partial switching of domains from one polarization state to the other. The typical architecture of FTJ devices is metal-ferroelectric-metal, where the ferroelectric layer should be less than 5 nm in thickness and possess a high remnant polarization to achieve a high ON current. As stabilizing high polarization in sub-5 nm thick HZO layer is challenging, an alternate device stack consisting of Metal-Ferroelectric-Dielectric-Metal layers utilizing a thicker ferroelectric layer (~10-12 nm) has recently been demonstrated with a high ON/OFF ratio [1]. In this work, we study CMOS back-end compatible Metal-HZO-Al<sub>2</sub>O<sub>3</sub>-Metal FTJ with TiN and W metals. Different stacks, by changing the position of the metal electrode and the dielectric, are fabricated to find the optimum configuration for high ON/OFF ratio. It is observed that the ON/OFF ratio is highly dependent on the positioning of the W, TiN electrodes, and the Al<sub>2</sub>O<sub>3</sub> dielectric. We will discuss the influence of processing sequence of the layers and the role of resultant interface charge trap density on the FTJ characteristics [2]. The impact of dielectric thickness on ON/OFF ratio will also be discussed. The optimized FTJ device is electrically programmed to demonstrate multiple resistance states through partial switching set and reset operations. The stability of the intermediate states will be discussed based on the endurance and retention characteristics.<br/>[1] V. Deshpande, K. S. Nair, M. Holzer, S. Banerjee, and C. Dubourdieu, Solid State Electronics, 186, pp. 108054 (2021).<br/>[2] R. Fontanini, M. Segatto, K. S. Nair, M. Holzer, F. Driussi, I. Häusler, C. T. Koch, C. Dubourdieu, V. Deshpande, and D. Esseni, IEEE Transactions on Electron Devices, 1 (2022).