Bhushan L. Sopori National Renewable Energy Laboratory
Bernhard Dimmler Würth Solar GmbH & Co. KG
Jeffrey Yang United Solar Ovonic LLC
Thomas Surek Surek PV Consulting
Q1: Crystalline Silicon Technologies
Monday PM, November 30, 2009
Room 306 (Hynes)
9:30 AM - **Q1.1
Hydrogen Passivation for Crystalline Silicon Solar Cells.
Michael Stavola 1 Show Abstract
1 Department of Physics, Lehigh University, Bethlehem, Pennsylvania, United States
The Si substrates that are often used for the fabrication of solar cells to reduce cost give rise to defect issues that must be addressed. Hydrogen is commonly introduced into silicon solar cells to reduce the deleterious effects of defects and to increase cell efficiency . A process that is used by industry to introduce hydrogen is by the post-deposition annealing of a hydrogen-rich SiNx layer that is used as an antireflection coating . A number of questions about this hydrogen introduction process and hydrogen’s subsequent interactions with defects have proved difficult to address because of the low concentration of hydrogen that is introduced into the Si bulk.Fundamental studies of hydrogen-containing defects in silicon provide a foundation for addressing issues of interest to the Si solar-cell community. Strategies have been developed by which hydrogen in silicon can be detected by IR spectroscopy with high sensitivity [3,4]. The introduction of hydrogen into Si by the post-deposition annealing of a SiNx coating has been investigated to reveal hydrogen’s concentration, diffusivity, and reactions with defects. The effect of processing variations on the concentration of hydrogen that is introduced into the Si bulk has also been studied. The contributions of F. Jiang, S. Kleekajai, V. Yelundur, A. Rohatgi, L. Carnel, J. Kalejs, and G. Hahn to our studies are gratefully acknowledged. This work has been supported by the Silicon Solar Research Center SiSoC Members through NCSU Subaward No. 2008-0519-02 and NSF Grant No. DMR 0802278. J. I. Hanoka, C. H. Seager, D. J. Sharp, and J. K. G. Panitz, Appl. Phys. Lett. 42,618 (1983). F. Duerinckx and J. Szlufcik, Sol. Energy Mater. Sol. Cells 72, 231 (2002). F. Jiang et al., Appl. Phys. Lett. 83, 931 (2003). S. Kleekajai et al., J. Appl. Phys. 100, 093517 (2006).
10:00 AM - Q1.2
A New, Ultrafast Technique for Mapping Dislocation Density in Large-area, Single-crystal and Multicrystalline Si Wafers.
Bhushan Sopori 1 , Przemyslaw Rupnowski 1 , Mathew Albert 2 , Chandra Khattak 2 , Mike Seacrist 3 Show Abstract
1 , National Renewable Energy Laboratory, Golden, Colorado, United States, 2 , GT Solar, Merrimack, New Hampshire, United States, 3 , MEMC, St. Peters, Missouri, United States
Average dislocation density and spatial distribution of dislocations are routinely used as a measure of crystal quality of single- and multicrystalline Si (mc-Si) wafers. A variety of techniques have been developed to generate dislocation maps, including X-ray imaging, Cu decoration, and chemical delineation. The most common method is to defect etch the wafer with a suitable chemical etchant and then count the etch pits using an optical microscope. Commercial camera systems, with image analysis software, are available as microscope attachments that can count etch pits within the field of view and combine that information to produce maps of dislocation distribution over a wafer. An improved technique uses light scattered by etch pits to statistically count dislocations. The wafer is illuminated by a laser beam and the total scattered light, which is proportional to the number of etch pits in the illuminated region, is measured. An instrument based on this technique takes 30–60 minutes to map a 6-in x 6-in wafer.This paper describes a new technique that uses scattering from a defect-etched wafer to map dislocation distribution of the entire wafer in a single image. The measurement is very fast and compatible with large-area wafers. In this technique, the single- or multicrystalline wafer is polished to produce a damage-free polished surface. The wafer is then defect etched using Sopori etch (HF:CH3COOH:HNO3 in a 36:15:1 ratio) for 30 s to produce etch pits at dislocation sites. The shape of the etch pit depends on the direction of dislocation at the surface and does not depend on the orientation of the wafer or grain (in mc-Si). The wafer is then placed in a reflectometer where a set of lights, symmetrically placed around the wafer, illuminate it at an oblique incidence. The light scattered normal to the wafer is collected by a camera and imaged. The image corresponds to the local reflectance of the defect-etched wafer. Because local scattering is proportional to the density of etch pits, the camera image is proportional to the local variation in the dislocation density of the wafer. The system is calibrated by using a reference sample to convert the reflectance map into a dislocation map. This technique allows a fast (< 1 s) mapping of dislocations. An interesting feature of this etch is that the scattering cross-section of all dislocations (which can have circular, elliptical, or comet shapes) is the same. Thus, all dislocations are counted. An instrument based on this technique is now commercially available. We will show results that demonstrate: (i) repeatability of defect etching of large mc-Si wafers, (ii) variation of dislocation patterns over selected parts of a mc-Si ingot, (iii) a correlation between defect maps and photocurrent maps of commercial Si solar cells, and (iv) a correlation between defect distribution and the solar cell performance.This abstract is subject to government rights.
10:15 AM - Q1.3
Low-cost, High Efficiency Solar Cells on Scrapped CMOS Silicon.
Daniel Inns 1 , Joel de Souza 1 , K. Saenger 1 , H. Hovel 1 , D. Sadana 1 Show Abstract
1 T. J. Watson Research Centre, IBM, Yorktown Heights, New York, United States
The cost of scrapped Si from the CMOS industry is extremely low which makes it an attractive material for solar industry. However, the minority carrier lifetime of this material is very low and variable, typically ~ 1 µs compared to the lifetime of the original prime-Si wafer which is > 500 µs. Solar cells made on scrapped wafers therefore result in efficiencies which are inferior to that from a prime CMOS grade Si. We have developed a novel and effective low-cost metal gettering anneal process which allows the minority lifetime of the scrapped wafer to recover to close to its original value, a 100-500 fold increase. Since the efficiency of a solar cell is directly impacted by the minority carrier lifetime, cell efficiency of the improved scrapped Si is nearly equivalent to that from a prime-Si wafer. In order to erase the processing history of the wafer, surface etching is performed to remove ~ 20 µm of surface Si. Following this is a unique impurity gettering step that is performed at > 1300°C with chlorine-containing gas to enable efficient gettering of metals out of the substrate. An efficiency of ~15% has been demonstrated on both prime and improved scrapped wafers using rudimental device design to study the validity of our unique metal gettering process. This efficiency is being improved to much higher values by refinements in device design, anti-reflection coating(s) and surface passivation schemes.
10:30 AM - **Q1.4
Crystalline Silicon Technology for Solar Applications.
Aditya Deshpande 1 , Mike Seacrist 1 , Steve Kimbel 1 , Gang Shi 1 , Jihong Chen 1 Show Abstract
1 , MEMC Electronic Materials, St Peters, Missouri, United States
The use of crystalline silicon in solar applications exceeds the silicon consumed in semiconductor applications. Further, the growth rate of silicon use in solar applications has been higher than the growth rate of use in semiconductor applications over the past several years. Many similarities and synergies exist between manufacturing silicon for semiconductor and solar applications. These include producing polysilicon raw material, growing silicon crystals, and converting crystals into silicon wafers by wire slicing. For these reasons there is a strong motivation for silicon suppliers to participate in the crystalline silicon solar market. Crystalline silicon solar cells are the workhorse of the photovoltaic industry and have a significant portion of the market share of the world production of solar cells. The key driver and challenge for crystalline silicon in solar is cost which is influenced by both the silicon material cost and silicon performance. For silicon to maintain and improve on solar cell market share, further reductions in production cost as well as improvements in solar cell efficiency are necessary. The approach of a vertically integrated silicon supplier to the challenge of improving solar cell efficiency performance while also improving silicon manufacturing productivity and reducing cost will be described. A technical roadmap for crystalline silicon material will be presented and discussed. Key components of the cost are silicon feedstock, crystallization, and slicing. The approaches for commercial production of all these steps will be contrasted with other available methods. The use of directional solidification (DS) methods to grow multi-crystalline silicon (mc-Si) is a large fraction of the crystalline silicon market. The efficiency of mc-Si solar cells is usually lower than for single crystal silicon because of a high degree of material defects that include dislocations, random grain orientations, grain boundaries, impurity precipitates, and inclusions. Typical defects and impurities in mc-Si wafers and their influence on the device performance are reviewed. Detailed characterization of these defects is not straightforward. Methods developed for characterization of these defects will be presented.
11:30 AM - **Q1.5
Developments in Crystalline Silicon-based Photovoltaic Product Architecture and Manufacturing.
Juris Kalejs 1 Show Abstract
1 , American Solar Technologies, Chelmsford, Massachusetts, United States
Solar electric (Photovoltaic) crystalline silicon (c-Si) product diversity has changed very little over three decades of development, including the last decade of unprecedented expansion of the industry. The dominant module product comprising over 90% of cumulative installations, which exceed 15 GW worldwide, still employs an ubiquitous configuration, a platform based on a planar laminate. This paper will review trends in module architecture and manufacturing methods for this currently dominant PV c-Si commodity module platform. The commodity flat-plate module contains typically 60-72 solar cells cut from multicrystalline blocks as 156 mm square areas, or 156 mm dimension pseudo-squares cut from single crystal boules. New module design and manufacturing approaches different from those of the commodity PV product are now in development and piloting. Developments which use innovations in manufacturing processes, i.e., stringing of cells and packaging in a laminate, will be discussed.
12:00 PM - **Q1.6
Contactless Measurement of Carrier Lifetime on As-Grown or Shaped Ingots, Sections, and Blocks.
Ronald Sinton 1 , Tanaya Mankad 1 , M. Forsyth 1 , James Swirhun 1
1 , Sinton Instruments, Inc., Boulder, Colorado, Unit