Minghwei Hong National Tsing Hua University
Wilman Tsai Intel Corporation
Athanasios Dimoulas National Center for Scientific Research “Demokitos”
Peide (Peter) D. Ye Purdue University
A1: High-<i>k</i> Dielectrics
Monday PM, November 30, 2009
Republic A (Sheraton)
9:30 AM - **A1.1
Structural Characteristics of High-k Dielectrics / Semiconductors Heteroepitaxial Systems.
Chia-Hung Hsu 1 2 , J. Kwo 3 Show Abstract
1 Scientific Research Division, National Synchrotron Radiation Research Center, Hsinchu Taiwan, 2 Department of Photonics, National Chiao Tung University, Hsinchu Taiwan, 3 Department of Physics, National Tsing Hua University, Hsinchu Taiwan
The aggressive scaling of Si complementary metal oxide-semiconductor (CMOS) technology has called for alternative high k gate dielectrics to replace conventional gate oxide SiO2 as well as adopting high carrier-mobility semiconductors such as Ge and III-V semiconductors to replace Si. Metal oxides of high dielectric constant are promising candidates of gate dielectrics. One common problem with amorphous dielectrics is polycrystalline formation during postannealing at dopant activation temperature. Grain boundaries so formed within the polycrystalline films act as the leakage channels and seriously degrade the device performance. It is thus desirable to grow single crystal like high k dielectrics to avoid the recrystallization of amorphous gate oxides. It is also known that the dielectric properties of high k thin films are intimately related to the degree of crystallinity, crystal structure, crystallographic orientation, and even strain. A good understanding of the structural characteristics and their influence to the electric performance of high k oxides is critical to the development of future gate dielectrics materials. The structural properties, including crystalline phase, orientation, strain, and defect structures of various ultra-thin high k oxide epi-films grown on semiconductors, such as Si, GaAs, and GaN will be presented.
10:00 AM - A1.2
Tetragonal Phase in Ge Doped HfO2 Films on Si Investigated by X-ray Absorption Spectroscopy.
Leonardo Miotti 1 , Karen Paz Bastos 1 , Gerald Lucovsky 1 Show Abstract
1 Department of Physics, North Carolina State University, Raleigh, North Carolina, United States
High-κ dielectric materials have been the focus of research for more than a decade and since then the most promising dielectrics for future metal-oxide-semiconductor (MOS) devices are HfO2 and other Hf based dielectrics. HfO2 films form nanocrystallites of mixed phases after deposition on Si, or on alternative high carrier mobility substrates, and thermal processing. The ability to stabilize the tetragonal phase of HfO2 is of technological importance because this phase has a significantly higher dielectric constant (κ~30-35) as compared to the mixed monoclinic-tetragonal films (κ~16-20). Stabilization of the tetragonal phase can be achieved by doping the HfO2. The most common dopant studied is trivalent yttrium, which has associated oxygen vacancies in HfO2. Here, we report the investigation of tetravalent Ge doping of HfO2 thin films and its effect on the stabilization of a higher dielectric constant phase of HfO2. Hafnium oxide films were deposited on Si(100) by remote plasma enhanced chemical vapor deposition using Hf-t-butoxide, GeH4, and O2 as reactive gases. Films were deposited with Ge concentration in the 0 to 15 at. % range, as determined by Auger electron spectroscopy. To access the local symmetry in 2 and 5 nm thick films we used O K edge x-ray absorption spectroscopy (XAS). We also investigated the electronic states in the vicinity the conduction band edge by spectroscopic ellipsometry (SE) and compared these results with those of monoclinic HfO2 films deposited on Ge(100) after annealing to 800°C.The XAS spectrum of undoped 5 nm thick HfO2 film on Si shows that the monoclinic phase is predominant phase after RTA at 750°C. After the same thermal budget, doping with 5 at.% of Ge stabilizes the tetragonal phase. The effect of increasing doping is mainly to reduce the local symmetry, as can be associated to the broadening of the XAS spectral features. In contrast to these results, the XAS spectra for 2 nm thick films do not reveal a well defined symmetry after RTA, neither in the undoped case. This effect can be associated to the suppression of the Jahn-Teller distortion by the reduced film thickness, which is lower than the characteristic scale of order of Jahn-Teller effect in HfO2 (~ 2.5 nm).
10:15 AM - A1.3
Effect of La and Al Doping on the Band Alignment at the SiO2 /HfO2 Interface.
Xuhui Luo 1 , Alex Demkov 1 Show Abstract
1 Department of Physics , University of Texas at Austin, Austin, Texas, United States
Following the introduction of HfO2-based high-k gate stack in Si field effect transistors, hafnia is now also considered as a possible gate dielectric in high-mobility channel devices. Si is often used to passivate surface states of the high-mobility channel materials. Therefore the HfO2/SiO2 interface needs to be understood when considering the overall gate stack band alignment. The use of HfO2 requires employing a metal gate electrode, and controlling the overall band alignment in the gate stack is important for controlling transistor threshold voltage. To help engineering the stack composition in order to control the band alignment we investigate theoretically the effects of Al and La incorporation in the HfO2 /SiO2 gate stack. We find that oxygen vacancies are stabilized in the vicinity of substitutional metal atoms in the SiO2 interfacial layer in the case of Al doping. However, the vacancies prefer to be in the HfO2 interfacial layer when doping with La. We find that metal interstitial atoms form stable metal-vacancy complexes in the vicinity of the HfO2/SiO2 interface. We show that La incorporation at the interface increases the valence band offset while Al incorporation decreases it. We compare our results with available experiment and provide explanation for the effects of doping on the band alignment.
10:30 AM - A1.4
Rare-earth Oxide Thin Films for High-k Dielectric by Atomic Layer Deposition.
Jun-Jieh Wang 1 , Venkateswara Pallem 1 , Christian Dussarrat 1 Show Abstract
1 , American Air Liquide, Inc., Newark, Delaware, United States
Beyond hafnium silicates, rare earth metal-based oxides are considered the next generation material for critical high-k films in electronic devices. A number of organolanthanide complexes are synthesized as sources (“precursors”) of metal or metal oxide layers for semiconductors. Under requirement of the semiconductor manufacturing process, these precursors have to perform particular physical and thermal properties such as high volatility, high reactivity, and high thermal stability. Recently, rare earth compounds containing cyclopentadienyl (Cp) ligands are introduced as precursors with optimized physical and chemical properties: relatively high vapor pressures, liquid or low melting point solid, high reactivity towards water, and high growth rates for deposition. Atomic layer deposition (ALD) is the preferred deposition technique to achieve precise control of film thickness and uniformity, with a possible control on the crystal structure grown depending on the experimental conditions. In our study, many different rare earth (Sc, Y, La, Ce, Er, Gd, Dy, Yb, Lu) oxide films are deposited from Cp-containing metal precursors by atomic layer deposition technique, and their physical and thermal properties are thoroughly examined. All of them are found high-k and high thermal stability, and are considered valuable material to future semiconductor industry.
10:45 AM - A1.5
Photoelectron Spectroscopy Study of Rare-Earth Oxide Films Deposited by Atomic Layer Deposition.
Conan Weiland 1 , Nicholas Lorenz 1 , Robert Opila 1 Show Abstract
1 Materials Science and Engineering, University of Delaware, Newark, Delaware, United States
High dielectric constant, or high-k films are currently being employed in semiconductor devices. To further extend Moore’s law, new, “higher-K” oxides, such as the lanthanides, must be used. Many challenges face the industry in implementing these materials in devices. Films must be free of defects, as these defects can create pathways for leakage current through the film. The oxide/silicon interface must also be free of defects – which can create charge centers which decrease channel mobility – as well as any SiO2 interlayer, which lowers the effective dielectric constant of the device. This work studies multiple photoelectron-spectroscopy techniques to probe the quality of film and interface of rare-earth oxides deposited by atomic layer deposition (ALD).Non destructive depth profiles of films are collected using angle-resolved XPS (ARXPS) and hard X-ray XPS (HAXPES). In ARXPS, the effective probe depth is varied by changing the takeoff angle between surface and detector. As a complementary technique, HAXPES provides depth profiles by adjusting the incident X-ray energy, and thus the corresponding inelastic mean free path of the photoemitted electrons. HAXPES also allows the ability to probe deeper into films than conventional lab-based sources, providing the possibility of analyzing thicker films. Using these techniques, we analyze the composition of several rare-earth oxide films, such as Yb2O3, Er2O3 and others, as well as determine the presence and thickness of interfacial SiO2 layers. The interface quality of these films is also probed using XPS. The presence of charge at the interface manifests itself as shifts in the energy of the photoelectron peaks. Using this data, we can determine charge at the high-k/silicon interface as well as measure band offsets.
Monday PM, November 30, 2009
Republic A (Sheraton)
11:30 AM - **A2.1
Performance Comparison of Si and III-V MOSFETs beyond the 15nm Node.
Mark Lundstrom 1 , Yang Liu 1 , Himadri Pal 1 , Mathieu Luisier 1 Show Abstract
1 ECE, Purdue, West Lafayette, Indiana, United States
The gate length scaling of Si MOSFETs according to Moore’s law has been accompanied by a proportional reduction of the power supply voltage Vdd till the 90nm technology node, where the decrease of Vdd has started to slow down. Hence, the ITRS predicts that Vdd will amount to 1 V in high performance logic at the 15nm node (probably Si-based), resulting in high power dissipation. Beyond the 15nm node, alternative materials are investigated to fabricate low power MOSFETs. The extraordinary electron transport properties of III-V compound semiconductors like InGaAs make them promising candidates to replace conventional Si MOSFETs in low power and high frequency logic applications. The integration of III-V semiconductors into the active region of future MOSFETs is mainly driven by the idea that the extremely high electron mobility of these materials, as compared to Si, will lead to high-speed transistors with very low supply voltages. Many technology issues have to be addressed before III-V MOSFETs can challenge state-of-the-art Si MOSFETs, like the deposition of a high-κ dielectric layer on top of the III-V channel, the doping of the source and drain contacts, the integration of III-V on a Si substrate, as well as the reduction of the parasitic source/drain series resistance. Assuming that these problems will be solved, we use numerical simulations to compare the performances of single- and double-gate, ultra-thin-body Si and InxGa1-xAs MOSFETs with a gate length of 10nm. The subthreshold slope, the DIBL, the ON and OFF currents, the transconductance, and the intrinsic delay of these transistors are simulated in the ballistic limit using a 2-D Schrödinger-Poisson solver with effective masses imported from accurate tight-binding calculations. This approach, which has been benchmarked against recent experimental results, provides realistic estimates of the maximum performance benefits that can be expected from the use of III-V channel materials.
12:00 PM - A2.2
Quantum Simulation of C-V and I-V Characteristics in Ge and III-V Materials/High-κ MOS Devices.
Mathieu Moreau 1 , Daniela Munteanu 1 , Jean-Luc Autran 1 2 , Florence Bellenger 3 , Jerome Mitard 3 , Michel Houssa 4 Show Abstract
1 , IM2NP-CNRS, Marseille France, 2 , IUF, Paris France, 3 , IMEC, Leuven Belgium, 4 , K. U. Leuven, Leuven Belgium
In order to improve CMOS performances for future technological nodes, i.e. increase the on-state current while reducing the gate leakage current, high mobility materials (Ge and III-V materials) integrated with high-κ gate dielectrics and metal gate have been recently considered to replace the traditional poly-Si/SiO2/Si gate stack. The realization of these new MOSFETs implies some technological integration problems but also simulation difficulties of electrical characteristics due to the complex gate stack. In this context, we developed a one-dimensional (1-D) numerical simulation code for the calculation of the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of MIS devices with high mobility materials (Ge and III-V materials like GaAs, InAs, InSb) and non-conventional gate stack (interfacial layer + high-κ layer).Our quantum simulation code self-consistently solves the Schrödinger and Poisson equations using finite-difference method with a non-uniform mesh size. The resulting quantum carrier density in the substrate is used for calculating the low and high-frequency capacitance of the structure. The electron transport through the gate stack is treated using the non-equilibrium Green’s function formalism (NEGF) adapted to the case of an effective-mass depending on the position along a 1-D grid in the transport direction. This method takes into account carrier wave-function reflections on the energy potential barrier (usually neglected in classical calculation) to precisely predict C-V and I-V characteristics in arbitrary multi-layered high-κ dielectric gate stacks. The C-V simulation code is validated on experimental data for classical SiO2/Si devices and is successfully used to simulate several MIS structures, such as HfO2/n-Ge or Al2O3/GeO2/p-Ge. The simulation results are confronted to experimental data for various MIS structures with different semiconductors and dielectric stacks. We also use the code to simulate the electron transport through the gate stack. A preliminary study concerns metal-insulator-metal (MIM) capacitors with multi-layer high-κ dielectric gate stack. Quantum simulation shows that conduction band offset between oxides induces wave-function reflections against barrier discontinuities which strongly modify the electron transport and thus the gate leakage current, especially in double-layer high-κ dielectric gate stacks. These quantum reflections cannot be taken into account in classical calculation approaches, such as the Wentzel-Kramers-Brillouin (WKB) approximation. The detailed study of various high-κ dielectric gate stacks highlights that the gate leakage current highly depends on material properties (such as dielectric constant, effective mass and conduction band offset) but also on the interfacial oxide (SiO2) layer thickness.
12:15 PM - A2.3
Physics of Polymorphic Silicide Interfaces; First-principles Study of Stability, Doping, and Schottky Barrier.
Takashi Nakayama 1 , Shinichi Sotome 1 Show Abstract
1 Physics Department, Chiba University, Chiba Japan
As promising candidates for gate/source/drain metals in next-generation Si devices such as Si nanowires, a variety of silicides have again attracted intensive attentions in these days. However, there remain many elementary questions concerning the stability and electronic properties of silicide systems : why some metal atoms such as Ni produce bulk silicides and the others like Au never produce silicides, why silicides with some stoichiometry are difficult to grow at silicide/Si interfaces, why Schottky barrier for electrons simply decreases as the Si ratio in silicides increases, and what changes occurs when silicides are intentionally doped. The purpose of this work is to answer these questions, especially to clarify the “silicide physics”, using the standard first-principles theoretical calculations based on the density functional theory. We adopted the repeated unit cell to simulate the interface. Answers to the above questions are summarized as follows: (1) By analyzing band structures and electron distributions, it is shown that the stability of metal silicides is realized by the energy gain caused by the electron transfer from occupied p-orbital states of Si to unoccupied d-orbital states of transition-metal atoms. This stabilization scenario well explains why transition-metal atoms produce stable silicide phases except Au and Ag and why Al atom having no d-orbital states never produces silicides. (2) By calculating phase diagrams, we can show that a variety of MxSiy phases (M=metal atom) with (x,y)=(1,2), (1,1), (2,1), and (3,1) stoichiometries are realized in the bulk growth, while the (3,1) phase becomes difficult to grow on the Si substrate. Such instability occurs due to the energy losses by the elastic strain and the interface bonding. (3) Reflecting the electron transfer from Si to metal atoms, the work function of silicides decreases as the ratio (y) of Si in MxSiy increases, being in good agreement with a number of observations at silicide/oxide interfaces. Correspondingly, when the B (P) atoms are highly doped into Si sites of silicides, the work function largely increases (decreases), which reasonably explains the recent experiments of doping-induced work-function modulation at silicide/high-k interfaces . These results are discussed in details. This work is supported by MEXT, Selete, ISSP, and GCOE, Japan.  T. Nakayama et al, Microelectronic Engineering 86 (2009) 1718.  K. Manabe et al, VLSI Tech.(2006) p.46.
12:30 PM - A2.4
Simulations of Short-channel Effects and Interface Traps in In0.75Ga0.25As MOSFET with ALD Al2O3 as Gate Dielectric.
Ozhan Koybasi 1 , Yanqing Wu 1 , Min Xu 1 , Peide Ye 1 Show Abstract
1 Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana, United States
In0.75Ga0.25As inversion-type enhancement-mode n-channel MOSFETs with ALD grown Al2O3 as high-k gate dielectric have shown promising results . A maximum drain current of 925 µA/µm and a peak transconductance of 700 µS/µm have been attained at VDD =1.6V at 150 nm gate length device. At the foregoing channel lengths and below, the major challenge is to come up with an optimized device design that minimizes the undesired short channel effects, which are mainly characterized by scaling metrics such as sub-threshold slope, drain-induced barrier lowering (DIBL), on-current/off-current ratios. The manifestations of the short-channel effects on the device characteristics include the shift of threshold voltage to negative voltage, an increase in subthreshold current and subthreshold slope, an increasing drain current with drain voltage in the “saturation region” of the drain characteristics unlike the long-channel devices where the drain current saturates, and a reduced transconductance in the saturation mode. Electrical simulations with the simulation package SYNOPSYS MEDICI have been carried out to investigate the impact of device parameters such as source/drain doping, source/drain depth, substrate doping, oxide thickness, etc., on the performance of short-channel devices. Moreover, as an intervening layer of a wide band gap material underneath the channel region helps reduce the short-channel effects, the highest band gap after which the improvement on short-channel effects ceases has been simulated. The degrading effects of interface traps on the operational behavior of MOS structures have been simulated as well. The interface traps , which are characterized by their density, energy distribution and type (donor-like or acceptor-like), manifest themselves as a stretch out in the C-V characteristics of MOS capacitors and an increase in the subthreshold slope in the transfer characteristics of MOSFETs. In literature, most discussions on interface traps are based on the assumption that a trap neutral energy level exists. Various trap distributions with different trap neutral levels and their effect on the CV characteristics of MOS capacitors and the I-V behavior of MOSFETs are discussed.
12:45 PM - A2.5
Large-Scale Modeling of GeO2/Ge and SiO2/Si Interface Structures.
Tomoya Onda 1 , Hideaki Yamamoto 1 , Ryo Tosaka 1 , Takanobu Watanabe 1 Show Abstract
1 , Waseda university, Japan, Tokyo Japan
Ge CMOS has been of increasing interest as a promising candidate for future electronic device over the scaling limit of Si technology. It is necessary to understand the atomistic picture of GeO2/Ge interface accurately. In this work, we performed large-scale molecular dynamics simulations on GeO2/Ge interface by using newly developed interatomic potential function for Ge, O mixed systems. We modeled also a SiO2/Si structure with almost the same size as the GeO2/Ge structure to compare both interface structures. In order to investigate the substrate orientation dependence of the interface structure, GeO2/Ge(001), GeO2/Ge(110), GeO2/Ge(111), SiO2/Si(001), SiO2/Si(110), and SiO2/Si(111) was fabricated.The potential function for Ge, O systems is designed by extending an existing potential function for Si, O systems which was developed in our previous work. The binding energies and distortion energies of bond angles in the Ge, O systems is smaller than corresponding bonds and angles in the Si, O system as a whole, but only a Ge-O-Ge bridging oxygen angle is found to be harder than a Si-O-Si angle, and has a narrower equilibrium angle of 133° than that of Si-O-Si of 144°. Using these interatomic potential functions, we have modeled GeO2/Ge and SiO2/Si interface structures. The result shows that the oxidation-induced strain is weaker in the GeO2 film than in the SiO2 film, regardless of the substrate orientation type. In addition, the defect density at the GeO2/Ge interface was lower than at the SiO2/Si interface. These results indicate that the GeO2/Ge interface structure has superior interfacial properties to the SiO2/Si interface structure, regardless of the substrate orientation. This is qualitatively agreeing with the recent experimental results, the minimum interface trap density value could be obtained for GeO2/Ge MOS interface fabricated by direct oxidation of Ge substrates. The reason for the superiority of GeO2 film is attributed to the following two facts. (i) The binding energies and distortion energies of bond angles in the Ge, O systems are weaker than those in the Si, O systems on the whole. (ii) GeO2 film has a smaller lattice mismatch with the substrate than the SiO2 film because the equilibrium angle of the Ge-O-Ge bridging oxigen bond is smaller than that of the Si-O-Si bond. These results are in agreement with the recent report that a better stress relaxation at/near the GeO2/Ge interface is owing to the viscoelastic properties of the GeO2 .  T. Watanabe et al ., Jpn. J. Appl. Phys. 38 (1999) L366.  H. Matsubara et al ., Appl. Phys. Lett. 93 (2008) 032104.  M. Houssa et al ., Appl. Phys. Lett. 93 (2008) 161909.
Monday PM, November 30, 2009
Republic A (Sheraton)
2:30 PM - **A3.1
Enhancement-mode Inversion-channel and Depletion-mode GaN MOSFETs using Atomic-layer-deposited Al2O3 and HfO2 as Gate Dielectrics.
Yao-Chung Chang 1 , Wen-Hsin Chang 1 , Yu-Hsing Chang 1 , Raynien Kwo 2 , James M. Hong 3 , Jacky C. C. Tsai 3 , Minghwei Hong 1 Show Abstract
1 Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu Taiwan, 2 Department of Physics, National Tsing Hua University , Hsinchu Taiwan, 3 , HUGA Optotech Inc., Taichung Taiwan
GaN, with a high saturation drift velocity at high electrical fields (νsat~3×107 cm/s), a high critical electrical field, good thermal conductivity, and epi-layers grown on Si, has been widely studied for applications in high-speed, high-power, and high-temperature devices. Compared to conventional AlGaN/GaN high-electron-mobility-transistors (HEMTs), GaN metal-oxide-semiconductor field-effect-transistors (MOSFETs) feature a larger voltage sweep range, lower gate leakage currents, more uniform threshold voltage, and circuit simplicity, and hence have attracted much interest lately. Owing to its wider energy band gap (3.4 eV) which alleviates the adverse affects like drain-induced barrier lowering (DIBL) and band-to-band tunneling (BTBT), GaN is now also being considered as a channel candidate for the next generation complementary MOS (CMOS) devices beyond the 16nm node technology. Furthermore, by taking into account of the short channel effect with the cutoff frequency (fT) given by fT=νsat/2πLg (where Lg is the gate length), GaN MOSFETs may outperform its counterparts of Si and GaAs in further scaled-down devices, despite the fact that GaN offers no special advantage in electron mobility. In the past few years, high-performance enhancement-mode (E-mode) inversion-channel and depletion-mode (D-mode) GaN MOSFETs using atomic-layer-deposited (ALD) Al2O3 and HfO2 as gate dielectrics have been demonstrated; for example, a 4μm gate length D-mode GaN MOSFET with HfO2 gate dielectric exhibits a maximum drain current of 230 mA/mm, low on-resistance of 4.5 mΩ.cm2, a maximum transconductance of 31mS/mm, and a high mobility of 400 cm2/Vs (μn=Gm(Lg/Wg)/NdTch). Compared to the previously reported GaN-based MOSFETs and HEMTs, these D-mode devices demonstrate excellent dc output as well as transfer characteristics, in terms of high drain currents, large gate voltage sweep ranges with very low gate leakage currents, and absences of current collapse. Well-behaved drain I-V characteristics of an inversion-channel GaN MOSFET with ALD high-κ gate dielectrics have also been obtained. These E-mode devices show very low off-state currents of about 10-13A/μm and clean pinch-off behavior. The maximum drain current and peak transconductance of Al2O3/GaN MOSFETs are about 3.5 mA/mm and 4mS/mm in a 4 μm gate length device, respectively. The overall performances of these devices are markedly improved over the previously reported results of the inversion-channel GaN MOSFETs based on other high-κ dielectrics. The D-mode and inversion-channel device performances of ALD-Al2O3 and -HfO2/ GaN have established the hetero-structures for CMOS, power-switching, and high-temperature applications.
3:00 PM - A3.2
Electrical and Interfacial Studies of HfO2 Thin Films as high k Metal Gate Dielectric Layer on SiC Devices.
Shiva Hullavarad 1 , Nilima Hullavarad 1 Show Abstract
1 Office of Electronic Miniaturization, University of Alaska Fairbanks, Fairbanks, Alaska, United States
High k dielectric metal oxide films have attracted much attention as promising candidates for the forthcoming gate dielectric materials of metal oxide field effect transistors, in place of SiO2 films . The use of high –k/metal gate technology will provide cost, performance and power savings. To increase the capacitance while reducing the tunneling current, various kinds of high dielectric materials have been investigated as possible alternatives to SiO2. Owing to handle high critical electric field, electron saturation velocity and thermal conductivity SiC has advantages over Si, quantitatively put together 186 times better than Si. In this work, we studied the low leakage electrical properties of HfO2 thin films on p-SiC. The bandgap of HfO2 thin films was observed to be 5.8 eV. The chemical nature and stoichiometry of the films were analyzed by X-Ray Photoelectron spectroscopy. Metal-Insulator-Semiconductor structures (TiN/SiC/HfO2/Ni) with Ni as a top electrode and TiN as a bottom electrode were fabricated to study the leakage current properties. The devices exhibited leakage current density of 50 nA/cm2. The leakage properties of the MIS junctions are studied for elevated temperatures in the range of 50-400C to demonstrate the thermal stability of HfO2 dielectric film. The dielectric constant of these films is estimated to be in the range of 17-24 from C-V measurements. The frequency dependence of the interface trapped charges is studied. We will also present results on the conformal deposition of HfO2 films for device passivation for the uniform 3-D coverage owing to its excellent dielectric and thermal stability properties. High k Dielectrics, Edited by M. Houssa, Institute of Physics Publishing, 2004
3:15 PM - A3.3
Physical and Electrical Interface Structure of Crystalline Oxides on GaN.
Fred Walker 1 , A. Posadas 1 , C. F. Vaz 1 , V. Henrich 1 , C. Ahn 1 Show Abstract
1 Center for Research on Interface Structure and Phenomena, Yale University, New Haven, Connecticut, United States
Achieving high mobilities at semiconductor-oxide interfaces depends critically on both electronic and physical structure. In this work, we study the mobility of crystalline MgO/GaN structures. For MgO grown by molecular beam epitaxy using metal sources and atomic oxygen from an RF plasma source, high quality (111) oriented MgO can be achieved. Substrate surface preparation is a key element for controlling interface state density and leakage current in this system. For films with low leakage currents, the breakdown field is > 7 MV/cm. In this talk, we discuss our approach to preparing carbon-free surfaces for epitaxy, with feedback from surface and interface characterization using capacitance-voltage measurements, atomic force microscopy, and synchrotron x-ray scattering. When carbon is eliminated from the starting substrate surface, the interface state density can be reduced to less than 6x1011 cm-2eV-1.
3:30 PM - A3.4
The Importance of Chemical Bonding and Crystal Symmetry at the Heteroepitaxial Interface Between Oxides Epilayers and Gallium Nitride Surfaces.
Mark Losego 1 , Lena Fitting Kourkoutis 2 , Ramon Collazo 1 , Seiji Mita 1 , David Muller 2 , Zlatko Sitar 1 , Jon-Paul Maria 1 Show Abstract
1 Materials Science and Engineering, North Carolina State University, Raleigh, North Carolina, United States, 2 Materials Science and Engineering, Cornell University, Ithaca, New York, United States
Heteroepitaxy of oxides on gallium nitride (GaN) is attractive for traditional solid-state device structures like dielectric gates and high-mobility channel passivation as well as for the integration of high-performance functional oxides like ferroelectrics and ferromagnets. A fundamental understanding of the epitaxial growth process at this oxide / nitride heterojunction is therefore critical to achieving optimal device performance. Herein, we discuss the interfacial structure of rocksalt (MgO, CaO) and perovskite ((Ba,Sr)TiO3) epilayers grown on (0001) GaN surfaces. Based on the observed in-plane orientation of these epilayers, we hypothesis that interfacial bond ionicity plays a more significant role than misfit strain in determining the epitaxial alignment. For example, (Ba,Sr)TiO3 chooses an in-plane orientation having 14% lattice mismatch rather than an orientation with only 1.3% lattice mismatch because of the difference in bonding environment (the former being more ionic than the latter). Based on previous observations of alkali halide epilayers on ionic solid and covalent solid substrates, we conclude that the Ga-O bond ionicity is sufficient for forming an ionic solid like interface in oxide / GaN heterostructures. The influence of ionic bonding across the oxide / nitride interface is also evident in the immediate (a single monolayer) structural relaxation of misfit strain observed in scanning transmission electron microscopy images taken of the MgO / GaN interface. Symmetry also plays an important role in such systems where a cubic oxide is being deposited on a hexagonal nitride substrate. Because of their difference in symmetry, two structural variants must nucleate resulting in the formation of twin boundaries throughout the oxide epilayer. Eliminating these twin boundaries and achieving 2D growth remains the most significant challenge for integrating oxide epilayers on GaN. The role of interfacial bond ionicity on film epitaxy will be summarized in terms of its impact on materials selection and the nucleation of epitaxial variants that lead to twinning in cubic oxide epilayers grown on GaN.
3:45 PM - A3.5
Interface Structure of Epitaxially Deposited La2O3 and Sc2O3 Dielectrics on Gallium Nitride for MOS Applications.
Mark Johnson 1 , Virginia Wheeler 1 , Dan Lichtenwalner 1 , Matt Veety 1 , Doug Barlage 1 Show Abstract
1 , North Carolina State University, Raleigh, North Carolina, United States
Processes for the formation of insulating dielectrics on III-Nitrides, which exhibit a low density of interface related energy state, have become of critical need for power and nanoscaled metal oxide semiconductor field effect transistors (MOSFETs). Of particular interest are epitaxially deposited oxides which exhibit suitable band offsets energies for MOSFET devices. Based on their expected relatively low coherency mismatch, La2O3 and Sc2O3 oxides have been deposited using Molecular Beam Epitaxy on Gallium Nitride. The GaN layers were all prepared by metal-organic chemical vapor deposition, with an acid surface preparation before oxide deposition to ensure a consistent surface termination. Following MBE deposition, test structures were investigated using x-ray diffraction, transmission electron microsopy, and X-ray photoelectron spectroscopy, as well as subsequently fabricated into MOS capacitor test structures. X-ray diffraction and in-situ RHEED during growth of the 10nm-30nmthick layers of Sc2O3 on GaN are consistent with cubic Bixbyite oxide phase with in-plane twinning. TEM if these samples showed a strained, atomically abrupt interface with no interfacial reaction layer. The Sc2O3 structure does contain twinning, with boundaries perpendicular to the MOS interface with 5-50nm spacing. Detailed analysis of these twin boundaries, and twin-boundary termination will be provided. XPS measurements indicate a Type-I interface with a 0.7eV conduction band offset. By comparison, the La2O3 on GaN samples showed the presence of both hexagonal and cubic phases by x-ray diffraction, although interpretation of thin film structure may be complicated by the possible formation of a hydroxide layer with La2O3. In-situ RHEED indicated a 2-D crystalline surface for epitaxially deposited La2O3. TEM clearly exhibited a thin (~1nm) coherent interfacial layer followed by a defective, highly oriented polycrystalline, layer of La2O3. Detailed investigation of the structure of individual crystalline domains, and the boundary between domains will be provided. XPS measurements indicate a Type-I interface with a 0.9 eV conduction band offset. The MOSCAP test structures with 10nm oxide thicknesses and exhibited 2 micro-F/cm2 for Sc2O3 and 3 micro-F/cm2 for La2O3 respectively. MOS leakage current densities less than 5E-3 A/cm2 have been achieved for 5nm thick MOS structures, Flat-band voltages >2V provide a basis for normally-off MOSFET devices for power and scaled logic using these epitaxial oxides on Gallium Nitride.
A4: Substrates and Devices
Monday PM, November 30, 2009
Republic A (Sheraton)
4:30 PM - **A4.1
High Performance Scaled Alternative Channel MOSFETs with High Carrier Injection Velocities
Raj Jammy 1 , Jungwoo Oh 1 , Niti Goel 1 , Injo Ok 1 , Jeff Huang 1 , Prashant Majhi 1 , Paul Kirsch 1 Show Abstract
1 , SEMATECH, Austin, Texas, United States
Transistors are increasingly dependent upon channel strain for mobility and drive current enhancement. Various strain engineering techniques, such as contact etch stop liner (CESL), strained SiGe or SiC in the source and drain regions, and stress memorization technique (SMT), have demonstrated higher carrier mobility for CMOS transistors. However, as the pitch dimension scales down beyond 32nm technology node devices, mobility and drive current enhancement afforded by local strain engineering are becoming less effective, but such highly scaled MOSFETs operate under quasi-ballistic regime. In this regime, the drive current and mobility are governed by the injection velocity in the channel. Germanium and III-V channel transistors potentially offer high injection velocity due to their high transport characteristics over Si channels. SiGe pMOSFETs with strained quantum wells (QWs) in the Si–Ge system exhibit high performance and low off-state leakage currents comparable to optimized gate stacks on Si. The encouraging results were due to selectively depositing Si–Si(x)Ge(1−x)-Si heterostructures QWs. High drain current is obtained in optimized Si caps on the SiGe channel when carrier transport on the high transport SiGe channel and the Si cap serves as a passivation layer. pMOSFETs with strained QWs in the Si-Ge system exhibit high performance and low off-state leakage comparable to optimized gate stacks on Si. Si–Si(x)Ge(1−x)-Si QWs have (i) low band-to-band tunneling current despite having a small bandgap (ii) low interface state density, and (iii) significant additional mobility enhancements under compressive uniaxial stress. For SiGe pMOSFETs, drive current increases as Ge % increases in the channel due to enhanced hole mobility. For SiGe nMOSFETs, however, drive current decreases dramatically as Ge % increases. A comparative study was conducted to understand low drive current of Ge-based nMOSFET. The poor electron transport property is primarily attributed to the intrinsically low density of state and high conductivity effective masses. For high performance nMOSFETs, a normalized power-delay benchmarking clearly shows the advantage of III-V channels over strained-Si and SiGe devices. Recent work on short gate length HEMT devices emphasizes the potential of InGaAs based III-V channels. However, for III-V to truly be viable, one must address key grand challenges, one of them being gate stacks. For sub 22 nm nodes the highly scaled gate length would require very low effective oxide thickness to maintain electrostatic control of the devices while demonstrating performance advantage over incumbent strained Si devices. To increase channel mobility and injection velocity further, local strain induced scaled Ge or III-V channels can be employed with significantly higher carrier injection velocities and consequently high performance at low operating voltages are expected.
5:00 PM - A4.2
Stress Liner Proximity Technique to Enhance Carrier Mobility in High-K Metal Gate MOSFETs.
Dechao Guo 1 , Kathryn Schonenberg 2 , Jie Chen 3 , Daniel Jaeger 2 , Pranita Kulkarni 1 , Unoh Kwon 2 , Yue Liang 2 , Joyce Liu 2 , Liyang Song 2 , Franck Arnaud 4 , Huiming Bu 1 , Michael Chudzik 2 , William Henson 2 , Philip Oldiges 2 , Melanie Sherony 2 , An Steegan 2 , Voon-Yew Thean 2 , Mukesh Khare 1 Show Abstract
1 , IBM T.J. Watson Research Center, Yorktown Heights, New York, United States, 2 , IBM Semiconductor Research and Develeopment Center, Hopewell Junction, New York, United States, 3 , Chartered Semiconductor Manufacturing, Hopewell Junction, New York, United States, 4 , STMicroelectronics, Hopewell Junction, New York, United States
High-κ/metal gate (HK/MG) technology is proved to resume the scaling trend down to 25nm gate length. Recent publications have demonstrated the compatibility of DSL, embedded SiGe, and stress memorization technique with HK/MG technology. For the first time, we discuss the compatibility of stress proximity technique (SPT) with dual stress liner (DSL) in HK/MG technology in a gate-first process flow.It is known that the thermal budget in the CMOS process flow could cause threshold voltage shifts and re-growth in HK/MG devices. Therefore, in a gate-first process flow, spacers are critical to encapsulate the HK/MG stack to prevent any impact from the thermal instability. However, the SPT process utilizes the spacer removal to enhance the stress and carrier mobility. This work presents a spacer integration scheme and SPT process to achieve the strain enhancement, drive current improvement along with maintained threshold voltage and short channel control, in a gate-first HK/MG process flow.In a gate-first HK/MG process flow, a thin layer of high quality SiN spacer, Spacer0, is immediately deposited after PC line definition. Spacer0 is thick enough to protect HK/MG stack, and thin enough to introduce embedded SiGe with close proximity for high channel strain. Oxide spacer, Spacer1, is deposited to facilitate halo/extension implant. The final SiN spacer, Spacer2, is necessary for S/D implant and salicidation. SPT is carried out after the S/D salicidation process to remove Spacer2, followed by DSL process. In the SPT+DSL process, one kind transistor experiences RIE process once; while the other kind transistor twice. The spacer removal process in SPT and the liner removal process in DSL have to be optimized accordingly to minimize the damage to Spacer0, Spacer1, and silicide. By implementing SPT at 32nm node, nFET Idsat is improved by 7% at Ioff=200nA/um, compared to the control sample with DSL only process. By applying the short channel mobility extraction technique, it is verified that the SPT process provides approximately 13% electron mobility enhancement, which is responsible for the above 7% Idsat improvement. In the tensile-liner-first DSL scheme, pFET has to experience both SPT RIE and tensile liner RIE processes. Un-optimized SPT+DSL could lead to damages to the HK/MG stack and silicide, resulting in as much as 33% Idsat reduction. Through the optimization of SPT RIE and tensile liner RIE, approximately 7% Idsat improvement has been achieved on both nFET and pFET, together with well controlled short channel effect. In summary, integration of SPT for DSL is demonstrated on a gate-first HK/MG process flow down to 32nm node, without introducing additional process complexity in the integration scheme. Both nFET and pFET achieve approximately 7% Idsat improvement simultaneously. Meanwhile, short channel control, the integrity of HK/MG stack and its critical protection spacers are well preserved.
5:15 PM - A4.3
Channel Strain Analysis in Damascene-gate pMOSFETs on Si (100) and (110) Substrates by Plane and Cross-sectional Raman Measurements.
Munehisa Takei 1 , Daisuke Kosemura 1 , Kohki Nagata 1 , Hiroaki Akamatsu 1 , Satoru Mayuzumi 2 1 , Shinya Yamakawa 2 , Hitoshi Wakabayashi 2 , Atsushi Ogura 1 Show Abstract
1 School of Science and Technology, Meiji University, Kawasaki Japan, 2 Atsugi Tec, Sony Corporation, Atsugi Japan
Channel strain profiles in damascene gate pMOSFETs with compressive stress liner (c-SL) and embedded SiGe (eSiGe) were studied by micro-Raman spectroscopy with a quasi-line-shape UV excitation (λ=363.8nm), optical com-ponents of monochromator were installed on the Super Invar metal whose thermal coefficient is extremely small. The damascene gate pMOSFETs were fabricated on Si (100) or (110) substrate. The 80 nm eSiGe epitaxial growth was carried out after Si recess for some samples. The 40 nm compressive stress liner with the inner stress of - 2.0 GPa was deposited after Ni silicidation. Only the c-SL above the dummy gate was cut by CMP, and the dummy gate was removed. After the dummy gate removal process, metal-gate and high-k film were formed with TiN and ALD-HfO2, respectively. We prepared two kinds of samples. The first was damascene gate pMOSFET after the dummy gate removal process. The second was damascene gate pMOSFET after metal-gate/high-k gate stack formation. The channel strain profiles for damas-cene gate pMOSFETs were obtained by the plane and the cross sectional Raman measurements. The plane Raman measurement was carried out in the backscattering geometry from the (100) and (110) surface of the pMOSFETs. However, because the metal-gate was not transparent, the evaluation of the channel strain by Raman spectroscopy has been difficult for the samples with the metal-gate. So then, the evaluation was performed only by the cross sectional Raman measurement. As results, the channel strain profiles obtained by the plane Raman measurement after dummy gate removal, the compressive strains at the channel edges were larger than those at the channel center for the relatively long gate length (Lgate). As the Lgate become smaller, the compressive strain at the channel center was enhanced by the superposition of the strain at the channel edges. Finally, we have succeeded in measuring the extremely large stress of - 2.4 GPa in the channel of Lgate = 30 nm pMOSFET. Then we also performed the cross sectional Raman measurement for the samples before and after metal-gate/high-k gate stacks formation. We observed that the compressive strains at the channel edges were larger than those at the channel center for the long Lgate, and the larger compressive strain in the channel center for the smaller Lgate. These strain profiles were similar to the result which was obtained by the plane Raman measurement. Thus, we point out that the significantly large strain in the damascene-gate pMOSFET was pre-served even after gate stack formation. We consider that the extremely high device performance was clearly explained by the compressive stress calculated from the Raman measurements both in Lgate dependence and eSiGe effect. Moreover, we demonstrated that the chan-nel strain even in the MOSFETs after the gate stack formation was evaluated by Raman spectroscopy using cross-section measurement.
5:30 PM - A4.4
SiGe Channels for Higher Mobility CMOS Devices.
Andreas Naumann 1 2 , Torben Kelwing 1 2 , Martin Trentzsch 2 , Thorsten Kammler 2 , Stephan Kronholz 2 , Peter Kuecher 1 , Johann Bartha 3 Show Abstract
1 , Fraunhofer-Center Nanoelectronische Technologien, Dresden Germany, 2 , GLOBALFOUNDRIES Dresden Module One LLC & Co. KG, Dresden Germany, 3 Institut für Halbleiter- und Mikrosystemtechnik, Technische Universistät Dresden, Dresden Germany
Silicon-Germanium (SiGe) is considered to substitute Silicon (Si) as channel material in future CMOS generations for its higher charge carrier mobility. In this work we investigate SiGe channels with low to medium Germanium content, even though the mobility is expected to be better with even more Germanium in the alloy.Low pressure chemical vapor deposition was used for SiGe deposition and a state of the art CMOS process including high-k dielectric and metal gate electrode was applied for fabrication of sub 50nm gate length devices. As expected from the SiGe channel conduction and valence band offset the threshold voltage of the devices is influenced. The gate stack was directly deposited onto the SiGe layer consisting of a chemically grown base oxide, Hafnium-based dielectric and Titanium nitride gate electrode. C-V and I-V measurements show comparable CET and leakage values for the high-k metal gate stack on Si and SiGe channels. The trap density at the channel dielectric interface was investigated using the charge pumping technique.The device characteristic of n- and p-MOSFETs with SiGe channels is compared to conventional Si channel devices to investigate the impact of SiGe channels on the device performance. Short channel mobility was extracted from RON-LG- as well as Gm,L-Method and match well to the observed device performance.
5:45 PM - A4.5
Formation of High Quality Colossal Ge-on-Insulator by Liquid-Phase Epitaxy from Si Substrate.
Takanori Tanaka 1 , Yasuharu Ohta 1 , Kaoru Toko 1 , Masaru Itakura 2 , Taizoh Sadoh 1 , Masanobu Miyao 1 Show Abstract
1 Dept. Electronics, Kyushu University, Fukuoka Japan, 2 Dept. ASEM, Kyushu University, Fukuoka Japan
In order to realize high-performance fully-depleted complimentary metal-oxide-semiconductor field-effect transistors (MOSFET), growth techniques of high-speed channel materials, such as Ge, on insulator are strongly required. To achieve Ge-on-insulator (GOI) structures, we have been investigating Si-Ge mixing triggered lateral liquid-phase epitaxy of Ge on SiO2, which is caused by the solidification temperature gradient due to Si-Ge mixing and the thermal gradient due to latent heat at the growth front. In the present study, we demonstrated formation of colossal single crystalline GOI (~4 mm length) by optimizing RTA conditions. The crystallinity and electrical characteristics of the colossal GOI are discussed.The SiO2 layers (thickness: 50 nm) thermally grown on Si (100), (110), and (111) substrates were patterned by wet etching to form seeding areas, where SiO2 layers were locally removed. Subsequently, a-Ge layers (100 nm) were deposited using an MBE system, and they were patterned into narrow lines (width: 3 micron, length: 1 cm). Then capping-SiO2 (800 nm) was deposited by RF magnetron sputtering. The samples were heat-treated by RTA (1000 degree C, 1 sec) to induce L-LPE from seeding areas.Electron backscattering diffraction (EBSD) observations of the annealed sample grown on Si (100) revealed that a single crystal line Ge (100) layer, where orientation is identical to the substrate orientation, was formed on the SiO2 layer from the seeding edge to 4.3 mm far from the seeding area, though the poly-crystalline Ge layer was formed in the region further than 4.4 mm from the seeding area. This demonstrates a surprisingly colossal growth of Ge with a half-cm on SiO2. Similarly, GOI (110) and (111) were obtained using Si (110) and (111) substrates. These results indicate that single crystal Ge with the crystal orientations identical to those of Si substrates are grown on SiO2 for all samples. This clearly shows that crystal growth is initiated at seeding areas and propagates laterally on SiO2 films and the crystal orientation can be controlled by selecting the Si substrate. In order to evaluate the crystal quality, GOI (100) near and far beyond the Si seeding area was observed by cross-sectional TEM. Many defects were observed around the Si/Ge interface in the seeding area, where SiGe mixing occurred. However, the single crystal GOI (100) with a very smooth surface, without any defects was achieved far beyond the seeding areas. Moreover, the hole mobility of the grown GOI layer was evaluated as 1000 cm2/Vs, which is much higher than that GOI (~400 cm2/Vs) obtained by the oxidation-induced Ge condensation process.This process will open up the possibility of Ge-based fully-depleted MOSFET with high mobilities. A part of this work was supported by Semiconductor Technology Academic Research Center (STARC).
A5: Poster Session
Peide (Peter) Ye
Tuesday AM, December 01, 2009
Exhibit Hall D (Hynes)
9:00 PM - A5.1
Fabrication of Single-Crystal Local Germanium-on-Insulator Structures by Lateral Liquid-Phase Epitaxy.
Tatsuya Hashimoto 1 , Chiaki Yoshimoto 1 , Takuji Hosoi 1 , Takayoshi Shimura 1 , Heiji Watanabe 1 Show Abstract
1 Material & Life Science, Graduate School of Engineering, Osaka University, Suita, Osaka, Japan
Germanium (Ge) is one of the most promising channel materials because of its high carrier mobility and, thus, integration of Ge-based devices with advanced Si-CMOS devices has gained considerable attention as future electronic devices. For this purpose, Ge-on-insulator (GOI) structure is a suitable starting substrate. However, fabrication methods for GOI substrates proposed so far, such as Ge condensation and layer transfer techniques, require complicated processes and have difficulties in achieving high-quality Ge layers. Recently, fabrication of local GOI structures by use of lateral liquid-phase epitaxy (LPE) from the Si seed area has been reported [1-3], which is based on the necking technique using "microcrucibles" to hold the Ge liquid. Interdiffusion at the Ge/Si interface promotes the epitaxial growth from the seed area during the cooling procedure from the melting point (938°C). In addition, propagation of crystallographic defects to the GOI region can be suppressed under the optimized conditions. However, in spite of the great advantage of the lateral LPE technique, determining factors for process optimization have not been clarified yet. In this study, we investigated both effect of microcrucible width; that is width of Ge wires, and impact of underlying insulator materials that will affect interface energy between Ge liquid and insulators on the Ge lateral LPE process. In the LPE growth of Ge wires of 100 µm width on SiO2 insulator, Ge was found to agglomerate into column shapes in order to reduce interface energy at Ge/SiO2. When decreasing line width down to 500 nm, the Ge wire maintained the initial line shape, and 7-µm-long LPE growth from the seed area was observed. Moreover, we demonstrated the use of La2O3 as an underlying insulator to promote lateral LPE growth, and 44-µm-long single-crystal Ge wires of 1 µm width was successfully grown on the insulator. These results indicate that control of the interface energy between Ge liquid and underlying insulators is crucial for suppressing Ge aggregation to realize ideal lateral LPE growth over the channel or active regions.  Y. Liu et al., Appl. Phys. Lett. 84 (2004) 2563.  D. J. Tweet et al., Appl. Phys. Lett. 87 (2005) 141908.  T. Hashimoto et al., IEEE Int. Meeting for Future of Electron Devices, Kansai, SA-4, Osaka, Japan (2008).
9:00 PM - A5.10
Novel Zirconium Formamidinate Precursor for ZrO2 ALD Application.
Huazhi Li 1 , Deo Shenai 1 Show Abstract
1 Dow Electronic Materials, The Dow Chemical Company, North Andover, Massachusetts, United States
Higher dielectric (High-κ) materials are required in order to continue scaling down gate dimensions and to eliminate the high gate leakage experienced by ultrathin (<1.5 nm) films in metal oxide semiconductor field-effect transistor (MOSFET). Hafnium oxide (HfO2) by atomic layer deposition (ALD) has been used in high volume manufacturing 45 nm node transistors because of its high dielectric constant, excellent thermal stability and compatibility with Si processing(1). The transistor performance is further enhanced by synergistically combining High-k gate dielectric materials with III-V materials such as GaAs that offer higher intrinsic carrier mobilities compared to Si. To further scale down effectively, High-k material is needed to possess excellent thermal stability as well as compatibility with Si or III-V material. Zirconium oxide (ZrO2) by ALD also exhibits similar properties as HfO2, and is considered as the alternative suitable candidate. The reported k values of ALD ZrO2 are in the range of 30(2, 3), which is significantly higher than (around 20)those reported for ALD HfO2 (4). In order to achieve ideal ALD ZrO2 performance, suitable zirconium precursors are needed that meet the stringent criteria of thermal stability and reactivity. Tetrakisethylmethylamidozirconium (TEMAZr) has been considered as one of the most promising Zr precursors because of its good physical properties. However, this precursor has relatively low thermal stability, which may become a drawback to ALD ZrO2 process. Low process temperature has to be used with TEMAZr, which may result in less dense films and high level of C contamination. Previously we had reported the La-FAMD and Hf-FAMD (5,6), a class of thermally stable and volatile precursors based on formamidinate platform. Consistent with our earlier work in La and Hf, we continue our development efforts with novel zirconium formamidinate (Zr-FAMD) as an alternative Zr source of greater thermal stability. In this presentation we will report the physical properties of Zr-FAMD precursor including the thermal stability, vapor pressure and solubility. Also we will present the preliminary ALD ZrO2 deposition data using Zr-FAMD and various substrates including III-V semiconductors.References:1. R. Chau; S. Datta; M. Doczy; B. Doyle; J. Kavalieros; M. Metz, IEEE Elect. Dev. Lett., 2004, 25(6), 408-410.2. C.M. Perkins, B. B. Triplett, P. C. McIntyre, K. C. Saraswat, S. Haukka, M. Tuominen, Appl. Phys. Lett., 2001, 78, 2357-2359.3. K. Kukli, M. Ritala, M. Leskela, Chem. Vap. Depos., 2000, 6, 297-302.4. Xinye Liu, Sasangan Ramanathan, Thomas E. Seidel, Mater. Res. Soc. Symp. Proc. 2003, 765, D3.85. H. Li, D. Shenai, R. Pugh, J. Kim, Mater. Res. Soc. Symp. Proc. 2008, 1036E, 1036-M04-18.6. H. Li, D. Shenai, Mater. Res. Soc. Symp. Proc. 2009, manuscript submitted.
9:00 PM - A5.11
Improved Dielectric Phase and Interfacial Dipole Control of Gd2O3-doped HfO2 Gate Dielectrics by Co-sputtering Technique.
Pai-Chi Chou 1 , Jer-Chyi Wang 1 , Woei-Cherng Wu 2 , Chao-Sung Lai 1 Show Abstract
1 , Chang Gung University, Tao-Yuan Taiwan, 2 department of electrophysics, National Chiao Tung University, Hsinchu Taiwan
Recently, high dielectric constant materials have drawn lots of attention on dielectric layer for replacing conventional SiO2 because of the increased capacitance of physically thicker films resulting in reduced gate leakage current. Among the high-k materials, HfO2 has been recently focused due to its reasonably high dielectric constant (~ 20), gate poly-Si compatibility, thermodynamically stable in contact with Si, and a relatively large band gap (~ 5.68 eV). However, for ultra thin oxide CMOS technologies, HfO2 gate dielectrics still face some limitations such as insufficiently low gate leakage, non-negligible C-V hysteresis, and degraded dielectric reliability. Thus, there have been many methods proposed to overcome these limitatons such as Y2O3-doped HfO2, HfAlO, and HfLaO, etc. In this work, we incorporate Gadolinium oxide (Gd2O3) into HfO2 by co-sputtering to form Gd2O3-doped HfO2 to improve dielectric characteristics, and we compared the physical and the electrical properties of Gd2O3-doped HfO2 gate dielectrics which show superior results to the ones of HfO2. To extract the performance of these high-k gate dielectrics, we prepared three different kinds of thickness for each HfO2, Gd2O3, and Gd2O3-doped HfO2 by RF sputtering in Ar and O2 mixture on cleaned p-type <100> Si wafer. The deposition time conditions of these gate dielectrics were fixed at 5, 10, and 20 minutes followed by 800 oC post deposition annealing (PDA) in nitrogen ambient for 30 seconds. Gate leakage current density (J-V), stress induced leakage current (SILC), and time dependent dielectric breakdown (TDDB) were extracted by Agilent 4156C. At the same time, C-V characteristics, frequency dispersion were measured by HP 4285 and HP 4294 LCR meters. Binding and crystallization characteristics were identified by XPS and XRD respectively. In the electrical analysis, we can observe that MOS capacitors with Gd2O3-doped HfO2 were improved compared to pure HfO2. Gd2O3-doped HfO2 exhibits suppressed gate leakage current and higher oxide breakdown voltage due to phase transformation which can be demonstrated by XRD analysis. Negligible C-V hysteresis can be obtained while there is still around 50 mV flatband shift of HfO2. Besides, frequency dispersion of Gd2O3-doped HfO2 also exhibits only less than 10 % capacitance loss when sweeping from 10 kHz to 1 MHz due to improved interfacial dipole. We believe this new Gd2O3-doped HfO2 gate dielectric will be very attractive to CMOS technology.
9:00 PM - A5.12
High Performance SnO2 Nanowire FETs with a high-k Al Doped TiO2 high-k Gate Insulator.
Hyun Hee Park 1 , Pil Soo Kang 2 , Jeong Sook Ha 1 , Gyu Tae Kim 2 Show Abstract
1 Department of Chemical and Biological Engineering, Korea University, Seoul Korea (the Republic of), 2 School of Electrical Engineering, Korea University, Seoul Korea (the Republic of)
High performance of SnO2 nanowire (NW) field effect transistors (FETs) with a 30nm thick of Al doped TiO2 high-k gate insulator was demonstrated in a low voltage operation mode. The Al-doped TiO2 layers were grown on a RuO2 substrate by the atomic layer deposition (ALD) with a variation of the ALD cycle ratio of [Al]/[Al+Ti],R [Al]/[Al+Ti]. At the relative composition ratio of R[Al]/[Al+Ti] ~ 1/60, a remarkable improvement in the leakage current were obtained to be 3 x 10-8 A/cm2 at 1V with a high dielectric constant, k= 50~55 at 30nm. The output characteristics showed a good saturation behavior at Vds =0.5V with a low threshold voltage (Vth) of -0.01V, channel mobility of ~ 3 cm2/V●s , a high on-off current ratio of ~105 at 0.5V and an sharp sub-threshold slope of 0.1~0.13V/dec, fitting to the low-voltage operations. Considering a rather high threshold voltage of ~-10V and sub-threshold slope 11.1V/dec for the 300nm thickness SiO2 gate insulator, the low operating voltage for the Al-doped TiO2 dielectric film around 0.5V suggests the usefulness of the high-k gate insulator in nanowire electronic devices with a low-power logic application or the flexible electronic devices.
9:00 PM - A5.2
Structural and Dielectric Characterization of Interlanthanide LaGdO3 Ceramic and Thin Films for High-k Application.
Shojan Pavunny 1 , R. Thomas 1 , N. Karan 1 , J. Schubert 2 , R. Katiyar 1 Show Abstract
1 Department of Physics and Institute for Functional Nanomaterials, University of Puerto Rico, San Juan, Puerto Rico, United States, 2 , Institute of Bio-and Nano-Systems (IBN1-IT) and JARA-Fundamentals of Future Information Technology, Research Centre , Jülich Germany
The scaling of complementary metal oxide semiconductor (CMOS) devices with silicon-based oxide gate dielectric will soon reach the limit and mixed oxides would enlarge the possibility for material selection suitable for the upcoming generations of CMOS devices. In this context, LaGdO3 (LGO) may be of interest as recently ternary rare-earth oxides such as DyScO3, LaAlO3, NdGdO3 showed encouraging results to sustain the CMOS scaling. LGO is a mixed rare earth oxide with a B-type monoclinic structure with space group C2/m. This phase remains stable to temperatures above 1800°C. In the present study LGO samples were prepared using conventional solid-state route. The X-ray diffraction confirmed the presence of a single phase of the sintered ceramic pellet. The room temperature dielectric constant and loss tangent were 20 and 0.004, respectively. The temperature (100K to 550K) and frequency (100Hz to 1MHz) dependence of the dielectric constant and loss tangent were small; encouraging for the high-k gate oxide and embedded capacitor applications. A series of thin films of LGO with various thicknesses were grown on Pt (111)/ZrO2/ SiO2/Si and Si (100) substrates by pulsed laser deposition to evaluate their performances for high-k applications. The structure, morphology, composition and valency-state were studied with XRD, AFM, EDX and XPS respectively. The electrical measurements were performed in the Metal-Insulator-Metal (MIM) and Metal-Insulator-semiconductor (MIS) configurations. The capacitance equivalent oxide thicknesses of thin films were extracted from capacitance-voltage (C-V) characteristics. The leakage current density and the density of interface traps were also measured. These measurements reveal that LGO could be one of the promising candidates to replace the conventionally used SiO2 or SiOxNy in CMOS devices.
9:00 PM - A5.3
Identification of Impurity Contained in LaAlO3 by Photoluminescence.
Eiji Hirata 1 , Yoshimichi Ohki 1 Show Abstract
1 Electrical Engineering and Bioscience, Waseda University, Shinjuku, Tokyo, Japan
Lanthanum aluminate (LaAlO3) is fascinating as a promising candidate for a gate insulator in advanced MOS devices. However, there is a high possibility that a lot of localized states due to point defects such as interstials, vacancies, and impurities cause leakage current, if they are present in the band gap. In this paper, we examine the presence of such defects in LaAlO3 single crystal plates and thin films by observing their photoluminescence (PL) spectra.The samples are LaAlO3 single crystals grown by the Czochralski method and thin films prepared by a spin-coating method. The films were annealed in oxygen at designated temperatures between 600 and 1000 °C. Using synchrotron radiation as a photon source, PL and PL excitation (PLE) were measured at 10 K. Crystallization of thin films was confirmed by in-plane X-ray diffraction (XRD) measurements.In the crystal samples, five PL peaks are observed at around 1.60, 1.64, 1.675, 2.0, and 2.8 eV at 10 K. The PLE spectrum detected at 2.8 eV has a peak at 5.1 eV. Since the energy state of oxygen vacancy, either charged or uncharged, lies around 5.1 eV over the valence band of LaAlO3, the 2.8 eV PL is assumed to originate from oxygen vacancies. From the temperature dependence of the 2.8 eV PL intensity induced by 5.1 eV photons, thermal activation energy for the 2.8 eV PL in LaAlO3 single crystal can be estimated to be around 30 meV.Although the films on the Si substrate annealed at 600 and 700 °C have no PL peaks, those annealed at 800 °C or higher as well as the crystal samples have three sharp PL peaks at around 1.60, 1.64, and 1.675 eV. On the other hand, the films on the CaF2 substrate have similar three PL peaks at around 1.86, 1.99, and 2.14 eV if they were annealed at 800 °C or higher.The XRD study shows that the films annealed at 800 °C or higher are polycrystalline, while those annealed at 600 and 700 °C are amorphous. Comparison of XRD spectra between the two annealed polycrystalline films on the Si and CaF2 substrates indicates that the lattice constant is smaller if substrate is CaF2.It is known that the luminescence due to Cr3+ in Al2O3 appears only when the sample is crystalline. This is due to energy state splitting of d orbitals in Cr3+ by the crystal field. The PL spectral shapes observed in the single crystal samples and polycrystalline films on the Si substrate in the present study and those of R lines of Cr3+ in LaAlO3 are similar. Therefore, there is a possibility that the present LaAlO3 samples contain Cr3+ ions as an impurity. Since the energy state of Cr3+ ions is significantly influenced by the crystal field, the difference in PL peak energy among the samples deposited on different substrates should be due to the lattice distortion. The authors bought the single crystals and raw chemicals for making thin films from different companies. This indicates that there is a high possibility that a raw material or ore of either La or Al contains chromium as an impurity.
9:00 PM - A5.5
Electrostatic Passivation of Peripheral Interface Trap Charges and Electrostatic Doping in Accumulated Body Transistors.
Mustafa Akbulut 1 , Faruk Dirisaglik 1 , Ali Gokirmak 1 Show Abstract
1 Electrical Engineering, University of Connecticut, Storrs, Connecticut, United States
Accumulated body Silicon MOSFETs that utilize an independently controlled poly-Silicon side-gate that separates the body of the transistor from the shallow trench isolation are fabricated. The side-gate surrounds the active area a guard-rail. By applying a certain bias on the side-gate (i.e. negative bias for a p-type body), the body of the transistor can be accumulated.Experimental results on these side-gated structures show significant improvement in subthreshold slopes and leakage currents (< 50 fA for sub-100nm length and width). Accumulation of the body of a planar nMOSFET results in passivation of traps in the silicon body – shallow trench isolation (STI) interface hence limit trap assisted recombination current.Three-dimensional simulations of devices employing highly p-doped poly-silicon side-gates with 8nm SiO2 of side-dielectric predict leakage currents in the fA regime for 30nm gate length and 60nm width. The voltage requirement on the side-gate is relaxed by 1V for the p+ doped side gates. Hence, the side-gate can be tied to the body for high-density. Furthermore, accumulation of the body through the side-gates reduces the need for channel doping, hence mobility degradation due to impurity scattering and variability due to dopant number fluctuation.
9:00 PM - A5.6
Effective Work Functions of TiCxN1-x in Contact with HfO2 Through ab initio Simulations.
Hong Zhu 1 , Rampi Ramprasad 1 Show Abstract
1 Department of Chemical, Materials & Biomolecular Engineering, Institute of Materials Science, University of Connecticut, Storrs, Connecticut, United States
The HfO2-based high-K dielectric/metal gate stack is being considered and optimized as a replacement for the SiO2/poly-Si stack in semiconductor devices. The choice of the metal gate is determined by its effective work function when in contact with the dielectric (i.e., the alignment of the metal Fermi level with the band edges of the semiconductor substrate beneath hafnia), which is determined by the true (or vacuum) work function of the metal itself and the dipole moment as a result of the charge transfer occurring at the metal-dielectric interface. TiCxN1-x is a promising metal gate due to its resistance to O diffusion and its variation in the work function that can be accomplished by composition changes. There is very strong evidence that the shifts in the metal work function occurs depending on the nature of the interface between HfO2 and the metal. Thus, controlling the composition of the gate metal and the metal/HfO2 interface structure are seen as approaches to controlling the effective work function of the metal gate.In this work, we have performed first principles density functional theory (DFT) calculations combined with statistical thermodynamics (the latter introduced to determine the most probable surface and interface terminations as a function of alloy composition, temperature and O pressure). We will first present the work function of TiCxN1-x alloys (with x spanning from 0 to 1). Our computed work function results for pure TiC (4.6 eV) and TiN (3.2 eV) are in good agreement with available experimental data, and we predict a smooth variation between these end-point values for intermediate alloy compositions. We will then present the metal work function shifts (resulting in an “effective” work function) when an interface between HfO2 and TiCxN1-x is created. In general, we find that the effective work function is a strong function of vacuum work function and interfacial O coverage. However, when an O rich interface is formed, the effective work function is found be pinned to a fixed value, regardless of the vacuum work function of the alloy. These behaviors will be explained in terms of interface dipole moments and interface states. The interface morphology can be related to experimental process conditions (e.g., temperature and O pressure) through statistical thermodynamic models. The DFT-thermodynamics scheme is thus allowing us to correlate effective work functions to processing conditions and alloy composition.
9:00 PM - A5.7
Interaction of an Oxygen Molecule with GaAs (001)-β2(2×4) Surface: First Principles Study.
Dae-Hyun Kim 1 , Dae-Hee Kim 1 , Hwa-Il Seo 2 , Yeong-Cheol Kim 1 Show Abstract
1 Department of Materials Engineering, Korea University of Technology & Education, Chonan Korea (the Republic of), 2 School of Information Technology, Korea University of Technology & Education, Chonan Korea (the Republic of)
We performed a first principles study to investigate the reaction of an oxygen molecule with a GaAs (001)-β2(2×4) surface. The GaAs (001)-β2(2×4) surface was reconstructed by forming three As–As dimers — two As–As dimers on the first layer and one on the third layer. The oxygen molecule can adsorb on the first layer (As), the second layer (Ga), and the third layer (As) because those three layers are partially exposed to the vacuum. The adsorption of the oxygen molecule on the third layer was the most favorable among these adsorption sites and the oxygen molecule formed a peroxyl linkage with the As–As dimer. The oxygen molecule could not form a peroxyl linkage with the As–As dimer on the first layer due to the relatively long bond length of the As–As dimer. The peroxyl linkage of the oxygen molecule with the As–Ga on the first and second layers was the second most favorable adsorption configuration. The dissociation of the oxygen molecule adsorbed on the third layer was exothermic by -3.19 eV, with an energy barrier of 0.36 eV. On the first layer, the inter-dimer dissociation of the oxygen molecule was more favorable than the intra-dimer dissociation; it was exothermic by -2.52 eV, with no significant energy barrier. Though the dissociation of the oxygen molecule between the As–Ga bond on the first and second layers was exothermic by -1.98 eV, it was unfavorable due to a high energy barrier of 0.73 eV and a low energy benefit of 0.08 eV. The insertion of one of the dissociated oxygen atoms into the As-As dimer on the third layer was more favorable than into the As–Ga bond on the third and fourth layers, whereas its insertion into the As-As dimer on the first layer was less favorable than into the Ga–As bond on the first and second layers.
9:00 PM - A5.8
Composition Dependence of the Dielectric Properties of Ta-Ge-O Thin Films.
Taro Naoi 1 , Sara Barron 1 , R. Bruce van Dover 1 Show Abstract
1 Materials Science and Engineering, Cornell University, Ithaca, New York, United States
We have investigated the composition-dependent dielectric properties of Ta-Ge-O as a potential candidate for gate dielectrics in Ge Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET). Ta2O5 – GeO2 binary composition spreads were prepared by 90° off-axis reactive magnetron co-sputtering on a Silicon substrate. At high concentrations of GeO2 (>30 mol.% GeO2), the dielectric constant roughly follows a trend conforming with a linear interpolation between the dielectric constant of pure Ta2O5 to that of pure GeO2. At lower GeO2 concentrations, a positive deviation from the linear interpolation is observed and the dielectric constant plateaus at around 10 mol.% GeO2. Using the Clausius-Mossotti relation we have concluded that this trend can be explained in terms of a rapid change in the ionic polarizability of the system. We attribute this to a change in the local short range bonding structure of the system induced by the addition of GeO2 molecules.
9:00 PM - A5.9
Atomic-layer-deposited Al2O3 and HfO2 on InGaAs – Electrical and Interfacial Micro-structural and Chemical Characteristics.
Yi Jiun Lee 1 , Mao Lin Huang 3 , Yao Chung Chang 1 , Yu Hsing Chang 1 , Han Chin Chiu 1 , Pen Chang 1 , J. Raynien Kwo 2 , Minghwei Hong 1 Show Abstract
1 Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu Taiwan, 3 , National Synchrotron Radiation Research Center, Hsinchu Taiwan, 2 Physics, National Tsing Hua University, Hsinchu Taiwan
High-κ/metal gates on high electron mobility channel materials, such as InGaAs III-V compound semiconductors, are important for complementary metal-oxide- semiconductor (CMOS) devices beyond the 16 nm node. Significant progress has been made on high-quality high-κ dielectrics grown on InGaAs using ultra-high vacuum (UHV) deposited Ga2O3(Gd2O3)[GGO]1 and atomic layer deposited (ALD) Al2O3 and HfO2. 2,3 High κ dielectrics grown by atomic-layer-deposited (ALD) are commonly used in Si MOS devices. In this work, ALD Al2O3 and HfO2 were deposited on InxGaAs1-xAs, where x = 0, 0.15, 0.25, and 0.53. TMA and TEMAH were used as precursors (water as an oxidant) for the ALD Al2O3 and HfO2 with substrate temperatures of 300°C and 200°C, respectively. Native oxides of InGaAs probed using high-resolution x-ray photoelectron spectroscopy (HR-XPS) and high-resolution transmission electron microscopy (HR-TEM) were of 2-4 nm thick and consisted of In2O3, Ga2O3, As2O3, and some variations of their hydro-oxides. Most native oxides were self-cleaned during ALD with residues being In2O3, Ga2O3, and their hydro-oxides at the ALD-oxides/InGaAs interface. In particular, all arsenic oxides (within the resolution of HR-XPS) were removed. The absence of elemental arsenic and arsenic oxide at the interface, as evidenced from the As 2p1/2 core level spectrum, may attribute to the unpinning C-V characteristics.We also observed that thickness of the interfacial residual oxides gets thinner for InGaAs with higher In contents, regardless of ALD-Al2O3 or –HfO2. Given the samples with the same In content, the interfacial thickness is thinner with ALD-Al2O3 than with HfO2.1. M. Hong, J. P. Mannaerts, J. E. Bower, J. Kwo, M. Passlack, W-Y. Hwang, and L. W. Tu, J. Crystal Growth 175/176, 422 (1997). 2. P. D. Ye, G. D. Wilk, B. Yang, J. Kwo, H.-J. L. Gossmann, M. Hong, K. K. Ng, and J. Bude, Appl. Phys. Lett. 84, 434 (2004). 3. M. L. Huang, Y. C. Chang, C. H. Chang, Y. J. Lee, P. Chang, J. Kwo, T. B. Wu, and M. Hong, Appl. Phys. Lett. 87, 252104 (2005).
Minghwei Hong National Tsing Hua University
Wilman Tsai Intel Corporation
Athanasios Dimoulas National Center for Scientific Research “Demokitos”
Peide (Peter) D. Ye Purdue University
A6: Ge and III-V: Device Structures
Tuesday AM, December 01, 2009
Republic A (Sheraton)
9:30 AM - **A6.1
Research Advances on III-V and Ge MOSFETs Beyond Si CMOS.
J. Raynien Kwo 1 , Minghwei Hong 2 Show Abstract
1 Physics, National Tsing Hua University , Hsinchu Taiwan, 2 Materials Science and Engineering, National Tsing Hua University, Hsinchu Taiwan
As driven by continual demands of faster speed of enhanced transport in channels and reduced power dissipation beyond the 22 nm node in the CMOS technology, to extend the Moore’s Law, the current consensus is that the employment of Ge and III-V semiconductors as high-mobility channels and integration with high κ gate dielectrics must be urgently pursued. III-V compound semiconductors InxGa1-xAs, with x varying from 0 to 1 have electron mobility six to eighteen times higher than that in Si, and are now strong contenders for channel replacements beyond the 22-16 nm node. Recently significant advances have been made in the self-aligned, inversion-channel In0.53G0.47As MOSFETs by employing MBE-Al2O3/Ga2O3 (Gd2O3) gate dielectrics as well as ex-situ ALD grown Al2O3. World records in drain current, transconductance, and peak mobility at 1μm gate length were demonstrated, surpassing the performance of Si CMOS at 32 nm node. The GGO/In0.2Ga0.8As interface of negligible bulk traps and good thermal stability led to studies of n- and p-MOSCAPs using metal gates of various work functions. These devices exhibited extremely low leakage current densities, symmetrical C-V characteristics with low Dit, little frequency dispersion, and gate-bias modulated Fermi-level with an efficiency as high as 80% near the midgap. A remarkable tunability of threshold voltage Vth with metal work function was demonstrated, crucial for high performance and low power III-V CMOS applications. Furthermore, the charge pumping method was utilized to determine accurately a mean interfacial density of states (Dit), and its energy dependence within the band gap, as well as the depth profile of bulk traps with respect to the oxide/semiconductor interface. These measurements and methodology are readily applied to other InGaAs semiconductors. Work on channel length scaling by e-beam lithography is now underway toward gate length of 0.1mm and less. Furthermore, direct deposition of Ga2O3(Gd2O3) on a clean Ge surface without a passivation layer such as GeOxNy or Si demonstrated excellent electrical performances and thermodynamic stability in self-aligned Ge p-FETs, showing a high IDS of 500 mA/mm, and peak Gm of 180 mS/mm at 1μm gate length.
10:00 AM - **A6.2
Scattering Mechanisms in Buried InGaAs/High-k Channels
S. Oktyabrsky 1 , Padmaja Nagaiah 1 , Rama Kambhampati 1 , Vadim Tokranov 1 , Michael Yakimov 1 , Sergei Koveshnikov 2 , Niti Goel 2 , Wilman Tsai 2 Show Abstract
1 , University at Albany, Albany, New York, United States, 2 , Intel Corporation, Santa Clara, California, United States
As CMOS scaling continues, new channel materials including III-V compound semiconductors with high-k gate oxides are considered to improve channel transport, intrinsic gate delay and to reduce power consumption of MOSFETs. In order to keep high mobility in the channel, it should be separated from the primary scattering sources, and thus buried quantum well (QW) channel is a promising option, although the top barrier adds up to the equivalent oxide thickness. This work studies the scattering mechanisms in 2D gas due to the presence of high-k oxide to achieve high electron mobility MOS channel. Using in-situ grown HfO2 gated Hall structures as well as ex-situ grown ALD oxides, we experimentally analyzed different scattering mechanisms due to phonons, surface roughness, charges in HfO2 and at the interface with the top In0.53Ga0.47As barrier. The samples were grown on InP substrates using multi-chamber Veeco Mod Gen II MBE system with metal e-beam evaporator source for HfO2 deposition. Hall effect, CV methods supported with analytical techniques (transmission electron microscopy, x-ray photoelectron spectroscopy) are used to analyze electron transport, interface structure and chemistry of the gate stack. Mobility degradation in 10nm-thick compressively strained In0.77Ga0.23As QW channel from 12000 to 1200 cm2/V-s and the mobility vs. temperature slope change from T-1.2 to almost T+1.0 in 77-300 K temperature range was observed when the barrier thickness was reduced from 50 to 0 nm. The reduction of the mobility is attributed primarily to remote Coulomb scattering (RCS) due to charges and dipoles fixed at semiconductor/oxide interface with a charge density of about 1013 cm-2. The mobility vs. sheet carrier density shows the maximum close to 2x1012 cm-2 and reduces at lower and higher carrier densities due to reduction of screening of the RCS by the channel electrons, and filling the high-effective-mass L-valleys, respectively.Introduction of low-k SiOx interface layer formed by oxidation of thin in-situ MBE grown amorphous Si passivation layer has been found to significantly improve the channel mobility. This is qualitatively similar to the formation of an interface SiOx layer in Si/HfO2 gate stack which demonstrates relatively lower contribution in channel scattering than InGaAs/HfO2 interface. The effect of InAlAs/HfO2 interface, oxide thickness and annealing temperature on electron concentration and Hall mobility is analyzed to estimate carrier trapping and various scattering mechanisms, such as bulk oxide charge, interface trapped charge and soft phonon scattering. In the QW channels with 3 nm-thick top barrier, the RCS limits the mobility to ~3500 cm2/Vs. The bulk oxide charge scattering-limited mobility can be as low as 8500 cm2/V-s, and the interface trapped charge of 1012 cm-2 and below does not play a noticeable role in scattering.
10:30 AM - A6.3
Charge Pumping Characterization of Interface Traps in Atomic-layer Deposited Al2O3/In1-xGaxAs Metal-oxide-semiconductor Field-effect Transistors.
Weike Wang 1 , James Hwang 1 , Yi Xuan 2 3 , Peide Ye 2 3 Show Abstract
1 Electrical and Computer Engineering, Lehigh University, Bethlehem, Pennsylvania, United States, 2 Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana, United States, 3 Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana, United States
When silicon-based metal-oxide-semiconductor (MOS) transistors are approaching physical limits, Si industry is searching for alternative materials to continue the scaling of transistors. Recently, In-rich InGaAs inversion-mode metal-oxide-semiconductor field-effect transistors (MOSFETs) show promising on-state performance among various other alternative channels. Although intensive CV studies on atomic-layer deposited (ALD) high-κ/III-V were carried out, limited work has been done on finished InGaAs MOSFETs with different In contents. In this paper, we report on interface studies by charge pumping (CP) technique to extract energy distribution of interface trap density (Dit) on In0.53Ga0.47As, In0.65Ga0.35As and In0.75Ga0.25As n-channel MOSFETs with ALD Al2O3 as gate dielectrics. The InGaAs MOSFETs under test have a 15~20 nm thick 1×1017 cm-3 p-type doped In0.53Ga0.47As, In0.65Ga0.35As or In0.75Ga0.25As channel layer, a 300 nm thick 1×1017 cm-3 p-type doped In0.53Ga0.47As layer and a 500 nm thick 4×1017 cm-3 p-type doped In0.53Ga0.47As layer from top to bottom grown by molecular beam epitaxy on a p+-InP substrate. A 10 nm thick Al2O3 film was deposited by ALD as gate dielectric. These devices have superior on-state performance and are free of Fermi-level pinning, which allows probing the interface over a wide energy range in the bandgap. To extract a detailed energy distribution of Dit over a wide energy range, tr and tf are swept respectively at both room temperature and -50°C. In0.53Ga0.47As MOSFET is measured at an additional 60°C to reach energy levels closer to mid-bandgap. Then the distribution is extracted according to emission-level CP theory with Fermi-Dirac statistics. The result reveals a similar distribution of the Dit for three different channel indium concentrations, which is at low 1012 cm-2eV-1 near conduction-band minimum (CBM) and increases to a peak of low 1013 cm-2eV-1 as it is about 0.2 eV above the valence-band maximum (VBM). No minimum in the Dit distribution is observed. In0.53Ga0.47As MOSFET is found to have a higher average Dit than In0.65Ga0.35As and In0.75Ga0.25As.
10:45 AM - A6.4
Structural and Thermal Stability Study of Al2O3/GGO/In0.2Ga0.8As/GaAs Upon High Temperature Annealing.
Yi Jiun Lee 1 , Pen Chang 1 , Tsung Hung Chiang 1 , Cho Ying Chuang 2 , Chih hsun Lee 1 , Shao Yun Wu 1 , Te Yang Lai 1 , J. Raynien Kwo 2 , Chia Hung Hsu 3 , Minghwei Hong 1 Show Abstract
1 Materials Science and Engineering, National Tsing Hua University, Hsinchu Taiwan, 2 Physics, National Tsing Hua University , Hsinchu Taiwan, 3 , National Synchrotron Radiation Research Center, Hsinchu Taiwan
Integration of high-κ dielectrics with III-V InGaAs compound semiconductors of high carrier mobility as new channel materials has become a very important research topic for device technology beyond the Si CMOS 16nm node . One potential channel candidate In0.2Ga0.8As is known to be strained-grown on GaAs. The strained layer tends to relax to an energetically favorable structure by generating undesirable defects, such as dislocations and others. As a consequence, these will increase roughness between oxides and semiconductors, which unfavorably increase scattering probability and produce more trap centers. Therefore, maintaining the intactness of In0.2Ga0.8As/GaAs without lattice relaxing during high-temperature annealing is the key to the successful device performances, and thus has drawn intensive attention. Excellent electrical properties of Al2O3/GGO/In0.2Ga0.8As/ GaAs under RTA to 850°C were obtained previously . In this work, Al2O3/GGO/In0.2Ga0.8As/GaAs under RTA to 850C has been carefully studied using high-resolution x-ray diffraction and high-resolution transmission electron microscopy (HR-TEM). The narrow line width of the theta-rocking curve of InGaAs (004) peak, 0.037°, reveals the great structural perfection of the InGaAs layer and the well alignment of the (001) axes of InGaAs and GaAs. Further, the contour map of the scattered x-ray intensity near GaAs (115) off-normal reflection of the sample after 850°C RTA shows the well coincidence of the strained layer and the substrate, indicating the identical in-plane lattice constant of InGaAs layer as that of GaAs substrate. In other words, InGaAs layer remains fully strained on GaAs after RTA to 850°C. A 1-D fast Fourier transform (FFT) image of the area in HR-TEM micrograph of an Al2O3/GGO/ In0.2Ga0.8As/GaAs sample after RTA treatment has exhibited nice continuity across the InGaAs/GaAs interface and no misfit dislocations were observed at the interface. Excellent thermal stability of the hetero-structures was convincingly demonstrated. M. Hong, J. R. Kwo, P. C. Tsai, Y. C. Chang, M. L. Huang, C. P. Chen, and T. D. Lin, Japanese Journal of Applied Physics, 46, Part 1 Issue 5B, 3167-3180 (2007).  K. H. Shiu, T. H. Chiang, P. Chang, L. T. Tung, M. Hong, J. Kwo, and W. Tsai, Appl. Phys. Lett, 92, 172904 (2008).
11:30 AM - **A6.5
CMOS Technologies with High-electron Mobility III-V Channels and High-k Gate Stacks.
Tso-Ping Ma 1 , Abigail Lubow 1 Show Abstract
1 Electrical Engineering, Yale University, New Haven, Connecticut, United States
For over 4 decades, the steady increase in switching speed of MOS transistors has been mainly achieved by scaling down the gate oxide thickness and the channel length. In recent years, strain engineering to increase the carrier mobility has also been a significant contributor to the improved switching speed. These measures have been able to keep Si as the only semiconductor for high-density CMOS technology. However, it has become increasingly difficult to implement these measures, and high-mobility channel materials are seriously being considered as alternatives to Si when ultra-high switching speed is required. Among the leading contenders are carbon nano-tube, graphene, and III-V semiconductors, and this author has concluded that only III-V semiconductors have a realistic chance of integrating with Si for future mainstream high-density integrated circuits technology, especially within the time frame when such alternative channels are first needed. The high carrier mobilities in aforementioned materials are often associated with their small effective masses, which may give rise to lower densities of states, and thus fewer carriers in the conduction channel for a given gate voltage. Therefore, a consequence of the lower density-of-state is to negate the gain in the drive current due to the carrier’s higher mobility. As a result, it is not obvious whether a high-mobility channel does indeed lead to high drive current. This question has been addressed for a few high-electron-mobility III-V semiconductors, and the results will be presented in this talk. Another major issue is the low hole mobility in many high-electron-mobility III-V semiconductors, which negates the advantage of the high electron mobility. A novel "unipolar" CMOS logic, which does not need a p-channel transistor in the CMOS switch, will be introduced to solve this problem. The “unipolar” CMOS logic technology is distinctly different from the conventional NMOS logic widely used in the 1970’s and 1980’s, in that the conventional NMOS logic consumes excessive standby power due to the unavoidable current path in one of the logic states, whereas the proposed “unipolar” CMOS logic is made of transistors with “complementary” threshold voltages (i.e., threshold voltages with opposite polarities) which minimizes the standby power. Examples of logic circuits utilizing the “unipolar” logic concept will be presented. The “unipolar” CMOS can also be applied to other materials, such as graphene, nanotube, or certain thin-film semiconductors, where it is difficult to incorporate both p-type and n-type dopants, or fabricate both p-type and n-type contacts.
12:00 PM - **A6.6
III-V Metal-Oxide-Semiconductor Structures with Silicon Passivation Interlayer: Facts and Future.
Chiara Marchiori 1 , Christian Gerl 1 , Mirja Richter 1 , Daniele Caimi 1 , Dave Webb 1 , Christophe Rossel 1 , Maryline Sousa 1 , Heinz Siegwart 1 , Caroline Andersson 1 , Jean Fompeyrine 1 Show Abstract
1 Zurich Research Laboratory, IBM Research GmbH, Rueschlikon Switzerland
The end of the CMOS roadmap has been announced many times in the recent years, yet further progress in device performance is still being demonstrated. One reason is that the industry has slowly shifted from the simple dimensions scaling to the implementation of novel materials. A clear illustration of this trend is the introduction of high-k materials as a replacement for SiO2. This evolution will go on, and one can also expect the replacement of silicon by other high mobility channel semiconductors with enhanced transport properties, such as Ge or III-V. In this context, III-V materials have generated a renewed interest in the last few years, and the number of publications in this area is growing rapidly. III-V’s exhibit nice features that make them attractive for digital applications, with the ability to fabricate band-gap engineered devices with high carrier velocity and possibly low access resistance. The most recent development in the fabrication of III-V based MOSFET or related devices will be reviewed, with an emphasis on the different architectures currently proposed.The price to pay to fully exploit the potential of III-V materials is to face the challenging problem of electrical passivation at III-V/oxide interfaces, whatever the device structure can be. Indeed the number of interface defects such as missing As atoms due to surface absorbed oxygen, misfit dislocations at GaAs interface, etc. must be minimized to avoid Fermi level pinning. Therefore, it is necessary to develop the right procedure for i) surface cleaning, ii) high quality III-V channel deposition and iii) effective surface passivation.It appears clearly that only a few passivation strategies are being pursued, based either on Ga2O3, or on Al2O3 or on group IV elements such as Si and Ge. The pros and cons of the different approaches will be discussed as wellWe have focused our own efforts on the use of ultra-thin Si as a passivation layer, grown between (In,Ga)As and HfO2 or Al2O3. The gate stacks are grown by MBE, and characterized by RHEED, TEM and in-situ XPS. Electrical properties of the stacks are assessed on capacitors and in some cases, on transistors. The results will be presented with a special focus on 1) the different approaches to clean and prepare the III-V surfaces 2) the deposition conditions to grow the silicon interlayer and the gate dielectric film 3) the correct extraction of the interface state density and finally 4) the impact on the output and transfer characteristics of field effect transistors
12:30 PM - A6.7
High-performance III-V MOSFETS with ALD High-κ LaLuO3.
Yiqun Liu 1 , Yanqing Wu 2 , Min Xu 2 , Jun-Jieh Wang 1 , Peide Ye 2 , Roy Gordon 1 Show Abstract
1 Department of Chemistry and Chemical Biology, Harvard, Cambridge, Massachusetts, United States, 2 School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana, United States
Amorphous LaLuO3 films were deposited by Atomic Layer Deposition (ALD) at 350 oC. The precursors are lanthanum tris(N,N'-diisopropylformamidinate), lutetium tris(N,N'-diethylformamidinate) and water vapor. The substrate is InxGa(1-x)As with 2 nm ALD Al2O3 as the interfacial control layer (ICL). The capacitance-voltage measurements from both n and p-type GaAs MOS capacitors indicate that the interface between GaAs and oxide is sharp by using Al2O3 interlayer and the κ value of LaLuO3 is 25(±1), which offers great potential to scaling the EOT by integrating the higher-κ dielectric on III-V semiconductors. Deep sub-micron LaLuO3/Al2O3/In0.7Ga0.3As n-type channel inversion MOSFETs with gate lengths down to 140 nm were then fabricated. The output current and transconductance of a typical 160 nm-channel device are over 600 uA/um and 600 uS/um, respectively. Important scaling metrics such as Subthreshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage roll-off will be discussed.
12:45 PM - A6.8
ALD-Al2O3 as an Interlayer for Ge MOS Devices with Higher-k Dielectrics.
Shankar Swaminathan 1 , Yasuhiro Oshima 2 1 , Michael Shandalov 1 , Paul McIntyre 1 Show Abstract
1 , Stanford University, CA, Stanford, California, United States, 2 , Tokyo Electron U.S. Holdings, Incorporated, Santa Clara, California, United States
The figure of merit for gate leakage by direct tunneling is given by f = K(Φ^0.5) where K is the dielectric constant of the gate dielectric and Φ is the tunnel barrier height. Empirically, it is found that scaling of with K makes dielectrics with K ~ 40 especially suitable for future scaling, prompting interest in gate oxides with K higher than of HfO2(~ 20).Ultrathin ALD-Al2O3 is promising as an interlayer (IL) between Ge FET channels and higher-K oxides that would, by themselves, have low band offsets to Ge (e.g. TiO2). Al2O3 has excellent thermal stability, large bandgap (~8.8eV), and moderately-high dielectric constant (K~8). In this context, the properties of ALD-Al2O3 on Ge(100) are studied to examine the viability of ALD-Al2O3 interlayers (IL) for Ge/higher-K gate stacks. Differentially-pumped in situ x-ray photoelectron spectroscopy (XPS) during ALD reveals 10-12 cycles for Al2O3 incubation and –OH incorporation in the bulk. TEM confirmed a nearly-abrupt Ge/Al2O3 interface which is beneficial for capacitance scaling. Evidence of GeOx self-cleaning by TMA-induced reduction and a surface-energy-induced GeOx “float-up” was observed by in situ XPS and medium ion-energy spectroscopy (MEIS). The stacks are observed to exhibit lower Dit as the physical thickness of Al2O3 is scaled down. A minimum Dit of 1.9x1011 cm-2 eV-1 was extracted for p-Ge/3nm Al2O3 gate stack. ALD-TiO2 was deposited by TDMAT/H2O process in situ after Al2O3 deposition to fabricate p-Ge/Al2O3 IL/TiO2/Pt stacks. Large reduction in gate leakage at Vfb (~ 6 orders) is achieved by the introduction of 1nm Al2O3 IL when compared to a sample with no IL. A low CET of 1.17nm was achieved using a 0.6nm IL. The hysteresis for 0.6,1 and 2.4nm IL stacks is observed to be < 10mV, indicative of low density of defects contributing to charge trapping in the IL. Positive flatband shifts with increasing Al2O3 IL thickness are suggestive of negative fixed charge at the interface. Forming gas annealing (FGA) is seen to improve the density of interface states Dit by an order of magnitude. Midgap Dit of these stacks after FGA annealing was ~ 3x1011 cm-2 eV-1, showing the promise of ultrathin ALD-Al2O3 as an IL for Ge MOS devices. Similar results on Ge/Al2O3 IL/ZrO2 and Ge/Al2O3 IL/HfO2 stacks will be presented.
A7: Ge and III-V: Gate Dielectrics
Tuesday PM, December 01, 2009
Republic A (Sheraton)
2:30 PM - **A7.1
High Mobility Channel Materials and Novel Devices for Scaling of Nanoelectronics beyond the Si Roadmap.
Marc Heyns 1 2 , Florence Bellenger 1 , Guy Brammertz 1 , Matty Caymax 1 , Stefan De Gendt 1 , Brice De Jaeger 1 , Annelies Delabie 1 , Geert Eneman 1 , Guido Groeseneken 1 , Michel Houssa 3 , Daniele Leonelli 1 , Dennis Lin 1 , Koen Martens 1 , Clement Merckling 1 , Marc Meuris 1 , Jerome Mitard 1 , Julien Penaud 4 , Geoffrey Pourtois 1 , Marco Scarrozza 1 , Eddy Simoen 1 , Sven Van Elshocht 1 , William Vandenberghe 1 , Anne Vandooren 1 , Anne Verhulst 1 , Wei-E Wang 5 Show Abstract
1 , IMEC, Leuven Belgium, 2 Metallurgy and Materials Engineering, K.U.Leuven, Leuven Belgium, 3 Physics, K.U.Leuven, Leuven Belgium, 4 , Riber assignee at IMEC, Leuven Belgium, 5 , INTEL assignee at IMEC, Leuven Belgium
High mobility channel materials and new device structures will be needed to meet the power and performance specifications in future technology nodes. Therefore, the use of Ge and III/V materials and novel devices such as heterojunction TunnelFET’s is investigated for future CMOS applications. High-performance CMOS can be obtained by combining Ge pMOS devices with nMOS devices made on III/V compounds such as InGaAs. In all cases the key challenge is the electrical passivation of the interface between the high-k dielectric and the alternative channel materials. Recent studies have demonstrated good electrical properties of the GeO2/Ge interface. Since the GeO2 layer is very hygroscopic, full in-situ processing of GeO2 formation and high-k deposition must be performed or other methods must be employed to stabilize the GeO2 layer. One of the most successful passivation techniques for Ge MOS gate stacks is a thin, epitaxial layer of Si. A lot of attention went into better understanding of this passivation and the effects of its optimization on various device characteristics. It was found that mobility and Vt trends in both pMOS and nMOS transistors can be explained based on defects located at the Si/SiO2 interface.Unfortunately, III-V/oxide interfaces are not quite as robust and most interfaces present rather high densities of interface states. Although, considerable improvements have been realized in the reduction of the interface state density, further developments are required to obtain high performance MOS devices. To this purpose various passivation methods were critically evaluated. Simulations using Density Functional Theory reveal the possibility of using a thin amorphous layer made of GeOx to obtain an electrically unpinned gap. The major challenge resides in the control of the c-Ge thickness and the oxidation of this layer to avoid the diffusion of oxygen atoms at the Ge/GaAs(001) interface. Promising results are obtained by optimizing the surface preparation, high-k deposition and annealing cycle on In0.53Ga0.47As-Al2O3 interfaces. Self-aligned inversion channel n-MOSFETs fabricated on p-type In0.53Ga0.47As demonstrate inversion-mode operation with high drive current and a peak electron mobility of 3000 cm2/Vs.Since ultimately the major showstopper on the scaling roadmap is not device speed, but rather power density, the introduction of these advanced materials will have to go together with the introduction of new device concepts. Novel structures such as heterojunction TunnelFET’s can fully exploit the properties of these new materials and provide superior performance at lower power consumption by virtue of their improved subthreshold behaviour. Vertical surround gate devices produced from nanowires allow the introduction of a wide range of materials on Si. This illustrates the possibilities that are created by the combination of new materials and devices to allow scaling of nanoelectronics beyond the Si roadmap.
3:00 PM - A7.2
Impact of Plasma Nitridation on Physical and Electrical Properties of Ultrathin Thermal Oxides on Ge(100).
Katsuhiro Kutsuki 1 , Gaku Okamoto 1 , Takuji Hosoi 1 , Takayoshi Shimura 1 , Heiji Watanabe 1 Show Abstract
1 Graduate School of Engineering, Osaka University, Suita, Osaka, Japan
Germanium (Ge) has attracted tremendous attention as an advanced channel material due to its higher hole and electron mobility compared with that of Si. Among various candidate materials for gate dielectrics of Ge-MIS devices, GeO2 is known as a fundamental insulator and as a buffer layer between modern high-permittivity (high-k) dielectrics and Ge substrates. Although recent studies have indicated good electrical properties of thermally grown GeO2/Ge interfaces [1,2], the intrinsic nature of GeO2, such as water solubility and poor thermal stability in contact with a Ge substrate, is a serious problem for implementation of high-mobility Ge-based devices. In addition, dielectric and interface qualities at the GeO2/Ge have been mainly examined for thick oxide layers or stacked structures with high-k gate dielectrics, and the scalability of GeO2 insulators has not been clarified for ultrathin regions down to a thickness of a few nanometers. In this study, we examined the basic properties of ultrathin GeO2 dielectrics grown by thermal oxidation of Ge(100) surfaces and investigated the effects of nitrogen plasma treatment on the electrical properties of Ge-MIS devices. The thermal oxides for the ultrathin region showed poor insulating properties, which indicates difficulties in the scaling of equivalent oxide thickness (EOT) of pure GeO2 gate dielectrics. To overcome these problems, high-density plasma nitridation of the oxide surfaces was conducted using ultrahigh vacuum (UHV)-based plasma equipment. Angle-resolved x-ray photoelectron spectroscopy analysis showed that plasma nitridation of GeO2 surfaces allows us to form an ultrathin Ge3N4 capping layer without piling up nitrogen at the interface. The EOT value was scaled down to 1.7 nm, and leakage current was significantly reduced. The minimum Dit value of the GeON/Ge interfaces was estimated as low as 3.3 x 1011 cm-2eV-1, which suggests that excellent interface properties of thermally grown GeO2/Ge structures were preserved. These results reveal that the nitrogen plasma treatment recovered insulating properties of the degraded GeO2 uppermost layers by forming stable and high-quality nitride layers, and clearly demonstrate the use of GeON with nitride capping for the gate dielectrics and interface layers for high-k/Ge gate stacks.  H. Matsubara et al., Appl. Phys. Lett. 93 (2008) 032104.  T. Hosoi et al., Appl. Phys. Lett. 94 (2009) 202112.
3:15 PM - A7.3
Structural, Chemical and Electrical Characterisation of La-doped ZrO2 and Er-doped HfO2 Films Deposited on Ge Substrates.
Simon Elliott 1 , Pierre-Eugene Coulon 2 , Sylvie Schamm 2 , Claudia Wiemer 3 , Luca Lamagna 3 , Silvia Baldovino 3 , Marco Fanciulli 3 4 Show Abstract
1 , Tyndall National Institute, Cork Ireland, 2 , CEMES-CNRS, Toulouse France, 3 Laboratorio Nazionale MDM, CNR-INFM, Agrate Brianza (MB) Italy, 4 Dipartimento di Scienza dei Materiali, Università di Milano Bicocca, Milano Italy
We present the deposition and properties of two different high-k dielectric films on Ge wafers, as an alternative to the more commonly studied high-k/Si stacks. We focus in particular on how interfacial layers (IL) and Ge diffusion affect the dielectric properties of the stack.Atomic layer deposition (ALD) was used to produce homogeneous high-k thin films in the 3-30 nm thickness range on native oxide free n-type Ge(100). La-doped ZrO2 was deposited from the precursors La(iPrCp)3, ZrD-04 and O3 and Er-doped HfO2 was deposited from Er(iPrCp)3, HfD-04 and O3, with Er concentrations ranging 1-15% The early stages of growth on the Ge substrate were monitored by means of in situ spectroscopic ellipsometry and were found to be quite different to comparable reactions on Si.A detailed analysis of the structural and chemical properties of both as-grown and annealed samples was carried out by XRR, XRD, ToF-SIMS, TEM/HRTEM and STEM/EELS. La-ZrO2 films were found to be completely crystalline, as-deposited and annealed, with mainly the cubic/tetragonal ZrO2 structure. The amorphous IL was germanate-like. Diffusion of Ge was evident throughout the oxide after annealing. Er-HfO2 films presented the cubic crystalline phase of HfO2. No change in structure was evident at the interface with the Ge substrate but a chemical IL was detected. This was correlated to the diffusion of Ge atoms from the substrate and with the increase of roughness at the semiconductor/oxide interface after annealing.Values of the dielectric permittivity were obtained from the capacitance of the high-k/Ge stacks across a range of oxide thicknesses. For La-ZrO2/Ge, k=29±1 was obtained, including a 2 nm thick IL. The contribution from the oxide increased dramatically on annealing, suggesting that Ge diffusion produces tetragonal ZrO2. Consistent with a germanate IL, the defect density at the interface to Ge was reasonably low, but increased along with the roughness on annealing. The investigation of dielectric properties of the as-grown and annealed Er-HfO2 films revealed a direct dependence of the dielectric properties on the Er content.This work was supported by the European Commission under the FP6 project REALISE, http://www.tyndall.ie/realise .
3:30 PM - A7.4
Effects of Post-Deposition Annealing on the Characteristics of LaLuO3/Ge(100) Structures.
Claudio Radtke 1 , Gabriel Marmitt 1 , Cristiano Krug 2 , Gabriel Soares 3 , Israel J. Baumvol 2 3 , Joao M. Lopes 4 5 , E. Durgun-Ozben 4 5 , J. Schubert 4 5 , S. Mantl 4 5 Show Abstract
1 , IQ-UFRGS, Porto Alegre, RS, Brazil, 2 , IF-UFRGS, Porto Alegre, RS, Brazil, 3 CCET, UCS, Caxias do Sul, RS, Brazil, 4 Institute for Bio- and Nanosystems (IBN1-IT), Research Center Juelich, Juelich Germany, 5 , JARA-Fundamentls of Future Information Technologies, Juelich Germany
Miniaturization of metal-oxide-semiconductor field effect transistors (MOSFETs) is approaching fundamental limits. New materials and innovative device structures are needed in order to continue the evolution of complementary metal-oxide-semiconductor (CMOS) technology. The use of high-k dielectrics in conjunction with semiconductors with better transport properties than silicon (Si) is an attractive alternative. Germanium (Ge) has bulk electron and hole mobilities that are 2.8 and 4.2 times those of Si, being a promising candidate. However, the formation of a stable passivating layer on Ge surfaces with a low density of electrically active defects is still a challenge. Lanthanum lutetium oxide (LaLuO3) presents interesting properties to be used as a gate dielectric. It keeps its amorphous structure after high temperature annealing (1000°C) with a dielectric constant (κ) of approximately 32. Mostly, rare earth oxides show strong interaction with Ge forming stable interfacial layers (see for example G. Mavrou et al., J. Appl. Phys. 103, 014506 (2008)). In the present work, we investigated the effect of thermal annealing on the electrical properties of LaLuO3/Ge structures, correlating results with physico-chemical characteristics. LaLuO3 films were deposited by molecular beam deposition (MBD) on p-type Ge(100) wafers. Si(100) counterpart samples were prepared for comparison. After deposition, the samples were annealed in either oxygen (O2) or nitrogen (N2) atmosphere. Oxidations were performed with O2 enriched to 97% in the 18O isotope (18O2). The amount and depth distribution of 18O were determined by nuclear reaction analyses. That enabled us to distinguish oxygen originally in the LaLuO3 film from that incorporated during annealing. MOS capacitors for electrical characterization were fabricated with platinum (Pt) gate electrodes and aluminum (Al) as the back ohmic contact. The chemical environment of the elements was probed by X-ray photoelectron spectroscopy (XPS) especially to infer about substrate oxidation. Higher values of interface state density (Dit) were measured in samples annealed in O2 in comparison to as-deposited — the higher the thermal budget, the higher the measured Dit. A slight improvement of interface characteristics was obtained after annealing in N2. Equivalent oxide thickness (EOT) values improved after thermal treatments, the best value being that of the sample annealed in N2 (2.6 nm, 22% reduction with respect to as-deposited). 18O depth profiling evidenced that oxygen penetrates deeper into the sample as the time and temperature of the oxidation step are raised. This fact can be related to a higher oxidation degree of the Ge substrate, generating undesirable GeOx species, which degrades the electrical characteristi