Symposium EM6 : Thin-Film Transistors---New Materials and Device Concepts

Organic thin-film transistors (TFTs) can typically be fabricated at temperatures below 150 °C and thus not only on glass substrates, but also on a variety of unconventional substrates, such as plastics, paper and textiles. This makes organic TFTs potentially useful for the realization of flexible, large-area electronics applications, such as rollable or foldable displays and conformable sensor arrays. In some of the more advanced applications envisioned for organic TFTs, such as the integrated row and column drivers of flexible active-matrix organic light-emitting diode (AMOLED) displays, the TFTs have to be able to control electrical signals of a few volts at frequencies of several megahertz. The first requirement for achieving high switching frequencies is efficient charge transport in the semiconductor. This requirement can be met by choosing organic semiconductors that provide good molecular ordering and large carrier mobilities, even when processed at low temperatures. Examples are the thienoacene DNTT and its alkylated or phenylated derivatives for p-channel TFTs [1,2] and the core-cyanated perylene diimide derivative Polyera ActivInk N1100 for n-channel TFTs [3,4]. The second requirement is a small channel length [5]. To meet this requirement, we have developed a process in which the TFTs are patterned using high-resolution silicon stencil masks. With this process, bottom-gate, top-contact organic TFTs with a channel length of 1 µm can be fabricated on flexible polyethylene naphthalate (PEN) substrates [6]. The gate dielectric is a combination of oxygen-plasma-grown aluminum oxide and an alkyl or fluoroalkyl-phosphonic acid self-assembled monolayer (SAM). Due to its small thickness (5.3 nm), the TFTs can be operated with voltages of about 2 to 3 V. For 11-stage complementary and unipolar ring oscillators based on TFTs with a channel length of 1 µm, signal propagation delays per stage as short as 6.6 µs and 420 ns have been measured at a supply voltage of 3 V [7,8]. [1] K. Niimi et al., Org. Lett. 13, 3430, 2011. [2] R. Hofmockel et al., Org. Electronics 14, 3213, 2013. [3] B. A. Jones et al., Angew. Chem. Int. Ed. 43, 6363, 2004. [4] J. Soeda et al., Adv. Mater. 23, 3681, 2011. [5] M. Kitamura et al., Appl. Phys. Express 4, 051601, 2011. [6] T. Zaki et al., IEEE J. Solid-State Circuits 47, 292, 2012. [7] U. Kraft et al., Adv. Mater. 27, 207, 2015. [8] U. Zschieschang et al., Org. Electronics, 14, 1516 2013.

Deformable wireless sensors, bendable radio frequency transceiver and high resolution flexible displays require electronic circuits which operate above tens of megahertz in order to efficiently treat signals, address local parts of the system and transmit data to the external world. The basic components of all these flexible circuits are thin film transistors (TFTs).
Depending on the application, there are parameters which are more important than others in evaluating the TFTs performance[1]. In digital circuits the TFTs must have excellent switching capabilities, on–off current ratio greater than 10⁵, and symmetrical threshold voltages, i.e. V_TH,n = −V_TH,p. In radio frequency (RF) circuit, switching capabilities are not required per se. For high-speed applications, TFTs should respond quickly to variations in the gate voltage: this practically means short gates and fast carriers in the channel. The cut-off frequency, f_T, is the most widely used figure of merit for RF devices and is defined as the frequency at which the current gain reaches the unity. It can be maximized by making the intrinsic transconductance, g_m, as large as possible and making the drain conductance, g_ds, the gate capacitance and source/drain contact resistances as small as possible. Drain-current saturation is also necessary to maximize the intrinsic voltage gain, G_int = g_m/g_ds, which has become a popular figure of merit for mixed-signal circuits. Channel length scaling is the most straightforward approach to achieve high frequency operation but it is very challenging in case of direct fabrication on plastic foils. This explains the continuous search for high mobility materials which can be processed at low temperature.
Research in recent years has established a-IGZO as the semiconductor for thin film transistors[2]. Such technology offers several attractive properties including optical transparency, large band gap (3eV) covering the UV-spectrum, high mobility (10cm²/Vs)[3], low temperature and large area deposition and operational stability. Moreover, existing data and preliminary experiments demonstrate that IGZO is biocompatible, in fact, Ga and In are approved as alloys by the US food and drug administration and ZnO at concentration<100ug/ml is biocompatible and water soluble.
This talk begins by providing some design guidelines and technological insights to achieve ultraflexible a-IGZO TFTs with a transient frequency above 100MHz[4, 5] and proceeds by showing examples of analog amplifiers which can be used in RF applications and in the amplification of biosignals[6].

[1] F. Schwierz, Nat. Nanotech., vol. 5, pp. 487-496, 2010.
[2] E. Fortunato, et al., Adv. Mat., vol. 24, pp. 2945-2986, 2012.
[3] K. Nomura, et al., Nature, vol. 432, pp. 488-492, 2004.
[4] N. Münzenrieder, et al., Appl. Phys. Lett., vol. 105, p. 263504, 2014.
[5] G. A. Salvatore, et al., Nat Commun, vol. 5, 01/07/online 2014.
[6] D. Karnaushenko, et al., Adv. Mat., vol. 27, pp. 6797-6805, 2015.

We demonstrate a zinc-tin oxide high-voltage thin-film transistor (HVTFTs) on polyimide integrated as a switch to drive 1 kilovolt dielectric elastomer actuators (DEAs) with 30 Volts gate control. DEAs find applications where their flexibility and high strain (>50%) provide unique advantages, such as in soft robotic, tunable optics, and haptic interfaces. However, they require high driving voltages, which makes controlling large actuator arrays challenging. HVTFTs enable the actuation of a large number of DEAs with a single common high voltage line. This paves the way towards new applications, such as multiple-degree-of-freedom soft robotic, self-switching and automation.
The high-voltage thin-film transistor uses a top-gate, coplanar electrode architecture. A layer of zinc-tin oxide is spincoated on a polyimide substrate coated with a 20nm layer of alumina. The oxide semiconductor is synthesized at 450°C under air. Then, 200nm aluminum source and drain electrodes are evaporated through a shadow mask. For the gate dielectric, we first passivate the semiconductor with atomic layer deposition of 100nm alumina. Then, 1µm parylene is added to the dielectric layer to achieve 400 V dielectric breakdown voltage. We then do aluminum gate evaporation. The gate is offset from the drain by several tens of microns. We show how critical this offset is to achieve kV transistor breakdown voltage. At the end, we open the source and the drain contact by laser ablation through the dielectric layer.
We use the transistor substrate as the frame for the suspended DEA membrane. The DEA is a thin-PDMS elastomeric membrane between two stretchable carbon electrodes. It behaves as a high-voltage stretchable capacitor with a quadratic strain response to voltage application. We then stencil print a silver line to connect the DEA and the transistor. Demonstration of a DEA driven by a high-voltage TFT is achieved and characterized by measuring the diaphragm deflection versus the applied gate voltage. When a drain voltage of 1kV is applied to the transistor, the deflection of the actuator can be controlled between 0 and 300um by modulating the gate voltage between 30V and 0V. We demonstrate an array of high-voltage thin-film transistors driving 4x4 matrix of dielectric elastomer actuator diaphragms, with microcontroller control of the gates and the drain being connected through a pull-up resistor configuration to a single 1kV supply.
We also show the potential of a migration of the HVTFT cleanroom process to a fully printed process to directly print the transistors on the DEA frames. Comparison of the two fabrication methods will be presented and the challenges will be highlighted.

Polymer semiconductors have long captured great academic and industrial interest for their potential in large-area electronics. This is in view of their facile solution processability, potentially low manufacturing cost, and the possibility of deployment in a variety of non-traditional situations (e.g., on substrates made of plastics, paper, wood, in cars and buildings, and on the human body).
Much sough-after for battery-powered applications, low-voltage operation in polymer transistors poses unique challenges that are intimately related to their charge-transport physics, namely large threshold voltages and shallow subthreshold slopes. These challenges have been typically addressed in terms of channel charge density and channel-gate capacitive coupling, both of which are enhanced by increasing the permittivity of the gate dielectric and reducing the thickness of the same.^1–3 Surprisingly, however, no clear implication for low-voltage operation has been brought to the fore in respect to the longitudinal field dependence of transport and injection processes, which are characteristic of polymer semiconductors.
This study sheds light on the low-voltage operation of polymer semiconductor transistors. With a focus on IDT-BT, a polymer with rather unique nearly “disorder-free” transport properties,⁴ we show that a mere enhancement of the channel-gate capacitive coupling is not sufficient for low-voltage transistor operation. We thus experimentally identify the underlying causes of this behavior, and present material strategies that successfully override them, leading to high-performance transistor operation at below 3V.
The technological significance of this study is finally demonstrated, in the form of a two-stage differential amplifier, namely a core analog circuit relevant to a wealth of signal conditioning and sensing applications (e.g., smart sensor systems). The circuit functions down to a power supply voltage of 5V, much lower than state-of-the-art implementations of similar circuits, and achieves superior performance in a number of fundamental metrics. Therefore, our study on low-voltage operation in polymer-semiconductor transistors paves the way for high-performance battery-powered large-area electronics.
1 A. Luzio, F. G. Ferré, F. Di Fonzo and M. Caironi, Adv. Funct. Mater., 2014, 24, 1790–1798.
2 Y. M. Park, J. Daniel, M. Heeney and A. Salleo, Adv. Mater., 2011, 23, 971–4.
3 J. Li, Z. Sun and F. Yan, Adv. Mater., 2012, 24, 88–93.
4 D. Venkateshvaran, M. Nikolka, A. Sadhanala, V. Lemaur, M. Zelazny, M. Kepa, M. Hurhangee, A. J. Kronemeijer, V. Pecunia, I. Nasrallah, I. Romanov, K. Broch, I. McCulloch, D. Emin, Y. Olivier, J. Cornil, D. Beljonne and H. Sirringhaus, Nature, 2014, 515, 384–388.

In the last decade there has been considerable development in the area of amorphous oxide semiconductors (AOS) such as InGaZnO, owing to their superior electrical properties as compared to a- Si:H, and lower cost and better uniformity over large areas as compared to poly-Si.^1,2 Today’s technique of choice for depositing these materials in industry has been sputtering from an oxide target. While sputtering is a useful and versatile deposition technique, it requires expensive vacuum equipment. Furthermore, it turns out to be difficult to achieve the right material composition and thickness over large areas, leading to variation in transistor performance particularly for thin films. In this work, we present spatial atomic layer deposition (S-ALD) as an alternative method to deposit these materials in an industrially scalable process at atmospheric pressure.³
S-ALD combines the advantages of temporal ALD (superior control of layer thickness and composition, large-scale uniformity and unparalleled conformability inherent to self-limited layer-by-layer growth) with high deposition rates, eliminating the need for vacuum processing. By pre-mixing vapors of metal precursors with either water vapor or oxygen plasma jet as the oxygen source, we can accurately control the film composition. Diethylzinc, trimethylindium, and triethylgallium are used as Zn, In, and Ga precursors, respectively. Amorphous InZnO thin-film transistors show a high mobility of 30 cm²/Vs, low-off current, a switch-on voltage of ~0V and excellent bias stress stability. These characteristics are preserved when scaling down the thickness of the semiconductor to less than 5 nm, opening the way to engineer novel semiconductor structures, such as superlattices,⁴ with even higher electron mobilities, and ultra-flexible electronics.
1. K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M Hirano and H. Hosono, Nature 432, 488 (2004)
2. T. Kamiya and H. Hosono, NPG Asia Mater. 2, 15 (2010)
3. A. Illiberi, B. Cobb, A. Sharma, T. Grehl, H. Brongersma, F. Roozeboom, G. Gelinck and P. Poodt, App. Mat. Interfaces 5 (24), 13124 (2013)
4. Yen-Hung Lin, Hendrik Faber, John G. Labram, Emmanuel Stratakis Labrini Sygellou, Emmanuel Kymakis, Nikolaos A. Hastas, Ruipeng Li, Kui Zhao, Aram Amassian, Neil D. Treat, Martyn McLachlan, and Thomas D. Anthopoulos, High Electron Mobility Thin-Film Transistors Based on Solution-Processed Semiconducting Metal Oxide Heterojunctions and Quasi-Superlattices, Adv. Science, 2, 1500058 (2015)

Organic thin-film transistors (OTFT) are attracting great interest in view of flexible electronics enabling future revolutionizing applications such as flexible displays or wearable electronics. However, for (applications such as) active matrix OLED display driving, the TFT performance regarding transconductance is still (too) low. Even if new organic semiconductors with improved charge carrier mobility are continuously being developed, there is a need for a new TFT design paradigm to further boost the performance of organic transistors.
Here, we present a vertical organic transistor (V-OFET) concept with superior current driving capabilities compared to state-of-the-art horizontal organic TFTs. Within this 3-dimensional V-OFET geometry, the channel length is not defined by the applied patterning technique, but rather by the thickness of the organic layers separating the vertically stacked source and drain electrodes, typically <300nm. This ultra-short channel configuration allows for superior current driving, however, it is usually accompanied by undesired short-channel effects such as a loss of saturation and an increased off-current level.
After introducing the V-OFET concept we discuss how such a device can be fabricated within an industrial process environment as it is used for display backplane fabrication. In particular, we show how surface engineering can be applied in order to effectively suppress short channel effects. In this way, an excellent transistor performance with a very high transconductance (>0.2µS/µm), high cut-off frequency (10MHz), excellent on/off ratio (10⁷), and good operational stability can be achieved.
In the second part of the contribution, we focus on the potential of V-OFETs for active matrix OLED (AMOLED) display driving. By comparing typical TFT design guidelines for vertical and horizontal TFTs we obtain that the V-OFET design leads to a considerable reduction of the area consumption within a pixel which allows either for a higher display resolution, more complex compensation schemes, or a lower power consumption. Due to their favorable layout and their superior transconductance, V-OFETs can be used for AMOLED driving up to a 4k resolution.

Low-temperature (≤500°C) formation of semiconductor-on-insulator with high carrier mobility is desired to realize advanced thin-film transistors for 3-D LSI and system-in-display. Recently, solid-phase crystallization (SPC) of Ge, SiGe, and GeSn on insulator has been intensively investigated. These efforts achieved mobility of 130−140 cm²/Vs,[1,2] exceeding that of poly-Si. To improve the mobility, in the present study, we comprehensively investigate SPC of amorphous GeSn layers on insulator.
In the experiment, amorphous GeSn films with wide ranges of Sn concentration (0−20%) and film thickness (30−500 nm) were deposited on quartz substrates. The samples were annealed (380−500^oC) to induce crystallization.
Firstly, Sn-concentration dependence of mobility for samples (Sn concentration: 0−20%, film thickness: 100 nm) annealed at 450^oC was investigated. With increasing Sn concentration from 0% to 2%, mobility increased; however, it decreased for Sn concentration exceeding 2%. Electron backscattering diffraction (EBSD) measurements indicated that grain size became the maximum for Sn concentration of 2%. It is noted that the optimum Sn concentration (2%) for the maximum mobility is almost equal to solubility of Sn in Ge.
For samples (Sn concentration: 2%) annealed at 450^oC, effects of film-thickness on mobility and grain size were investigated. For thickness ≤120 nm, grain size was almost constant. In addition, mobility increased with increasing thickness. This phenomenon is due to high concentration acceptors (~5×10¹⁷ cm⁻³) near substrates, which was revealed by in-depth analysis using successive Hall measurements combined with layer-by-layer etching. On the other hand, for thickness ≥120 nm, mobility showed the highest value (280 cm²/Vs) for 200-nm thickness, and then both mobility and grain size decreased with increasing thickness. These results indicate that mobility is degraded by grain-boundary scattering due to decreased grain size for thickness ≥200 nm, which is attributed to increased bulk nucleation.
To suppress bulk nucleation in samples (Sn concentration: 2%, thickness: 200 nm), effects of annealing temperature were examined. EBSD measurements revealed that with decreasing annealing temperature, grain sizes increased from ~2 (450°C) to ~4 μm (380°C). As a result, very high mobility of 320 cm²/Vs, which is about 2.5 times as high as reports of Ge[1] and GeSn[2] grown at low-temperature (≤500°C), is achieved at 380°C.
In summary, by controlling film-thickness (200 nm), Sn-concentration (2%), and annealing temperature (380°C), Sn-doped poly-Ge with high mobility (~320 cm²/Vs) is obtained on insulator. This high value of mobility is the top data of semiconductor films grown at low temperatures (≤500°). This SPC technique will facilitate realization of high-performance thin-film transistors for next-generation electronics.
[1] K. Toko, et al., Solid-State Electronics 53, 1159 (2009).
[2] W. Takeuchi, et al., Appl. Phys. Lett. 107, 022103 (2015).

Ionic liquids have received considerable attention in electrochemical device applications due to their outstanding properties including high thermal and electrochemical stability, large ionic conductivity and specific capacitance. To solidify ionic liquid and prepare gel-type thin films, structuring polymers have been blended with ionic liquid. The resulting solid polymer electrolytes, also known as ion gels, have been employed as high capacitance gate dielectrics in thin film transistors and their circuit applications. To deposit ion gels, various solution processing techniques such as solvent casting, spin coating, lamination, screening printing and aerosol jet printing have been successfully demonstrated. Soft-lithographic transfer printing that has been widely used to make thin layers of self-assembled monolayer, organic molecules, polymers, nanoparticles was applied in block polymer based ion gels. More specifically, physically crosslinked ion gels based on poly(styrene-b-ethylene oxide-b-styrene) triblock polymer and 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide were used. In this presentation, another type of physically crosslinked ion gel using random copolymer poly(vinylidene fluoride-co-hexafluoropropylene) and an ionic liquid was fabricated by using transfer printing for the first time on various substrates such as stainless steel, glass, polyimide, PET, paper, and Al foil with different sizes up to 1 in². With these transfer-printed random copolymer ion gels as high capacitance gate dielectrics, thin-film transistors were successfully fabricated on flexible plastic substrates. These transistors operated at low voltages (< 1 V) with reasonably high hole mobility (> 1 cm²/Vs) and on/off current ratio (~10⁵). The Flexible transistors on polyimide exhibited moderate performance degradation ~20 % after 10,000 bending cycles because of the outstanding mechanical strength of the ion gels. Statistical investigations on hole mobility, on/off ratio and turn on voltage suggested excellent reliability of the transfer printing to fabricate random copolymer based ion gels transistors. Therefore, these results demonstrate an attractive deposition technique to employ high capacitance copolymer ion gels on flexible thin film transistors.

Amorphous oxide TFTs are amenable to direct processing on plastic substrates. They possess several characteristics that make them attractive for complex circuit integration. Whereas the typical charge carrier mobility is about 15 cm2/Vs, it is known that significantly higher mobilities can be reached when thin highly doped transport layers are used. We show the use of spatial ALD to reach reproducible mobility of 30 cm2/Vs. Ab-initio calculations reveal more insights into the material system, which can lead to further improvements. Furthermore, unlike amorphous silicon or organic transistors, amorphous oxides are compatible with self-aligned transistor configuration exhibiting high f_T. Finally, they have record-low off-state current, which can be used in circuit design to lower the power consumption. We will relate these different properties to their role in applications, in particular OLED backplanes, integrated gate drivers, and thin-film ICs.
So far, only n-type amorphous oxide semiconductors have been found. Some p-type oxide semiconductors have been shown, but they have lower mobility, are crystalline, and have reverse leakage due to an ambipolar character. We will give insights in the future possibilities regarding oxide as well as organic p-type semiconductors suitable to complement high-performance n-type amorphous oxides.

Oxide semiconductor thin film transistors (TFTs) offer significant performance improvement compared to hydrogenated amorphous silicon (a-Si:H) devices, including >10x higher field effect mobility. Most current oxide semiconductor TFT manufacturing processes use indium gallium zinc oxide (IGZO) deposited by sputtering onto glass substrates. However, this deposition technique, and typically associated post-deposition annealing, present challenges for polymeric substrates. For substrates with imperfections, layer-by-layer deposition processes like plasma enhanced atomic layer deposition (PEALD) can provide improved defect coverage and device yield.

We have used low-temperature PEALD to fabricate ZnO TFTs on few micron thick solution-cast polyimide substrates. The devices use a bottom gate structure with Al₂O₃ gate dielectric and thin (~10 nm thick) ZnO channels, both deposited by PEALD at 200 °C. Solution cast polyimide substrates provide smooth films (few nm rms roughness) and excellent in-plane dimensional stability (ppm range) during processing on carrier substrates. PEALD ZnO TFTs fabricated on thin polyimide substrates have characteristics very similar to devices fabricated on glass, with linear region field effect mobility >10 cm²/V×s at a gate electric field of 2 MV/cm, and i_on/i_off >10⁸. Al₂O₃ passivated devices have excellent stability, and double-gate and tri-layer TFTs provide additional design flexibility. PEALD ZnO TFTs fabricated on thin polyimide survive tens of thousands of cycles of flexing or movement over few mm diameter rollers [1,2]. PEALD ZnO TFTs are interesting core devices for flexible electronic applications.

1. H. U. Li and T. N. Jackson, “Oxide Semiconductor Thin Film Transistors on Thin Solution-Cast Flexible Substrates,” IEEE Electron Device Letters, 33, pp. 35-37 (2015).
2. H. U. Li and T. N. Jackson, “Flexibility Testing Strategies and Apparatus for Flexible Electronics,” IEEE Transactions on Electron Devices, 63, pp. 1934-9 (2016).

Zinc tin oxide (ZTO) is an inexpensive indium-free amorphous oxide semiconductor (AOS) with a wide optical band gap (> 3 eV) and an electron mobility of up to 32 cm²V^-1s^-1 [1]. AOS thin film transistors (TFTs) typically exhibit changes in electrical performance following positive bias stress (PBS) and negative bias illumination stress (NBIS). The dominant origins of AOS instabilities are believed to be interactions between the back channel and ambient, charge injection and trapping in the gate insulator, and creation of semiconductor charge states such as under-coordinated oxygen, metal-metal or metal-oxygen mis-coordination, or oxygen vacancies [2,3]. The first two processes can be minimized by using back channel passivation and high quality gate insulators. To control bulk charge states, AOS can be alloyed with elements that strongly bond to oxygen. Yttrium is an excellent candidate because Y₂O₃ has a large Gibbs free energy and is inexpensive [4].
Here we studied PBS and NBIS in solution-processed bottom gate top contact ZTO and Y-doped ZTO TFTs. In un-passivated TFTs, PBS causes large positive voltage shifts in the TFT transfer curves. Backchannel passivation with 40-nm ALD Al₂O₃ virtually eliminates PBS instability, indicating that its main origin is back channel chemical absorption/desorption. NBIS on un-passivated ZTO TFTs induces large negative shifts in threshold voltage that cannot be fully remedied by back channel passivation. By comparison of experimental results with 2-D numerical device simulations (Silvaco), the main origin of NBIS instability in unpassivated ZTO TFTs was identified to be accumulation of positive trapped charges at the semiconductor-gate insulator interface, whereas the major cause of NBIS instability in passivated ZTO TFTs may be creation of shallow donor states (0.1 to 0.3eV below E_c) either in the bulk or at the semiconductor-passivation layer interface. Our experiments show that creation of shallow states during NBIS was significantly slowed by incorporation of yttrium in ZTO. Since shallow states in AOS are commonly attributed to positively ionized oxygen vacancies, we conclude that yttrium improves NBIS stability by gettering oxygen to reduce oxygen vacancy-related defects. However, incorporation of yttrium at concentrations above 3at% begins to compromise TFT DC performance possibly via creation of deep acceptor states due to alloy disorder or formation of nanometer-scale insulating regions. Due to the multiple roles of Y in ZTO, careful film composition selection is required for optimal Y:ZTO TFT performance.
[1] J.-I. Kim, et al., Appl. Phys. Lett., vol. 99, no. 12, p. 122102, Sep. 2011. [2] J. F. Wager, et al., Curr. Opin. Solid State Mater. Sci., vol. 18, no. 2, pp. 53, Apr. 2014. [3] S. Sallis, et al., Appl Phys Lett, vol. 104, p. 232108, 2014. [4] W. M. Haynes, CRC Handbook of Chemistry and Physics, 95th Edition. CRC Press, 2014.

One of the main issues that need to be addressed in amorphous In-Ga-Zn-O (IGZO) technology is the fabrication of reliable metal–semiconductor field-effect transistors (MESFETs) desired for low-power flexible electronics applications. Previous works on IGZO MESFETs reported devices fabricated only on rigid substrates, since fabrication of reliable Schottky contacts to oxide semiconductors acting as a transistors gate electrodes often requires annealing treatment. Targeting transparent and flexible electronics applications, in the following study we propose fabrication of a-IGZO MESFETs with such transparent conductive oxides as Ru-Si-O and In-Sn-O, acting as Schottky gate electrode and ohmic source/drain contacts, respectively. The electrode materials were chosen to mitigate interfacial reactions with the IGZO channel, which deteriorate the Schottky barrier properties. This allows to avoid the standard post-deposition annealing step, enabling MESFET fabrication on flexible PET and paper substrates.
The chemical composition of the Ru-Si-O Schottky metallization was optimized in order to achieve simultaneously a high oxygen content, low resistivity and high optical transmission. According to X-ray diffraction, all deposited films are amorphous. However, high resolution transmission electron microscopy revealed randomly oriented nanocrystalline inclusions embedded in an amorphous matrix. With the increase in %O₂ one can observe an expansion of the amorphous matrix. The density recorded for the sample deposited without oxygen is 7.3 g/cm³ and the final density is 2.42 g/cm³, close to the density of amorphous SiO₂ (2.19 g/cm³). Atom probe tomography studies enabled to identify nanoparticle as pure ruthenium with a Ru-O shell and the amorphous matrix as SiO₂. Values of work function extracted from internal photoemission spectroscopy changed from 5.65 to 5.85 eV for 0% and 30% O₂, respectively.
The understanding of Ru-Si-O process-property relationship allowed us to introduce Ru-Si-O/a-IGZO Schottky barrier as a gate electrode of MESFET transistors. Fabricated contacts exhibit rectification ratio exceeds 3×10⁵. Schottky barrier heights and ideality factors (n), evaluated by fitting exact solutions of the Schottky diode equation based on the thermionic emission model to experimental I-V curves equal Φ_B = 0.91 eV and n = 1.59 respectively.
MESFETs fabricated on flexible PET and paper substrates present field-effect mobility exceeding 9 cm²/Vs, on-to-off current ratio above 10⁵, and subthreshold swing as low as 210 mV/dec. 3D-printed elements were used to bent PET foil with MESFET structures into a curve with radius in the range of 50 – 5 mm causing tensile mechanical stress. Within the bending radii from 50 to 30 mm the fabricated devices are almost unaffected by mechanical stress, although slight decrease is observed in saturation current. For lower bending radii channel mobility, threshold voltage and subthreshold swing drop of about 10%.

Metal-oxide thin-film transistors (TFTs) with zinc oxide (ZnO) as the semiconductor can have mobility above 20 cm²/V-s, on-off ratios greater than 10⁸, and show good bias stability. However, the back channel of such transistors must be properly treated to achieve the best results. Early studies showed that aluminum oxide layers deposited on the back-channel in bottom-gate (inverted) TFTs improved the stability enormously, although often at the cost of a negatively shifted turn-on voltage.*

In this talk we will discuss the effect of different treatments of the back-channel of ZnO TFTs fabricated by spatial atomic layer deposition (SALD). In our definition, the “back-channel” is the surface of the ZnO semiconductor that is furthest from the gate contact. Thus it can refer not only to the top surface of the semiconductor in a bottom-gate geometry, but also to the interface between the substrate and the semiconductor when a top-gate geometry is employed. Empirically, when the ZnO back-channel is in contact with an organic material such as a polymer, the turn-on and threshold voltage are above zero; in contrast, when the back-channel is in contact with an inorganic material, such as a glass substrate or an aluminum oxide layer, the turn-on voltage is negative. This electrical response provides an additional knob for designing enhancement and depletion mode TFTs and circuits. Thus a mixture of top- and bottom-gate devices can be used to provide the depletion-mode load and enhancement-mode drive TFTs for an inverter, or alternatively, all bottom-gate devices can be differentiated into enhancement- and depletion-mode by choice of material for the first passivation layer. We will illustrate results from the application of these techniques to both planar and vertical TFTs.


*D. A. Mourey, Mitchell S. Burberry, D. A. Zhao , Y. V. Li, S. F. Nelson, L. Tutt, T. D. Pawlik, D. H. Levy, T. N. Jackson, Journal of the SID 18/10, 2010.

Thin-film transistors (TFTs) based on oxide semiconductors are promising candidates for use in flexible organic light-emitting diode (OLED) displays on plastic substrates, because they can provide the high mobility necessary to drive OLED devices and they can be fabricated at temperatures of less than 300 °C. Generally, oxide semiconductor films are deposited by sputtering in a vacuum chamber. Recently, however, solution processes that do not require vacuum equipment have been extensively studied, with the goal of realizing a simple low-cost fabrication method. One problem with general solution processes is that a baking temperature of more than 400 °C is usually required in order to achieve high mobility, because it is necessary to reduce the amount of impurities in the semiconductor film. In contrast, the use of aqueous solutions can allow solvent evaporation and oxide formation at low temperatures, leading to the possibility of fabricating high-performance TFTs [1]. In the present study, bottom-gate TFTs using aqueous solution-processed InGaZnO (IGZO) films baked at a temperature of 300 °C were fabricated, and the effects of thermal annealing following the formation of the source and drain electrodes on the IGZO film and the adaptability of the backplane process for OLED displays were investigated. It was found that thermal annealing at a temperature of 300 °C led to an increase in the field-effect mobility from 0.7 to 2.1 cm²/Vs, and suppression of the hysteresis in the transfer characteristics. Next, we fabricated a 5-inch OLED display using these TFTs at temperatures of less than 300 °C and confirmed that moving images were successfully displayed on the screen. It was found that the aqueous solution-processed IGZO-TFTs are applicable to the low-temperature backplane process. Furthermore, a solution-processed organic gate insulator was applied to aqueous solution-processed IGZO-TFTs that had a top-gate structure in order to simplify the fabrication process and improve the flexibility. Switching behavior was observed for these TFTs, but the mobility was lower than that for the bottom-gate structure. A compositional analysis along the film thickness direction using Rutherford backscattering spectrometry showed that the In content at the top of the IGZO film was lower than that at the bottom. This may be the principal reason why the mobility is lower for top-gate structures than for bottom-gate structures. To improve the mobility, it is therefore necessary to optimize the composition of the IGZO film.
[1] K. H. Lee et al., ACS Appl. Mater. Interf. 5 (2013) 2585.

We have developed solution processed oxide thin film transistors for large area electronics.
We designed and processed high-k dielectrics (Y₂O₃, ZrO_x, AlO_x, ZAO...) and oxide semiconductors (IZTO, IGO...).
We have reached field-effect mobilities exceeding 100cm²/Vs.
By careful choice metal ratios in the oxide semiconductor, process condition and device optimization, we can obtain highly reliable and stable TFT swith variation of V_th of less than 0.1V within 1hour of temperature gate bias stress.

Solution-processed oxide thin film transistor (TFT) has remarkably received attention for low fabrication cost and simple fabrication process. However, it has inferior electrical performances compared to vacuum processed oxide TFT. In order to enhance electrical performances of solution-processed oxide TFT, many researchers have investigated various engineering such as materials, structure, and post treatment. In particular, for material engineering, solution- processed high-k gate insulator has recently been researched to solve aforementioned issue. However, conventional solution-processed high-k gate insulator needs high temperature annealing process to obtain satisfactory electrical performance so it has a limitation for applying various flexible substrates that have low glass transition temperature. In this paper, we propose a simple method for reduction of fabrication temperature for HfO_x gate insulator with thermally purified solution (TPS). Fabrication method of TPS is that we thermally process HfO_x solution around boiling temperature of solution on hot plate just ‘before’ film deposition. High temperature can evaporate residual gas and other components in solution which can form defect sites so that essential energy to reduce defect can be reduced. Thus, TPS process successfully decreased film formation temperature of solution-processed HfO_x gate insulator from 350^oC to 200^oC. In addition, TPS has improved surface energy by low surface tension and contact angle resulting high film attachment with substrate. Thus, TPS processed HfO_x gate insulator has better electrical characteristics such as breakdown electric field (from 4.16 MV/cm to 6.23 MV/cm) and leakage current density (from 10^-7 A/cm² to 10^-9 A/cm²) compared to those of conventional solution-processed HfO_x gate insulator. After depositing sputtered In-Ga-Zn-O film and evaporated Al electrodes, TPS processed TFT exhibits higher mobility (35.76 cm²/Vs) and on/off current ratio (1.19 x 10⁴) than those of conventional TFT. Consequently, TPS processed HfO_x film plays superior role of gate insulator so that the TFT can have improved electrical characteristics at low temperature.

Inorganic metal oxides are competitive materials for pixel drivers in next generation displays, offering high-performance and good transparency. Solution-processing of metal oxides can allow efficient material use and scalable large area processing. However, the organic solvents predominantly used in metal oxide inks add cost and complexity to roll-to-roll manufacturing since environmental regulations require solvent capture and organics necessitate high-temperatures to decompose carbonaceous species. This work addresses these challenges by developing aqueous, carbon-free inks for fabricating transparent metal oxide thin film transistors (TFTs) at low temperatures. These inks’ fluid properties are optimal for inkjet printing transparent conductive electrodes and semiconductors with low line-edge roughness, high-uniformity, and no coffee-ring.

Highly conductive (ρ < 10 mΩ cm) transparent electrodes based on aluminum-doped cadmium oxide (ACO) present a new material for printed inorganic electronics. The optical and electrical properties of these conductors, as well as their crystallinity and microstructure, were investigated as a function of the low temperature annealing (220 °C – 300 °C) conditions and aluminum doping concentration. To demonstrate their suitability for high-performance transparent electronics, TFTs with ACO source / drain electrodes and InO_x semiconductors were prepared exclusively from aqueous solutions of metal nitrates (Al(NO₃)₃, In(NO₃)₃, Cd(NO₃)₂) at ≤ 250 °C. Competitive device performance was achieved with a champion mobility of µ_lin = 19 cm²/Vs and average performance of µ_lin = 11.0 ± 4 cm²/Vs, SS = 200-300 mV/dec, and I_on / I_off > 10⁷_. This work represents the first demonstration of printed aqueous metal oxide conductors and semiconductors, a step towards realizing transparent, printed electronics that do not depend on vacuum-deposited electrodes.

GaN is a widely used semiconductor, finding its commercial applications in several areas including, high power electronics, optoelectronics, and microwave electronics. Despite having excellent electrical and optical properties, the use of this material is limited to conventional rigid substrates, mainly due to the high deposition temperature of the GaN epi-layers. In order to introduce this material into the low temperature applications, several methods are employed. Among the applied methods, atomic layer deposition has offered the most promising results with our demonstration of the TFTs with GaN channels fabricated with a thermal budget lower than 250°C, the lowest processing temperature level for the nitride based electronic devices. Up to now, the nitride based electronic and optoelectronic devices have been realized on flexible substrates only via transferring method, which carries the potential risk of decreasing the yield of the devices, which therefore prevents the commercialization of the proposed devices. In this study, we demonstrate bottom gated TFTs with GaN channel layers directly built on flexible polyethylene naphthalate (PEN) substrates, for the first time. Thermal budget of the device processing steps is below 200°C, which breaks our previous lowest thermal budget record.
Flexible TFT fabrication starts with the solvent based cleaning of the PEN substrates. 100 nm thick Al thin film is deposited via thermal evaporation at room temperature, and this layer serves as the gate of the TFTs. 200nm thick SiO₂ thin films are deposited with e-beam evaporation and patterned via lift-off technique. This is followed by the growth of 77-nm-thick Al₂O₃ and 11-nm-thick GaN subsequently deposited at a single ALD process, at 200 °C. Active device areas are isolated by BCl₃-based dry etching of the GaN layer. Source and drain contacts are formed by e-beam evaporation of the metal stack consisting of Ti/Au (30/150 nm).

Output electrical characteristics of the ALD-based GaN TFTs on flexible substrates show that fabricated devices have clear pinch-off and saturation characteristics, and they exhibit n-type field effect transistor behavior. Transfer characteristics of the devices reveal the I_ON/I_OFF ratios as high as 2x10³. The threshold voltage of the device is extracted from the transfer characteristics and it is found to be 2.5 V. Charge mobility in the channel is extracted in the linear region of the device operation and calculated to be 0.025 cm²/V-sec. This particularly low mobility can be attributed to the nanocrystalline structure of GaN thin films, and the surface states at the semiconductor insulator interface. Finally the effect of the positive gate bias stress on threshold voltage of the devices is studied and devices are shown to be extremely stable. This study is believed to pave the way for the nitride based stable and fully transparent flexible electronics upon further materials and process optimization.

The ultrathin flexible active-matrix organic light-emitting diode (uf-AMOLED) technology is in the limelight because it has higher refresh rates, faster response time, and lower power consumption than passive-matrix. Thin film transistor (TFT) backplane technology is essential to the fabrication of AMOLED displays. In TFT backplane technology, above all, oxide TFTs is vital switching and driving component, due to its high mobility, low leakage current, high speed, and current-density. In this paper, we report an ultrathin, flexible, transparent, and high performance oxide TFT array via inorganic based laser lift-off (ILLO) process on PET substrate of 4 μm thickness. The flexible oxide TFT array on ultrathin PET substrate enabled to attach anywhere, successfully operated with outstanding electrical performance, and showed the reliable operation of NMOS inverter circuit.

In recent year, amorphous oxide thin film transistors(TFTs) have attracted interest of applications for flexible organic light emitting diodes(OLEDs). For reasonable oxide TFTs, the requirements such as high mobility and good stability at low temperatures should be satisfied. In this study, we chose double channel layers to solve the issues of oxide TFTs at low temperature and we successfully fabricated top gate ZITO/ ZITO:AlZr TFTs. After low-temperature annealing process at 250°C, V_th of -0.75V, SS of 0.16V/decade and mobility(u_FE) of 18.8 cm²/V s were achieved. At the PBTS(positive bias temperature stress) test, the oxide-TFT exhibited △V_th of 0.42V at 40°C for 1hour.

Much research to date has been devoted to synthesizing new polymers or improving existing polymers in order to overcome the performance limits of the conventional organic thin-film transistor (OTFT): (1) a rather low channel mobility (< 20 cm²V^-1s^-1) requires a supply voltage well above 2 V for an on-/off-current ratio of > 10⁵; (2) the formation of a relatively poor-quality interface between the polymeric channel and the gate insulator would induce a large off-state leakage current well above 10^-13 A; (3) asymmetric pairs of n- and p-type OTFTs result in noncomplementary switching. All these would affect the overall power consumption at the transistor and circuit levels and hence at the system level. In this meeting, we propose and demonstrate a polymer-based electrostatically-actuated microelectromechanical (MEM) relay comprising multiple input and output electrodes, namely, double gates, double bodies, and double pairs of source/drain, in order to enable efficient implementation of large-area portable and/or wearable electronics for the internet of things requiring ultralow-power operation, structural flexibility, visual transparency, low-cost, and low-temperature processing. Firstly, we show that fabricated devices exhibit typical relay I-V characteristics including zero off-state leakage current, steep transitions to the on-/off-state with an input swing less than 60 mV for a decade change in the output current (I_ds), and a relatively high on/off current ratio of > 10⁸, and that they can endure a finite number of hot- and cold-switching cycles. Secondly, we examine the effect of similar and dissimilar contact materials on the surface adhesion force (and hence hysteresis voltage) and the on-state current. Thirdly, we explore the dependence of the threshold pull-in voltage (V_pi) on input voltage combinations, and demonstrate basic two-input logic gates: AND, OR, and XOR and a four-input carry generation: (A XOR B) AND (C XOR D) via adjusting the biases applied to a single dual-gate dual-body relay.

Oxide semiconductors are considered as a good alternative to silicon for a transparent electronics, due to its high field-effect mobility and on/off ratio. Recently, there are many attempts to develop transparent phototransistors using oxide semiconductors. However, the photocurrent of oxide semiconductors can be observed only when the device is exposed to a high-energy photon, such as a ultra-violet light, because oxide semiconductor has a wide band gap. Therefore, we decorated small band gap cadmium selenide (CdSe) quantum-dots (QDs) on the oxide semiconductor phototransistors to increase the photocurrent for a low-energy light, i.e., visible light. The oxide phototransistors, decorated with QDs, showed significantly increase in photocurrent when exposed to visible light due to the QDs. Measurements to construct an energy level diagram were made using ultraviolet photoelectron spectroscopy to determine the origin of the photocurrent, and we found that the small band gap of CdSe QDs enables the increase in photocurrent in the oxide semiconductor phototransistors. The device characteristics and origin of the photocurrent will be presented in detail. The result would provide a promising method for developing highly transparent photosensors based on oxide semiconductors and QDs.

We investigated the advanced physical electronic properties and characterizations of 2-dimentional nano film assembly of metal-organic frameworks (MOFs) based on 5,10,15,20-tetrakis(4-carboxyphenyl)porphyrin by self-organization of Cu(NO₃)₂ secondary building units (SBU) in situ. The main challenges lie in the choice of suitable self-assembly monolayer (SAM) to control the growth of epitaxial layers on a gold surface and the amalgamation of conductive ligands which is suitable for molecular electronic applications.
MOF multilayer thin films were deposited from solution on a gold surface pre-functionalized with 4-mercaptopyridine (MP) via incubation in a glove box, which was connected to an ultra-high vacuum system outfitted with photoelectron spectroscopy (PS). This enabled to determine the full electronic structures via the combination of ultraviolet photoelectron spectroscopy (UPS) and inverse photoemission spectroscopy (IPES), and also evaluated the growth mode of the nano film via X-ray photoemission spectroscopy (XPS) measurements. The UPS and IPES data agreed very well with the density functional theory (DFT) calculations of the density of states (DOS), thus setting paradigms for their implementation in bottom-up and self-assembled nano electronic devices.

Recently, the demands for flexible device are growing rapidly in parallel to the expansion of the wearable device market. Two- and three-dimensional conventional inorganic materials are used for the device fabrication, but it is difficult to apply in flexible device because of its rigid property. However, one-dimensional inorganic materials are applicable to the flexible devices because of its flexible nature. It is noteworthy that the flexible device can be fabricated only when all component parts such as substrate, electrode, and gate insulator (GI) have flexibility. The substrate and electrode can have flexibility by using polymer substrate and metal nanowire (NW), respectively, but the GI using high-k inorganic materials has a rigid characteristic. To overcome this problem, we have used one-dimensional Si NWs as the channel material and the flexible ionic liquid as the GI.
In this study, p-type Si NWs were synthesized by using electroless etching method. The Si NWs were transferred on polyimide (PI) substrate by using the Langmuir-Blodgett method for the alignment of nanowires. Thereafter, Au was deposited on aligned Si NWs as source-drain electrodes. The ion gel consisting of polymer finely blended with an ionic liquid was deposited on the exposed Si NWs between Au electrodes, as the flexible GI. Morphology of Si NWs and structure of device were investigated by scanning electron microscope and optical microscope. The electrical properties of the transistor as a function of bending cycle were measured by semiconductor-parameter-analyzer in order to confirm the flexibility of the device. The mobility, on-off ratio, V_th, and S.S were found to be stable even after 10,000 cycles of bending test.



Keywords: P-type Si nanowire, Ion-gel gate insulator, Flexible FET, Electroless etching method, Langmuir-Blodgett alignment.

ALD has been a key deposition method for oxide semiconductors, due to its high conformal characteristics and controllability of compositions. ALD carries on alternating exposures of precursor vapors, which chemisorb on the substrate surface in a self-limiting manner to deposit films in an atomic layer-by-layer fashion. Therefore, it is easy to control the stoichiometric composition and film thickness. There are several reactants such as, O₂ plasma, O₃, H₂O and H₂O₂ for the oxide ALD. According to these reactants, film’s quality and growth characteristics can be greatly changed. In this paper, we studied characteristics of O₂ plasma reactant and O₃ reactant for the comparison.

We adopted indium oxide which is known as excellent transparent conducting oxide (TCO) and zinc oxide which have semi-conductor characteristic for the film analysis and fabrication of TFTs. Up to now, some precursors have been known for indium oxide such as, InCp (Cyclopentadienyl indium), INCA-1 (Bis(trimethy-silyl)-aminodiethyl-Indium) and DADI (Dimethyl-Aminopropyl-Dimethyl-Indium). Among these, DADI has been rarely studied although it have some advantages. For example, it makes good thin films which have reasonable cost, good purity and low contamination. In contrast, InCp is too expensive to fabricate and INCA-1 contains silicon so that it has the possibility of silicon by-product contamination. In this study, we tried to use DADI as a precursor for indium oxide thin film.

Here, we have utilized a multi-layer structure comprising of InOx/ZnOx layers to realize high-performance TFTs. The TFT with InOx/ZnOx multi-layer structure is fabricated by plasma enhanced atomic layer deposition (PEALD) and ozone processed atomic layer deposition with varying the number of InOx and ZnOx cycles. This well controlled multi-layer structures are expected to induce improved electric and optical performance due to its convenience of chemical composition control resulting in high mobility transistors. The obtained characteristics of the InOx/ZnOx multi-layer films were analysed using TEM, XRD, and XPS. Through this work, we accomplished 30.3 cm²/V●s of field effect mobility, 0.14 V/dec of sub-threshold swing and about 85% of transmittance. So, we saw potential possibility about transparent large area display’s back-plane.

Acknowledgment

1. This research was financially supported by the "Sensitivity touch platform developmnet and new industrialization support program" through the Ministry of Trade, Industry & Energy (MOTIE) and Korea Institute for Advancement of Technology (KIAT)

2. This work was supported by Institute for Information & communications Technology Promotion(IITP) grant funded by the Korea government(MSIP) (B0117-16-1003, Fundamental Technologies of two-dimensional materials and devices for the platform of new-functional smart devices)

Recently, 1-D nanostructures, such as semiconductor nanowires (SiNWs), have emerged as interesting materials for the fabrication of high-performance transistors with electronic performance comparable to and in some cases exceeding that of the highest quality single-crystal materials. Preparation of crystalline SiNWs is the use of metal-assisted chemical etching, where solution-nucleated metal plays the important role of a nanoscale electrode in the electrochemical etching of a single-crystalline Si wafer. The metal nanoparticles, such as Ag, oxidize Si that is in contact with them by taking electrons from Si. The oxidized Si, or SiO2, is then etched away by HF in the etching solution, leaving a pit or hole on the Si surface. Finally, Si nanostructures result from areas where no metal is present. This can be done even at room temperature without involving high temperature, low pressure, or costly equipment and hazardous materials, which makes metal-assisted chemical etching simple, easy, and economical. Here, we report on studies of transparent and printable thin-film transistor (TFT) devices based on SiNWs. The NW-based devices exhibit uniform characteristics with average field-effect mobilities exceeding 100 cm2/Vs. The nanowires can be aligned and selectively deposited via spray gun under air pressure as a result of evaporation-induced polar solvent flow. Prototype nanowire-based TFT (NW-TFT) devices on glass substrates showed excellent optical transparency and transistor performance in terms of transconductance, threshold voltage range, and on/off ratio. High on-currents and field-effect mobilities were obtained from the NW-TFT devices even at low nanowire coverage. The SiNWs-based TFT approach offers a number of desirable properties such as low growth temperayure, high electron mobility, and optical transparency and low operation voltage, and may lead to large-scale applications of transparent electronics on diverse substrates.

The solution process is a simple and low-cost thin film deposition method that enables a large area coating and high throughput because it can circumvent the need for photolithography and vacuum deposition. Direct patterning can be processed with screen printing, imprinting, ink-jet printing, and electrohydrodynamic-jet printing. Among them, inkjet printing is an attractive technique in device fabrication for the direct pattern writing and precise materials delivery. Recently, spin-coated double-active layer oxide TFTs, in which heterostructured channels, were reported to obtain improved electrical properties at relatively low processing temperatures. However, inkjet printing can provide a patterned active layer structure and give better properties compared to a simple spin-coated one.
To achieve the optimized electrical properties of an inkjet-printed double-active layer, the ZTO TFTs with various compositions of In₂O₃ solutions were examined. By controlling the annealing temperature and indium content, heterostructured In₂O₃/ZTO TFTs with improved mobility, threshold voltage and bias stability were obtained. The best electrical properties of the inkjet-printed double-active layer ZTO TFTs were obtained with 0.01 M of In₂O₃: a mobility of 8.6 cm²/ V s, a threshold voltage of 2.76 V, a subthreshold slope of 0.52 V/dec, and an on-to-off current ratio of 10⁶ . The electrical properties of the inkjet-printed double-active layer oxide TFTs were superior to those of the single-active layered TFTs.

Oxide Semiconductors have been paid attention to suitable TFTs for OLED because of higher mobility than a-Si TFTs, lower leakage current than LTPS TFTs and even low cost. These oxide thin films can be obtained by simple solution process and applied to printed electronics. Printing process is a way to reduce cost and process time effectively over tranditional vacuum process and photo-lithography by direct patterning. Nevertheless, semiconductor films, in most study of solution processed oxide TFTs, are fabricated by spin coating, which is inadequate for electronics industry. For this reason, researches for various printing methodes on oxide TFTs are needed certainly. Electrohydrodynamic-jet (EHD-jet) technique is avilable to form a fine pattern by electric fields between metal stage and tiny orfice tip.
We opimized EHD-jet printning conditions for IZO solution and fabricated with addition patterning technique IZO TFT sucessfully showing better and stable features than spin coated one. The EHD-fabricated IZO TFTs showed good characteristics at an annealing temperature of 400 and 500 ^oC. The positive and negative bias stability was also characterized. The EHD jet-printed IZO TFTs showed good electrical properties: mobility of 4.8 cm /Vs, threshold voltage of 8.4 V, on-to-off current ratio of , subthreshold slope of 1.2 V/dec at 400 ^oC. The positive and the negative bias stress of the EHD-jet printed IZO TFTs were characterized. No negative shifts in the EHD-printed IZO TFTs were observed at process temperatures of 300 and 400 ^oC under negative bias stress.

Hydrogen (H) induced performance degradation of semiconductor devices has been a serious problem [1]. Aluminum oxide (Al₂O₃), high-k dielectric material, films were employed for many kind of devices [2,3] and found to provide a high-quality H barrier. It is reported that the H trapping performance of an Al₂O₃ film strongly depends on the annealing temperature [4]. Therefore, a systematic study of the annealing temperature dependence of H behavior in Al₂O₃ films is of great importance in order to fully understand its H trapping properties. Laser-assisted atom probe tomography (APT) was reported to be a powerful method for obtaining three-dimensional (3D) elemental distributions in semiconductors and insulators with nearly atomic resolution. For APT measurement, due to the adsorption of residual gas from the APT vacuum chamber onto the apex of the needle specimen, a direct quantitative analysis of H in a sample is challenging issue. Here, we propose that the residual gas in the APT raw data can be eliminated with appropriate methods. In this study, the annealing temperature dependence of the H concentration and distribution in Al₂O₃ film deposited on Si substrates was investigated [5].
An Al₂O₃ film was grown on a Si(100) substrate. First, the Si substrate surface was cleaned by RCA process. Then, a 10-nm-thick Al₂O₃ film was deposited by atomic layer deposition using sequential exposures of trimethylaluminum and H₂O at 300 °C. Lastly, a polycrystalline Si cap layer of approximately 100-nm-thick was deposited on the Al₂O₃ film by low-pressure chemical vapor deposition at 620 °C. Samples were then annealed at 800-1200 °C for 10 min in a vacuum chamber. A commercial local electrode atom probe (LEAP4000X HR, Cameca Instruments Inc.) equipped with an UV pulsed laser (355 nm) was employed for APT analysis.
The H ions from the residual gas were effectively eliminated from the raw APT data by adjusting the evaporation rate during the APT measurement as the number of H ions adsorbed from the residual gas is inversely proportional to the evaporation rate (defined as the number of ions evaporated per laser pulse). Our APT results demonstrate that H ions piled up in the Si substrate/Al₂O₃ interface region in the as-grown sample, H pile-up disappeared after annealing at 900 °C or higher. Moreover, the concentration of H in the Al₂O₃ film decreased with increasing annealing temperature. This research enables to extend to study the H behavior in Al₂O₃ film involved in the state-of-the-art 3D devices.
This work in Tohoku University was supported in part by JSPS KAKENHI Grant Numbers 26289097 and 15H05413.
References
[1] Y. Nagano et al., VLSI Technology Digest of Technical Papers (2003) p. 171.
[2] Y. Shin et al., IEEE IEDM Technical Digest (2005) p. 327.
[3] K. Yoshitsugu et al., Phys. Status Solidi C, 10 (2013) 1426.
[4] B. Yang et al., Appl. Phys. Lett. 79 (2001) 2064.
[5] B. Han et al., submitted.

Organic field-effect transistors (OFETs) with a heterojunction structure were fabricated and the relationship between the performance characteristics with copper phthalocyanine (CuPc) and the dioctyl perylene tetracarboxylic diimide (PTCDI-C8) heterojunctions and the thickness of the PTCDI-C8 layer is investigated. The changes of the electrical parameter are attributable to the morphology of the film and the heterojunction effect. Moreover, the heterojunction OFETs were used as the nitrogen dioxide (NO₂) gas sensors, and the sensing properties were characterized with the variation of PTCDI-C8 layer thicknesses, compared to the device with single CuPc active layer, OFET sensors with the optimized film thickness of 0.5 nm PTCDI-C8 and 7 nm CuPc had one order of magnitude enhancement of sensitivity, enabling a detection limitation of NO₂ as low as 2 ppm. The sensitivity enhancement was attributed to the intensification of the charge transfer in the heterojunction structure while introducing the oxidizing gas of NO₂. This study provides a promising prospect for the application of OFET in room temperature, low-cost and high sensitivity NO₂ gas detectors, and describes the importance of active layer thickness to optimize the sensing properties of OFETs.

We report an effective strategy for independently tuning the threshold voltage (V_TH) of thin-film transistors (TFTs) without degrading field-effect mobility. Our approach is based on using zinc oxide (ZnO)/hafnium oxide (HfO₂) multilayer stack as a transistor channel. By optimizing the different layer thicknesses in the multilayer channel stack, enhancement mode transistor operation is achieved. The optimized TFT devices showed saturation field-effect mobility of 14.2 ± 0.9 cm²/V.s along with V_TH of 0.1 ± 0.1 V, which represents significant improvement over previous results. Our approach is shown to be effective for obtaining enhancement mode TFTs, while maintaining high mobility and low subthreshold swing, which makes the multilayer ZnO-based devices attractive for various applications.

We present that the hole and electron transport properties in an ambipolar semiconducting polymer can be controlled with thermal annealing. We also show that the split-gate structure offers more accurate characterization for the hole and electron transport parameters such as saturation (µ_sat.), linear mobility (µ_lin.), turn-on (V_to), and threshold voltage (V_th) than conventional ambipolar transistor does. As a result, well-balanced hole and electron conduction could be achieved in an ambipolar semiconducting poly-(diketopyrrolopyrrole-terthiophene) (PDPP-3T). It was also observed that hole de-doping (electron doping-like) occurred with thermal annealing, which removed the dipole formation by atmospheric oxygen. Such a recuperation from the atmospherically doped to intrinsically un-doped state changed the characteristics in hole and electron transport, which agreed with the shift in the measured ultraviolet photoelectron spectroscopy (UPS) spectrum. A complementary logic inverter with balanced charging and discharging was demonstrated based on the findings.

Unique features of π-conjugated organic semiconductors, such as charge generation, transport, and recombination properties, are depending on the materials and their interfaces. Especially, in organic field-effect transistors (OFETs), the channel region, between semiconductor and dielectric layer, is intensely important for charge transport and their electrical property. In addition, organic phototransistors (OPTs) basically have the same structure of OFETs with combining photodiode properties, that results in the controlling the channel conductance via absorption additional light. As using the organic π-conjugated molecules for semiconductor layer in OPTs, the unusual properties of organic molecules, such as photogenerated exciton, and charge separation for generating excess charge carriers, can be used for the photogenerated charges which can play a critical role in the devices. In this study, for OFETs based novel applications, such as OPTs and integrated circuit, solution processed P-N heterojunction bilayer can be developed by using p-, n-type conjugated polymers and orthogonal solvents. OFETs based on bilayer conjugated polymers semiconductor have been researched for controlling charge transport in channel region of the device, and fabricated ambipolar based CMOS-like inverter. Moreover, the photo response is investigated at the P-N interface via illumination with generating of photocurrent which is including in channel region of the device.

Recently, the flexible transparently substrates for substituting flexible electronics to existing inorganic substrates have been actively researched. To fabricate the flexible electronics devices, polymeric substrates have usually used such as PET, PEN, PC, PES, etc. However, these substrates have problem that is difficult recycle after use and need long time for biodegradation. Thus, we have developed a flexible transparent substrate using starch that is eco-friendly material substituting old polymeric substrates for the flexible OFETs. Starch substrate enables realization of large area, simple cheap process and has good stability in the aprotic solvents such as toluene or hexane. Also, it has advantage in reducing environmental pollution after service life due to biodegradability. Lastly, we evaluated the usefulness of starch substrate for the flexible electronics and demonstrated the device performance of manufactured organic transistors.

Vanadium dioxide (VO₂) shows huge resistivity change at around room temperature with metal-insulator transition (MIT). New functional devices utilizing this drastic change have been energetically studied. Among them, controlling of MIT by an electric field is especially expected toward the realization of Mott transistor. In this research, we fabricated a side-gate-type field-effect transistor (SG-FET) via air gap with a VO₂ nano-wire channel. We have focused on characteristics of SG-FET capable of controlling various kinds of gas atmospheres such as humid air, dry air and reactant gases as chemical and/or electrostatic reaction fields. In this study, we tried to modulate channel resistance by a pure electrostatic field effect under dry N₂ atmospheres.
VO₂ thin films were deposited on TiO₂ (001) substrate and Al₂O₃ (0001) substrate by using a pulsed laser deposition technique and formed the pattern of SG-FET by using nanoimprint lithography method. The change rate in resistance (, defined as (R_off-R_on)/R_off, where R_off and R_on is the resistance of off-bias and on-bias states, respectively) on Al₂O₃ (0001) substrate is 0.4% at gate bias V_G = 30 V, while the rate on TiO₂ (001) substrate is 4.5%, which is 10 times higher than that using Al₂O₃ (0001) substrate. It is considered that the huge difference was caused by obtaining single crystalline epitaxial VO₂ on TiO₂ (001) substrate. Furthermore, the change rate in resistance depend on wire width of VO₂ channels, that is, when reducing wire width of VO₂ channels from 3000 nm to 300 nm on TiO₂ (001) substrate, resistance modulation ratio enhanced from 0.7 % to 4.5 %. This indicated the advantage of nanowire and the modulation rate will be drastically enhanced in narrower width. In this symposium, we will show the detail data for difference of the change rate in resistance between in-plane polycrystalline VO₂ on Al₂O₃ (0001) substrate and of single crystalline VO₂ on TiO₂ (001) substrate, and width of VO₂ nanowire dependence of the change rate.

Hybrid printed complementary inverter circuits can be manufactured by using an n-type inorganic transistor, based on a metal oxide active layer, and a p-type organic semiconductor transistor. Some studies have shown that, among the several possibilities available to produce inverter circuits, the hybrid complementary inverter is the most stable and most promising in terms of device performance. In the current work, we present studies of zinc oxide (ZnO) transistors obtained by spray pyrolysis of an organic precursor salt (zinc acetate dehydrate). The morphological and optical properties of the spray-produced ZnO films were characterized by atomic force microscopy (AFM) and UV-Vis and FTIR spectroscopy for different deposition conditions. The transistors were manufactured by spraying the zinc acetate solution (in methoxyethanol) over substrates made of a 200 nm SiO₂ layer (which acts as the transistor dielectric layer) which was thermally grown on top of a p-type, highly conductive, Si wafer, used as the transistor gate electrode. The Si/SiO₂ substrates were heated up at temperatures between 200^oC to 400^oC during the spray deposition, in order to promote a more efficient pyrolysis of the organic precursor. After the film deposition, a further annealing in the same range of temperature was performed. The device is completed by the thermal vacuum evaporation of the drain and source electrodes (100 nm thick aluminum layer). The transistor I_on/I_off ratio, threshold voltage (V_T) and charge-carrier mobility (µ) presented a strong dependence on the pyrolysis and annealing temperatures. The I_on/I_off ratio presented variations from 10³ to 10⁸, the threshold voltage, from +15 to +5 V and the carrier mobility (electrons) from 1.0x10^-3 to 3.2 cm²/Vs, for the pyrolysis and/or annealing temperatures varying from 200^oC to 400^OC. The electrical properties, including AC characterization of zinc oxide films, are discussed based on thermal analysis of the ZnO precursor, performed by differential scanning calorimetry (DSC) and thermogravimetric analysis (TGA). The results presented in this work show that ZnO based transistors, obtained with lower pyrolysis temperatures (about 200^oC), due to spray deposition, are compatible with flexible substrates, matching with printed organic transistors to be applied to hybrid inverter circuits.

Along with the attention on the solution-based metal-oxide thin-film transistors (TFT), many novel processes have been introduced to achieve high performance TFTs at low temperature. Among them, flash lamp annealing (FLA) process has attracted huge attention with its simple process condition and short process time, less than 5 min. In this study, we introduce a new water-assisted FLA (W-FLA) process to achieve high performance solution-based indium-gallium-zinc-oxide (IGZO) TFTs. In(NO₃)₃, Ga(NO₃)₃, Zn(NO₃)₂ were dissolved in 5 ml 2-methoxyethanol with 0.1 M as a precursor and spin-coated on a Si wafer with thermally grown SiO₂ (100 nm). As-spun films were pre-annealed at 120°C for 10 min and treated by FLA under ambient condition for 15 sec. Then, the films were dipped in the water dish and treated by FLA for 15 sec. W-FLA on the first flash lamp annealed IGZO thin film is likely to decrease oxygen vacancies by absorption of water molecules. With the W-FLA treatment, IGZO TFTs show a high current on/off characteristics, whereas the untreated TFTs show conductive characteristics. Overall, W-FLA process recovers the imperfection of metal-oxide thin-film, such as oxygen vacancies, and enhanced electrical performances of IGZO TFTs (mobility: 1.17 cm²V^-1s^-1, current on/off: ~10⁶).

To enhance electron injection in n-type organic field-effect transistors (OFETs), a non-conjugated polyelectrolyte (NPE) layer was interposed between a [6,6]-phenyl-C₆₁-butyric acid methyl ester (PCBM) layer and Au electrodes. Novel NPEs with various counterions (Cl^-, Br^-, I^-) improved the electron mobilities up to ~10^-2 cm²V^-1s^-1 and on-off ratios (I_on/I_off) of 10⁵. Ultraviolet photoemission spectroscopy (UPS) indicates that reduced electron injection barrier at NPE/metal interface was induced by dipole formation and led the improved electron injection and transport. These findings are important for understanding how NPEs function in devices, improve the device performance, and design of new materials for use in optoelectronic devices.

Hydrogen doping has been studied as one of the effective methods for improvement of electrical performance in amorphous oxide semiconductor (AOS) thin-film transistors (TFTs). However, it is difficult to apply to AOSs TFTs because hydrogen causes critical deterioration of instability as well as works as a donor by forming –OH bond. Hence, hydrogen causes serious instability under negative bias temperature stress (NBTS) and negative bias illumination stress (NBIS). In this study, we propose hydrogen radical doping (HRD) method without instability degradation by hydroxyl radical reaction on highly-hydrophilic surface. HRD is a new doping method that can not only improve electrical characteristics but also enhance stability of amorphous oxide TFT. Highly-hydrophilic surface is firstly made by UV irradiation resulting in a complete wettability property and defective components: metal defects, oxygen vacancies. And then, by dipping in hydrogen peroxide solution, hydroxyl radical (OH*) is effectively decomposed on the highly hydrophilic surface and reacts with defective components in IGZO film by chemisorption. IGZO film can be doped hydrogen by forming OH bond using HRD. Therefore, IGZO film used HRD can decrease defect sites; V₀ ⁽²⁺⁾ + OH* and increase stable metal oxide bond; M⁺ + OH*. As a result, IGZO TFT used HRD has superior electrical performances. The mobility increased from 10.9 to 17.5 cm²/Vs, on-off ratio increased from 1.05 x 10⁸ to 3.96 x 10⁹, subthreshold slope decreased from 0.44 to 0.31 V/decade, negative V_th shift (NBTS test at 50°C) decreased from 2.4 to 0.4V, and positive V_th shift (PBS test) decreased from 5.0 to 3.4V. We believe that this research can contribute to extend oxide TFTs to high resolution and large size OLED display backplane. Moreover, it can be easily applied to manufacturing line due to simple method without vacuum system.

In this work, present low temperature flash light based curing of spray coated high-k zirconium
oxide (ZrOx) thin film to realize low voltage operated flexible and fully patterned organic field
effect transistors (OFETs). ZrOx was prepared by sol-gel technique using a metal-organic
precursor. An alternative spray coating method offers both casting and patterning of Zr-based gel
film simultaneously in a simple and cost effective way. On the other hand, flash light curing
process which is very fast and low temperature method allows using polymeric flexible substrate.
Several spray and flash curing parameters were carefully optimized to achieve uniformly thick
ZrOx film with high dielectric constant (k). Elemental and micro structural analysis confirms that
flash light irradiation to the samples causes formation of ZrOx film from the metal-organic
compound based gel. Coated ZrOx films of 12-15 nm in thickness on flexible chromium/gold
(Cr/Au) coated Polyethyene terephthalate (PET) substrate exhibited low leakage current density
below 10-7 to 10-6 A/cm2 at -3 V and high dielectric breakdown strength V >4 V. Finally using
this patterned ZrOx film as gate dielectric layer and thermally evaporated pentacene as
semiconducting layer flexible thin film transistor was fabricated which functioned at low voltage
(below −3 V). Field effect mobility and ON/OFF ratio of as fabricated transistor is found to be as
high as 1.2 cm2V-1S-1 and 105 respectively.

Germanium thin films have previously been employed as the semiconductor channel to produce high speed thin film transistors (TFT’s). ¹ It is well established that the maximum driving current in inorganic group IV based thin film transistors (TFT’s) can be increased using semiconductor channels with larger average grain sizes due to a higher field effect mobility. ² The predominant technologies used to deposit inorganic group IV semiconductor channels for TFT’s have relied mainly on chemical and physical vapor deposition based techniques. While low temperatures (~ 300 ^oC) have been employed to deposit amorphous group IV semiconductors, crystalline material generally requires much higher temperatures (≥ 600 ^oC) which can limit the fabrication processes and compatible materials.³ Electrochemical liquid-liquid solid (ec-LLS) growth is a developing technique providing a low cost method to electrodeposit crystalline group IV and III-V semiconductors (Ge, Si, GaAs and GaSb) at temperatures ranging from 25 - 90 ^oC. ⁴ The low temperatures employed to deposit these crystalline semiconductors via ec-LLS could provide the benefits of both low temperature processing as well as enhanced field effect mobility (compared to amorphous counterpart) for TFT’s. In ec-LLS a liquid metal electrochemically reduces ionic precursors and dissolves the component atoms of the semiconductor in order to achieve a supersaturation and promote the growth of the crystalline semiconductor from the liquid metal solvent. ⁴ In this account ec-LLS was used to grow continuous epitaxial films of p-type Ge on a silicon substrate over an area of roughly 3 cm² at 90 ^oC from an aqueous electrolyte containing dissolved GeO₂. The epitaxial character and grain size of the films was confirmed with electron backscatter diffraction, rocking curve X-ray diffraction and atomically resolved scanning transmission electron diffraction. While preliminary measurements of the films electrical properties were performed using a 4-point probe. Chemical mechanical planarization was performed on the as-deposited films to achieve a surface roughness of ~ 5 nm and to demonstrate the viability of subsequent processing and deposition. The prospects and efforts of integrating these Ge films into devices and depositing the films on insulating substrates is also discussed.

References:
(1) Morii, K.; Iwasaki, T.; Nakane, R.; Takenaka, M.; Takagi, S. IEEE Electron Device Letters 2010, 31, 1092.
(2) Shahrjerdi, D.; Hekmatshoar, B.; Mohajerzadeh, S. S.; Khakifirooz, A.; Robertson, M. Journal of Electronic Materials 2004, 33, 353.
(3) Voutsas, T.; Nishiki, H.; Atkinson, M.; Hartzell, J.; Nakata, Y. Shapu Giho/Sharp Technical Journal 2001, 36.
(4) Fahrenkrug, E.; Maldonado, S. Accounts of Chemical Research 2015, 48, 1881.

Printable, flexible electronics has emerged as a promising means to fabricate wearable sensors, bioelectronics devices, and displays. Thin film transistors are an essential building block for these devices. Electrostatic double layer gating using ionic liquids (ILs) has been demonstrated as a means to achieve low voltage switching in a variety of semiconductors. While such devices operate reversibly within a window of electrochemical stability, electrochemical changes can still occur in the semiconducting layer changing the mechanism of transport and causing hysteretic effects. We will discuss our recent work to understand and control electrochemical effects in metal oxide thin films gated by ILs. Through the addition of polyphenol additives to the IL gate, we have achieved significant enhancements in operational stability of zinc oxide films through chemical control of reversible redox-reactions. We will also discuss recent efforts to use polymerized ionic liquids to gate semiconducting polymers. In these systems only one ion can undergo significant mass diffusion and this constraint has a strong influence on their properties as gates. Prospects for designing hybrid devices that leverage electrochemical effects will be discussed.

The optical, electrical, and magnetic properties of many functional oxides can be switched by their non-stoichiometry, i.e. oxygen excess or deficiency and protonation. For example, WO₃, known as an electro-chromic material, is basically transparent insulator, but it becomes blue colored metal by protonation (H_xWO₃). SrCoO_2.5 with Brownmillerite structure is known as insulating non-magnet, but it can be changed into SrCoO₃ with Perovskite structure, which is ferromagnetic metal. Thus, multifunctional memory devices, which can switch optical transmission and electrical conductivity or magnetism and electrical conductivity, can be realized by using functional oxides, but the switching classically needs high-temperature heating or electrochemistry in liquid electrolyte, which is unsuitable for practical applications. In order to overcome these difficulty, we have developed ‘liquid-leakage-free water’, in which water molecules are infiltrated in a nanoporous glass [1, 2]; by using liquid-leakage-free water as a gate insulator of three-terminal device with thin film transistor (TFT) geometry, the water is expected to be a strong reductant (H⁺) as well as an oxidant (OH^-) for functional oxide active layer. Herein we show the water-gated TFTs on several functional oxide layers for reversible switching of optical, electrical, and magnetic properties at room temperature in air atmosphere [3-5]. The present device concept will provide novel multifunctional memory devices.

[1] H. Ohta et al., Nature Commun. 1, 689 (2010).
[2] H. Ohta et al., Adv. Mater. 100, 173107 (2012).
[3] T. Katase et al., Adv. Electron. Mater. 1, 1500063 (2015).
[4] T. Katase et al., Adv. Electron. Mater. 2, 1600044 (2016).
[5] T. Katase et al., Sci. Rep. 6, 25819 (2016).

Metal oxides are among the most interesting materials for next generation electronics due to their superior electrical properties, high reliability and easy reproducibility. Amorphous metal oxides are attracting great interest, with a recent emphasis on flexible transparent electronics. [1,2] TiO₂ and SnO₂ are very promising oxide materials that already found applications in sensing, photovoltaic, optoelectronic devices and batteries.
We fabricated, both on rigid and flexible substrates, electrolyte-gated (EG) TiO₂ and SnO₂ transistors making use of high surface area activated carbon (AC), as a gate electrode, and the ionic liquid (IL) 1-Butyl-3-methyl imidazolium bis(trifluoromethylsulfonyl)imide [EMIM][TFSI], as the gating media. Thin films of metal oxides have been deposited by thermal evaporation and sol gel techniques and were photolithographically patterned as transistor channel materials.
To explore the effect of the double layer capacitance on device performance we investigated bottom-contact top-gated transistor where we varied the area of the active layer in contact with electrolyte and the area of overlap of source/drain electrodes with the gate. To shed light on the doping mechanisms of such transistors we performed electrical measurements, cyclic voltammetry and electrochemical impedance spectroscopy. We demonstrated that patterning improves the performance of electrolyte- gated TiO₂ transistors with respect to their unpatterned counterparts. Patterned EG TiO₂ transistors show threshold voltages of about 0.9 V, ON/OFF ratios as high as 1 × 10⁵ and electron mobility above 1 cm²/(V s). [3]
We believe that these simple architecture devices working at low voltages are promising for low cost, flexible and large area electronics.

[1] Banger K.K., Yamashita Y., Mori K., Peterson R.L., Leedham T., Sirringhaus H., Low-temperature, high-performance solution-processed metal oxide thin-film transistors formed by a ‘sol–gel on chip’ process. 2011, Nature Materials, 10, 45–50.
[2] Hong, K; Kim, SH; Lee, KH; Frisbie, CD. Printed, sub-2V ZnO Electrolyte Gated Transistors and Inverters on Plastic. Adv Mater, 2013, 25, 3413-3418.
[3] Valitova I., Kumar P., Meng X., Soavi F., Santato C., Cicoira F., Photolithographically patterned TiO₂ films for electrolyte-gated transistors, ACS Appl. Mater. Interfaces, 2016, in press (10.1021/acsami.6b01922).

Recently, transition metal dichalcogenide (TMDC) monolayers, such as molybdenum disulfide (MoS₂) and tungsten diselenide (WSe₂), have attracted strong attention as novel two-dimensional (2D) semiconducting materials due to their large bandgap (1−2 eV) and excellent transport properties. Moreover, the thickness of monolayer TMDCs is less than 1 nm, which is one of the thinnest materials, and it leads to strong confinement effects, resulting in large binding energy of exciton (> 100 meV) and formation of charged excitons. Particularly, due to their layered structure, there are no dangling-bond states on the surface of TMDC monolayers and it could be an ideal quantum well. Here, we will report the electrical, optical and thermoelectric properties of TMDC monolayers films.
In this study, we fabricated ion-gel-gated EDLTs (Electric Double Layer Transistors) using large-area TMDC monolayers, MoS₂ and WSe₂, grown by chemical vapor deposition [1-9]. The Fermi level of TMDCs can be continuously shifted by applying gate voltage, and we can induce both hole and electron transport in these devices. The hole mobility of WSe₂ can be enhanced up to 90 cm²/Vs at high carrier density of 10¹⁴ cm^-2, whereas the MoS₂ showed electron mobility of 60 cm²/Vs. By the combination of p-type WSe₂ and n-type MoS₂, we fabricated CMOS inverters.
Based on these technique, we realized pn junction by EDL carrier doping, and performed electroluminescence and photo-detection by diode structure, so called EDLED (Electric Double Layer Light-Emitting Diode) and EDLPD (Electric Double Layer Photo-Diode). Moreover, we also investigated Fermi energy dependence of thermoelectric conversion properties in TMDC monolayers using EDLT technique. As the results, we observed clear enhancement in thermoelectric properties due to the low-dimensional effect.

[1] J. Pu, L.-J. Li, T. Takenobu, et al., Nano Lett. 12, 4013 (2012).
[2] J.-K. Huang, T. Takenobu, L.-J. Li, et al., ACS Nano. 8, 923 (2014).
[3] J. Pu, L.-J. Li, T. Takenobu, et al., Appl. Phys. Lett., 103, 23505 (2013).
[4] J. Pu, L.-J. Li and T. Takenobu, Phys. Chem. Chem. Phys., 10.1039/C3CP55270E (2014).
[5] Y.-H. Chang, T. Takenobu, L.-J. Li, et al., ACS Nano. 8, 8582 (2014).
[6] C.-H. Chen, T. Takenobu, L.-J. Li, et al., 2D Materials, 1, 034001 (2014).
[7] L. Chu, T. Takenobu, G. Eda , et al., Scientific Reports, 4, 7293 (2014)

Flexible thin films organic transistors are actively explored as devices to amplify the signal of sensors in order to improve sensitivity. Combining sensing function with a transistor leads to a smart pixel that can easily be addressed in a sensor array, thus creating imaging detectors. One of the key parameter to map is the temperature as foreseen in applications such as electronic skin. One if the temperature sensor found on the skin of shark and other predator animals is based on an ionic thermoelectric effect. Up to now, the ionic Seebeck coefficients of electrolytes were too small compared to the operating voltage of organic transistors, such that temperature sensing could not be amplified properly.
Here, we successfully integrated the concept of ionic thermoelectric gating of a low-voltage organic transistor. The low-operation voltage (<1V) of the transistor is obtained by the strategy of utilizing electric double layer gate. The high thermovoltage is obtained with the recently found polymer gel electrolyte with a Seebeck coefficient reaching close to 10 mV/K. Besides demonstrating the temperature sensing amplification by this combination, we also show that it is possible to operate logic circuit with an input heat. This finding blaze the trail for new heat-gated electronic circuits with potential applications going further than just e-skins.

Closed-shell macromolecules, especially π-conjugated polymers have been the main stream charge transporting materials for various organic electronic applications, including transistors. Despite their impressive progress, there are still a number of demands for more functional potentials. To satisfy these critical demands, we demonstrate a new class of non-conjugated oxidation-reduction (redox) active polymer transistors with open-shelled, charge transporting macromolecules, radical polymers. The radical polymer allows for the rapid electron transfer between its stable radical sites which is persistent even under ambient conditions. The charge transport mechanism of a model radical polymer, poly(2,2,6,6-tetramethylpiperidine-1-oxyl methacrylate) (PTMA), is established for the first time through the introduction of an electrochemically-gated organic thin film transistor. In this system, the ion-gel gate allows for electrochemical ion (cation or anion) penetration into the main channel PTMA layer through the application of a gate bias. Furthermore, because of the ability of non-conjugated PTMA to undergo oxidation or reduction, application of a positive or negative gate bias affords a transparent transistor with ambipolar behavior. We have established that the ion gel activated charge mobility and conductivity values of PTMA are on the same order of magnitude as common conjugated semiconducting polymers at low gate biases (Vg = ± 2 V). In addition, electrochemical doping of the PTMA layer increases the conductivities by a factor of 100 – 1,000 as well as produces ON/OFF current ratios of ~10⁴. Thus, this work provides great promise in using radical polymers in a myriad of solid-state organic electronic applications.

Neuromorphic devices are very promising in offering neuroinspired computational paradigms beyond traditional von Neumann architecture. Several solid-state technologies including memristive, phase change, spintronic and ferroelectric devices, are being used for hardware implementation of the basic functional building blocks of neural processing, namely the various forms of synaptic plasticity. Devices that offer interface with biological systems, such as organic bioelectronic devices, are just beginning to be explored as potential neuromorphic platforms. Here we demonstrate orientation selectivity, a neuromorphic function that is inspired by the visual cortex cells, using a poly(3,4ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) organic electrochemical transistor. A multi-gated organic electrochemical transistor is used in this work, in order to correlate spatially distributed inputs with the output of the device, and thus to create a weighted coupling between the multiple inputs and the output. The demonstration of spatiotemporal processing in an organic electronic device paves the way for neuromorphic devices with new form factors and a facile interface with biology.

Printed electronics was proposed for applications in the fields of flexible displays, wearable, or ubiquitous electronics. Among its benefits, the compatibility of the fabrication techniques and materials with flexible, low-cost substrates and the prospect of economically convenient mass production of electronic devices.
Despite the notable advancements achieved, the optimization of some desirable figures of merit still has to be addressed appropriately to credibly enable the implementation of this technology for a wide range of real applications. Primarily, a transistor operation frequency suitable for more demanding applications must be guaranteed (e.g. more than 10 MHz in the case of RFID-based item-tracking systems) and secondly a low-cost, industrially scalable production flow must be developed to convey the optimized electrical performance which is requested.
The optimization of high-frequency operation is largely determined by a number of factors: first, the reduction of the device channel length and of the parasitic capacitances insisting between the device electrodes. At the same time, high-mobility semiconducting materials and techniques yielding optimal charge injection properties at the contact/semiconductor interface must be employed.
Here, we combined and optimized three industrially scalable techniques (inkjet printing, femtosecond laser sintering, bar-coating) to fabricate high-frequency Organic Field-Effect Transistors (OFETs) via a scalable production flow. Thanks to the high-resolution patterning capability offered by laser processing we realized conductive electrodes as narrow as 1.4 µm and channel lengths shorter than 2 µm. The combination of high-resolution direct-writing of electrodes with the optimal effective charge mobility of bar-coated poly[N,N′-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5′-(2,2′-bithiophene) (P(NDI2OD-T2)) guaranteed that the realized OFETs exhibited maximum operation frequency of 20 MHz.
This performance was achieved with the sole employment of scalable techniques for the definition of the critical features for a high-frequency OFET (the semiconductor mobility, the channel length, the geometrical overlap between the gate electrode and the source/drain), proving that the fabrication of high-frequency devices under the constraints required by the industry is practicable.

Low voltage Organic Field-Effect Transistors (OFETs) are fundamental building blocks for novel, portable electronic systems fabricated over plastic substrates at relatively low costs. Low voltage operation is generally obtained with the employment of ultra-thin dielectrics, which requires small area techniques, such as spin coating and physical vapor deposition, to be reliably fabricated.
Therefore a reproducible fabrication process for low voltage OFETs with high throughput large area techniques is still substantially missing. The activity here described is devoted to the definition of reliable approaches to low voltage OFET fabrication with large area techniques, with particular focus on the optimization of the fabrication of gate dielectrics.
The first investigated strategy consists on the integration of two large area techniques easily up-scalable to the industrial size, namely inkjet printing and chemical vapor deposition (CVD). Parylene C, which can be deposited in nanometer-sized films over large areas by CVD, was considered as gate dielectrics in OFETs. Such thin dielectric layers (tens of nanometers) were employed in combination with optimized inkjet-printed electrodes, patterned using different conductive inks, to define the transistor structure. Also the organic semiconductor active layer was deposited by inkjet printing: in particular, TIPS pentacene was employed. A proper optimization of the ink and of the printing parameters, allowed obtaining OFETs with ideal features, i.e. low threshold voltage (< 2 V), significantly high mobility (of about 0.1 cm²/Vs) and low leakage current (in the range of picoAmpere). Bias and mechanical stress test show the good stability of the structure where continuously biased and bent.
Starting from these results, the employment of a solution processable dielectric was investigated towards the fabrication of all-inkjet-printed OFETs. In particular, an home-made ink based on polyvinyl phenol (PVP) was considered. Several cross-linking agents have been tested to optimize the ink formulation; printing setup, as well as drying and cross-linking processes and final layer thickness, were investigated. To verify the dielectric features, electrical and morphological characterization has been carried out. Finally, the dielectric has been tested as gate insulator in transistor structures with printed silver as gate electrode, inkjet printed PEDOT:PSS as source and drain and TIPS pentacene as active layer. The fabricated devices can be operated at voltages as low as 1V, showing hole mobility up to 0.8 cm²/Vs and remarkably low leakage currents (10 pA). Such result represents a promising proof for the feasibility of the proposed ink for gate dielectric fabrication. Ongoing activities are related to the optimization of the printing process for all the transistor elements, with a particular attention devoted to the dielectric surface properties for its proper interfacing with organic semiconductors.

Organic field-effect transistors (OFETs) are expected to be used for next-generation low-cost IoT electronic film devices because of their mechanical softness and compatibility with mass-producible printing technologies. Among various OFET devices, printable single-crystal OFETs with a high carrier mobility above 10 cm²/Vs have advantages for relatively high-speed applications such as RF-ID tags and integrated logic circuits in sensor devices. However, equally crucial to achieve high-frequency response is to achieve low contact resistance because the influence is more pronounced in shorter-channel configurations. Reducing contact resistance is the most important challenge for high-mobility semiconductors to demonstrate their apparent benefit in achieving higher-speed transistor operation . Here, we focus on high-mobility single-crystal OFETs with only two-monolayer organic semiconductors because such ultrathin molecular layers are indeed favorable to minimize resistance of accessing the charge-accumulated channel in the top-contact geometry.
Organic single-crystal films were coated by continuous edge-casting technique, by which inch-size single crystalline films can be obtained.[1] We selected a p-type organic semiconductor material, 3,11-dioctyldinaphtho[2,3-d:2’,3’-d’]benzo [1,2-b:4,5-b’]dithiophene (C₈–DNBDT–NW), which is more soluble in organic solvent than previously reported compound, C₁₀–DNBDT–NW.[2] This improved solubility contributed to lower the process temperature to 60–70 °C, leading to fabrication of extremely-thin organic crystalline films. The thickness of the single crystal was measured by AFM to be approximately 8 nm, which corresponds to two-monolayer film. We fabricated several transistors with different channel length by vacuum depositing source and drain electrodes on top of the two-monolayer single crystal. The mobility estimated by the slope of typical transfer-curve in linear regime is as high as 13 cm²/Vs.
The contact resistance (R_c) of the two-monolayer transistors is estimated employing the transmission line method (TLM). In order to study the effect of film thickness on R_c, we estimated the R_c of three-monolayer transistors as a reference. The result indicates that the contact resistance of the two-monolayer transistors is less than one fifth of that of three-monolayer devices. Interestingly, the difference appears to be more drastic at lower gate voltages, which can be beneficial in low-voltage operation. The estimated value of R_cW of the two-monolayer devices is 46.9 Ωcm at the gate voltage of -30 V, which is actually the lowest contact resistance reported for any OFETs in literature.

[1] J. Soeda, T. Uemura, T. Okamoto, C. Mitsui, M. Yamagishi, and J. Takeya, Appl. Phys. Express 6, 076503 (2013).
[2] C. Mitsui, T. Okamoto, M. Yamagishi, J. Tsurumi, K. Yo-shimoto, K. Nakahara, J. Soeda, Y. Hirose, H. Sato, A. Yamano, T. Uemura, and J. Takeya, Adv. Mater. 26, 4546 (2014).

Organic thin film transistors (OTFTs) have been extensively investigated for next-generation electronic devices. However, many of OTFTs still suffer from high driving voltage more than 15 V to achieve high mobilities and sharp on-off ratio. To handle this issue, increasing capacitance of dielectric layer (C_i) is imperative. High-k dielectric layer via atomic layer deposition (ALD) is beneficial for increasing C_i. However, the abundant –OH functionality and ionic polarization between the carrier and the high-k ionic lattice cause hysteresis, drop of mobility, and shift of threshold voltage in OTFTs. Low mechanical flexibility of the layer is also another issue, which hinder the broad use of the ALD layers to the application for flexible electronics.
Applying non-polar low-k polymer is a way to solve these problems by passivating surfaces and releasing the interfacial stress of oxide dielectrics. However, most of the low-k polymer/oxide dielectrics reported so far were suffering the reduction of C_i, due to the thickness of applied polymer (typically larger than 50 nm, at least) for avoiding dewetting or pinhole formation. Furthermore, most of the processes for the organic buffer layer rely on solution-based processes, which limits the productivity due to the process incompatibility. In this regard, alternating deposition of high-k inorganic layer and ultrathin organic layers commonly via vacuum process will be desirable to minimize the process incompatibility. Initiated chemical vapor deposition (iCVD) is a promising method to deposit ultrathin polymer thin films onto the ALD layer. Furthermore, the similarity of the iCVD and ALD processes has enabled the integration of two processes as a one-step deposition system, which is capable of depositing iCVD polymer and ALD inorganic layers in a single chamber.
In this presentation, we demonstrate a bilayer-structured hybrid dielectric layer with ultrathin thickness (< 15 nm) for OTFTs through a single chamber system of ALD and iCVD. The hybrid dielectric layer consist of iCVD poly(1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3) and ALD Al₂O₃. The entire layer can be deposited in a one-step process with a low temperature (~90 °C), which is highly advantageous in terms of throughput and efficiency of the entire device fabrication process. It turned out that the hybrid dielectric layer generally exhibited reduced hysteresis and interfacial trap densities of OTFTs, leading to a substantial improvement of the device performance. Also, excellent bias stress stability during the long-term operation could be achieved, thanks to the passivation of polar surface of Al₂O₃. Furthermore, the resulting 15 nm-thick hybrid layer withstands the tensile strain up to 4 %, far superior than the mechanical flexibility of ALD layer. Coupled with the process temperature of lower than 90 °C, this will be beneficial to design the various kinds of flexible, soft electronics onto the thermally vulernable substrates.

Small molecular organic semiconductor crystals form interesting electronic systems of periodically arranged “charge clouds” whose mutual electronic coupling determines charge coherent over fluctuating molecules. This presentation focuses on methods of reducing molecular fluctuation [1,2], which strongly restricts mobility of charge carriers in single-crystal organic transistors, using ultra-thin organic semiconductor crystal films.
We grew a-few-monolayer thick single-crystal films of decyldinaphthobenzo-dithiophene derivatives (Cn-DNBDT) on a plastic substrate so that uniaxial force is applied by bending the samples. It is crucial to use such ultrathin crystal films to reproducibly apply strain because the surface of the plastic substrates and the semiconductor films are to be deformed in the same rate without either slippage or mechanical break. We examined the reproducible modification in crystalline structure and inter-molecular phonon vibration repeatedly as the function of applied strain.
At maximum, 3% strain is uniaxially applied without any damage to the sample so that room-temperature mobility increased by the factor of 1.7 [2]. The measured mobility is 9.7 cm²/Vs without strain, and it significantly increases up to 16.5 cm²/Vs under 3% strain. Analysis using X-ray diffraction (XRD) measurements and density functional theory (DFT) calculations reveal the origin to be the suppression of the thermal fluctuation of the individual molecules, which is consistent with temperature dependent measurements. The findings show that compressing the crystal structure directly restricts the vibration of the molecules, thus suppressing dynamic disorder.
High performing organic semiconductors are usually obtained by increasing the mobility through synthesizing novel molecules, improving processing conditions or combining various materials. Here, we showed a new way to increase the mobility in organic single-crystal transistors by taking advantage of the inherent softness of organic semiconductors. The crystal lattice is compressed by deforming a flexible substrate, which directly improves the charge transport properties.
[1] K. Sakai, Y. Okada, T. Uemura, J. Tsurumi, R. Häusermann, H. Matsui, T. Fukami, H. Ishii, N. Kobayashi, K. Hirose, and J. Takeya, Nature Asia Mater. 8, e252, (2016).
[2] T. Kubo, R. Häusermann, J. Tsurumi, J. Soeda, Y. Okada, Y. Yamashita, N. Akamatsu, A. Shishido, C. Mitsui, T. Okamoto, S. Yanagisawa, H. Matsui, and J. Takeya, Nature Commun. 7,11156 (2016).

The organic permeable base transistor (OPBT) represents a fascinating approach to achieve excellent transistor performance from organic semiconductors. OPBTs take advantage of the special property that thin metal films do not necessarily form closed layers when deposited onto molecular layers but rather have pinholes. When applied as a permeable base electrode, these self-formed nano-porous metal films can control the vertical charge flow between two adjacent organic semiconductor layers. Similar to organic light-emitting diodes, all layers are stacked in a sandwich geometry, allowing simple fabrication techniques as well as using inexpensive low-resolution structuring.

Recently, we demonstrated superior OPBT performance [Klinger et al., Adv. Mater. 27, 2015] reaching current densities of 10 A/cm² at an operation voltage of 1 V. In pulsed operation, current densities as high as 1 kA/cm² can be achieved. For an active area of 200 µm times 200 µm, this corresponds to a switchable current of 400 mA. Thus, organic transistors are now entering an operating range in which very significant current and power can be switched, only limited by the self-heating of the device. Furthermore, despite their very simple fabrication method, these devices achieve excellent speeds for organic transistors with a transition frequency of 10 MHz at 16 mA. Although 1 kA/cm² cannot be applied in DC mode, many applications can benefit from our achievements. Wherever capacitances have to be charged in short time, a high transition frequency and a high current density are beneficial, e.g. in a pixel driving circuit of a display this will allow for increasing the repetition rate and thus an increase of the number of pixel lines.

In this contribution, we will also discuss in detail the working principles of the devices. Experimental results are complemented by detailed three-dimensional drift-diffusion simulations. They demonstrate that in the on-state of the OPBT, even the small openings of the base electrode do not limit the current density. Instead, the space-charge limited current in the intrinsic semiconductor region in the emitter as well as in the collector part restricts the maximum possible current. Therefore, future optimization strategies will focus on minimizing the semiconductor layer thickness while preventing electrical short-circuits and on improving the charge carrier mobility in vertical direction. Here, the general scientific trend of increasing lateral field-effect mobilities should be extended towards increasing the bulk mobility of organic semiconductors. Then, an additional performance boost by a factor of 10 to 100 is within reach.

Organic transistors are the core element for the realization of full-organic electronic circuitry. Performance, down-scaling, and integration are the key challenges to fulfill the requirements of target applications in displays and flexible electronics. Recently, progress has been reported mainly on the active channel area of lateral organic field effect transistors (OFET), both in miniaturization and charge transport performance. For successful device integration, these achievements need to be complemented by simultaneous progress at the contact area.
In this contribution, we demonstrate the positive effect of electrically doping the organic semiconductor at the source contact in both conventional lateral OFET and recently developed vertical OFET (VOFET) [1] devices. In p-type pentacene transistors, introducing a small quantity of dopant molecules strongly improves charge injection into the organic semiconductor. The transfer length required for current injection is reduced by more than one order of magnitude, leading to values below 2 µm even at high gate fields. The conductivity of the device can be improved by more than two orders of magnitude and the on/off ratio by one order of magnitude. These improvements pave the way towards high performance applications and high frequency operation with the simultaneous possibility of further reducing the contact size and, thus, the footprint area of organic field-effect transistors.
[1] Kleemann et al., Small (2013), doi: 10.1002/smll.201202321

Nanolamination has entered the spotlight as a novel process for fabricating highly dense nanoscale inorganic alloy films. Organic Thin-Film Transistors (OTFTs) commercialization requires, above all, excellent dielectric properties of gate dielectric layer. Here, we describe the fabrication and characterization of Al-O-Ti (AT) nanolaminate gate dielectric films using a PEALD process, and their OTFT applications. The AT films exhibited a very smooth surface (R_q < 0.3 nm), a high dielectric constant (17.8), and a low leakage current (8.6 × 10^-9 A/cm² at 2 MV/cm) compared to single Al₂O₃ or TiO₂ films. Importantly, a 50 nm thick AT film dramatically enhanced the value of μ_FET (0.96 cm²/Vs) on a pentacene device, and the high off-current level in a single layer TiO₂ film was effectively reduced. The nanolamination process removes the drawbacks inherent in each single layer so that the AT film provides excellent dielectric properties suitable for fabricating high-performance OTFTs. Triethylsilylethynyl anthradithiophene (TES-ADT), a solution-processable semiconductor, was combined with the AT film in an OTFT, and the electrical properties of the device were characterized. The saturation I_D and V_th values measured in the films agreed well with the κ values. However, in AT laminate film, quite low leakage current near single Al₂O₃ and the highest μ_FET value was observed. The highest μ_FET value could be explained in terms of two antithetical hypotheses regarding the effect of κ: (1) A higher value of κ can attract more mobile carriers into the channel, and allows to fill traps near the interface at relatively low values of V_G. (2) A higher κ value can broaden the DOS near the edge of the conduction/valence bands, leading to trap formation. The enhanced electrical performances of the TiO₂ and AT nanolaminate OTFTs were predominantly influenced by the former mechanism rather than by the latter; however, the latter mechanism played a decisive role in determining difference in μ_FET in the AT nanolaminate and TiO₂. Our results suggest new approaches to gate dielectric research geared toward developing high-performance OTFTs.

Charge injection at metal/organic interface is a critical issue for organic electronic devices in general, as poor charge injection would cause high contact resistance and severely limit the performance of organic devices. In this presentation, we will present a new approach to enhance the charge injection by using atomic layer deposition (ALD) to prepare an ultrathin vanadium oxide (VO_x) layer as an efficient hole injection interlayer for organic field-effect transistors (OFETs). Since organic materials are generally delicate, we first develop a new low-temperature ALD process for VO_x at 50 °C using a highly volatile vanadium precursor of tetrakis(dimethylamino) vanadium and non-oxidizing water as the oxygen source. The process is able to prepare highly smooth, uniform, and conformal VO_x thin films with precise control of film thickness. With this ALD process, we demonstrate that the ALD VO_x interlayer is able to remarkably reduce the interface contact resistance, and, therefore, significantly enhance the device performance of OFETs. Multiple combinations of the metal/VO_x/organic interface (i.e. Cu/VO_x/pentacene, Au/VO_x/pentacene, and Au/VO_x/BOPAnt) are examined, and the results uniformly show the effectiveness of reducing the contact resistance in all cases. Employing ALD to prepare high-quality well-controlled ultrathin interlayer is not only technologically promising for organic electronics in general, but also opens new paths for studying fundamental problems with interfacial charge injection.

In the last few years exciting advances have been achieved in developing printing techniques for organic semiconductors, and impressive mobility values have been reported for the resulting organic field-effect transistors (OFETs). However, not all these techniques are scalable and some of them require additional crystallization steps, preventing the integration of these semiconductor devices into real circuit applications. Recently, we reported the bar-assisted meniscus shearing (BAMS) of an organic semiconductor blend based on a small semiconducting molecule (DB-TTF) and an insulating polymer (polystyrene).[1] This solution coating technique resulted in highly crystalline thin films that showed ideal OFET characteristics. Aiming to extend the applicability of the BAMS technique to other organic semiconductors, this study reports on the fabrication of OFETs employing blends of four benchmark organic semiconductors (TIPS-PEN, diF-TES-ADT, C8-BTBT and DT-TTF) with polystyrene and demonstrates that applying the same formulation and experimental conditions for printing them, highly reproducible and uniform crystalline films exhibiting high OFET performance are successfully achieved.[2] It is noted that the mobility values achieved here are not the highest reported for the studied materials; however, they are state-of-the-art values and could be regarded as exceptional considering the low cost and fast speed of the fabrication process involved here.

References:
[1] F. G. del Pozo, S. Fabiano, R. Pfattner, S. Georgakopoulos, S. Galindo, X. Liu, S. Braun,M. Fahlman, J. Veciana, C. Rovira, X. Crispin, M. Berggren, M. Mas-Torrent, Adv. Funct. Mater. 2016, 26, 2379.

[2] I. Temiño, F. G. del Pozo, M. R. Ajayakumar, S. Galindo, J. Puigdollers, M. Mas-Torrent, Adv. Mater. Technol. 2016, DOI 10.1002/admt.201600090.

Organic thin film transistors (OTFT) offer great potential for use in flexible electronics. Much of this potential lies in the solution processability of the organic polymers enabling both roll coating and printing on flexible substrates and thus greatly reducing the material and fabrication costs. We have fabricated an OTFT in ambient air, on a PET flexible substrate. The printing technique is very similar to the one used for printing newspapers and has low environmental impact in comparison with traditional electronics. This is because is made at lower temperature than you would normally use for baking a cake. After implementing the transistor we build a small demonstrator circuit to operate a printed electrochromic surface powered by an organic solar cell all realized with the same technique.

The footprint of organic electronic technologies is important when united in complex circuitry. We present flexible organic power transistors prepared by fast (20 m min−1) roll-to-roll flexographic printing of the drain and source electrode structures, with an interspace below 50 um, directly on polyester foil[1]. The devices have top gate architecture and were completed by slot-die coating of the organic semiconductor poly-3-hexylthiophene and the dielectric material polyvinylphenol before the gate was applied by screen printing. We explore the footprint and the practically accessible geometry of such devices with a special view toward being able to drive large currents while handling the thermal aspects in operation together with other organic printed electronics technologies such as large area organic photovoltaics (OPV) and large area electrochromic displays (EC). We find especially that an elevated operational temperature is beneficial with respect to both transconductance and on/off ratio. We achieve high currents of up to 45 mA at a temperature of 80 °C with an on/off ratio of 100 which is sufficient to drive large area organic electronics such as an EC device powered by OPV devices that we also demonstrate. Finally, we observe a significant temperature dependence of the performance which can be explored further in sensing applications.

[1] Francesco Pastorelli, Thomas M. Schmidt, Markus Hösel, Roar R. Søndergaard, Mikkel Jørgensen and Frederik C. Krebs, " The Organic Power Transistor: Roll-to-Roll Manufacture, Thermal Behavior, and Power Handling When Driving Printed Electronics", Volume 18, Issue 1, pages 51–55, January 2016, doi: 10.1002/adem.201500348

Polysilicon CMOS TFTs are fabricated on large area, flexible stainless steel foils using novel ink depositions within a hybrid printed/conventional process flow. A self-aligned top gate TFT structure is realized with an additive materials approach to substitute the use of high capital cost ion implantation and lithography processes. Polyhydrosilane-based silicon ink is coated and laser crystallized to form the polysilicon channel. Semiconductor grade P-type and N-type unique dopant ink formulations are screen printed and combined with thermal drive in and activation to form self-aligned doped source and drain regions. A high refractory top gate material is chosen for its process compatibility with printed dopants, chemical resistance, and work function. Steel foil substrates are fully encapsulated to allow for high temperature processing. The resultant materials set and process flow enables TFT electrical characteristics with NMOS and PMOS mobilitiies exceeding 120 cm²/Vs and 60 cm²/Vs, respectively. On/Off ratios are >10⁷. Reproducibility, uniformity, and reliability data in a production environmental is shown to demonstrate high volume, high throughput manufacturability. The device characteristics and scheme enable NFC (13.56MHz) capable circuits for use in flexible NFC and display-based smart labels and packaging.

Oxide semiconductors are attractive alternatives to organic materials for solution processed/printed field-effect transistors (FETs), due to their superior physical properties, such as high intrinsic mobility, optical transparency, and high thermal as well as environmental stability. High performance solution processed/printed oxide FETs have been reported in recent times. However, there are also hindrances to overcome and the foremost obstacle is that the oxides require high processing temperatures. In order to reduce the processing temperatures, several methods such as combustion synthesis with added fuel and oxidizers in the ink, sol-gel on chip, etc., have been investigated. Nevertheless, the processing temperatures were still about 200 °C, which is beyond the glass transition temperature of most of the inexpensive plastic substrates. To circumvent this issue, we have investigated photonic curing techniques (both UV-visible and UV-laser), which can cure the nanoparticles on flexible substrates. Here, we report completely room temperature processed indium oxide nanoparticulate FETs on flexible polyethylene naphthalate (PEN) substrates. UV-laser cured indium oxide FETs have shown better field-effect mobility (12 cm²V^-1s^-1) than UV-visible light cured (8 cm²V^-1s^-1) FETs. More efficient removal of the capping agent by UV-laser resulted in improved interparticle contacts, thereby in better electrical performance. The results indicate that the photonic curing can be used as an alternative to reduce the processing temperatures without compromising the electrical performance to realize flexible as well as portable electronics.

Advances in materials science and manufacturing techniques are essential to the fabrication of robust, large-area, and low-cost printed electronics, which have attracted increasing attention in a broad variety of applications. Some major challenges faced by printed electronics include the comparatively low carrier mobilities of many printed semiconductors, large channel lengths due to printing resolution limits, and low capacitance coupled with the poor compatibility of many printed gate dielectrics. In fact, many of the reported “fully printed” thin-film transistors (TFTs) actually use non-printing techniques to form some portion of the devices, such as photolithography for the source/drain contacts or, most commonly, spin-coating for the gate dielectric. In this study, we demonstrate fully printed, hysteresis-free carbon nanotube TFTs (CNT-TFTs) and integrated logic gates on flexible substrates through an aerosol jet printing technique; this includes the printing of all layers using the same printer. The active channel for the transistors was printed from the dispersion of high-purity (>99%) semiconducting CNTs while the electrodes and resistors were printed with Ag nanoparticle ink and metallic CNT ink, respectively. The printed gate dielectric ink consisting of two components: poly (vinylphenol) and poly(methyl silsesquioxane), and is tailored by adding appropriate n-Butanol solvent. The printing parameters for the developed ink and curing conditions for final devices and circuitry are studied and optimized in order to improve the quality and reliability of the CNT-TFTs. Additionally, we explore the trade-offs of bottom vs. top-gated structures. In the absence of encapsulation, the CNT-TFTs in air ambient show negligible hysteresis between forward and reverse gate sweep directions. Furthermore, the threshold voltage of the fully printed CNT-TFTs has been greatly reduced from more than >30 V to <5 V compared with those using a p++ Si/SiO₂ back gate. Considering the superb gating effect along with considerable mechanical compliance, this printed dielectric can also be used for printing flexible electronics and circuitry. It is demonstrated that the flexible devices on Kapton substrate show negligible amount of change after up to 1000 cycles of bending tests as well as aggressive folding tests. Overall, this work demonstrates an important advancement toward practical applications for CNT-TFTs with an all-printed approach for low-cost flexible electronics via a completely digital, additive, and maskless method.

Over recent years several new classes of conjugated polymer and molecular semiconductors have shown promise as materials for polymer field-effect transistors. Many of the recently discovered high mobility polymers, in particular donor-acceptor copolymers, are characterised by a puzzling lack of pronounced crystalline order. In this presentation we will present our current understanding of the transport physics of these materials, of the reasons why they exhibit such high carrier mobilities and discuss approaches for improving their device reliability and threshold voltage stability for applications that have demanding mobility, but also stability requirements, such as active-matrix addressing of liquid crystal and OLED displays.

Despite the emergency of competing materials carbon nanotubes remain at the fore-front of the promising materials for organic electronics like field-effect transistors. Due to their properties, are among the most suitable structure to support the current advancements goals in flexible electronics. However, very few are the ways to make stable single walled carbon nanotubes (SWNT) dispersions for simple processing. To further push the adoption of this kind of devices in everyday life applications, high-throughput dispersion and fabrication methods must be adopted.
In this work, we highlight how a simple process for chirality selection and dispersion of semiconducting SWNT may be used for the realization of all-printed Field Effect Transistors.
Chirality selection is operated by polymer wrapping of the s-SWNTs with poly[(9,9-dioctylfluorenyl-2,7-diyl)-alt-co-(6,6’-{2,2’-bipyridine})] in common organic solvents, with a process optimized for the [6,5] chirality selection. After solution purification, wrapped nanotubes can be dispersed in those solvents suitable for ink-jet printing.
The printing process was performed in ambient air and at room temperature, and the SWNT ink was dispense using a nozzle with an orifice diameter of 60μm over pre-patterned source and drain electrodes. In order to obtain a sufficiently well interconnected network of SWCNTs multiple subsequent layers were printed resulting in a surface coverage of ≈75%. The devices exhibit ambipolarity, with a slight prevalence of the n-type behaviour. For both electron and hole accumulations, at V_DS = ± 5V (linear regime) 10⁶ on-off ratios can be observed, with mobilities (μ_lin) around 0,3 cm² V^-1s^-1 for both carrier types. In saturation regime (V_DS = ± 60 V) mobility values (μ_sat) up to 0,8 cm² V^-1s^-1 for electrons and 0,65 cm² V^-1s^-1 for holes are reached.
The study also highlights the effects of different solvents on the carbon nanotube network formation and transistor performances with best results with those solvents that tend to form polymer pre-aggregates in the printed solution (i.e. Mesitylene, o-Xylene).

Vertical organic field effect transistor is one approach to improve the organic transistors performance to the requirements of the thin-film transistor industry while keeping the fabrication process relatively low-cost and large-area compatible. In vertical transistors the channel length is the semiconductor film thickness so it is possible to fabricate a short channel high-performance device in spite of the organic semiconductors’ relative low mobilities. In our design of vertical transistors the gate electrode is located beneath the source electrode and controls the amount of carriers injected from the source electrode to the organic semiconductor. From the semiconductor the carriers swiftly cross the very short channel length towards the drain electrode. We developed fabrication processes of n-type and p-type vertical transistors reaching on/off over 10⁵ and current densities above 10mA per cm². Complementary inverters with gain of 2 were successfully assembled using those transistors. Further analysis of the inverter output suggests that although the gain is relatively low the inverter can still be cascaded.

In this presentation we will discuss the new fabrication process we developing in-order to achieve a drain-source saturation regime. Since the current is induced by potential barrier lowering between the source electrode and the semiconductor it is crucial to expose the semiconductor-source electrode interface only to gate field and insulate the area subject to drain field. This process is achieved using simple one step photo-lithography with two different resists and lift-off process. The result is patterned electrode with holes in sizes of 2-20 µm on top a buried layer of organic semiconductor. Beside measured results a simulation results will be also presented in order to shed some light on the device behavior.

Organic semiconductor crystals grown from solutions with thin thickness, large domain size and good uniformity are highly desired for the active layers of organic field-effect transistors (OFETs). Here in this study, we utilized bar coating, a method compatible with roll-to-roll process, to deposit aligned and uniform crystals of small molecule organic semiconductors. The domain width of the deposited crystals is in millimeter scale and length is in centimeter scale. Based on the success of bar coating, we further optimized the molecules transport by using Marangoni effect from mixed solvents of different surface tensions and boiling points. Contrary to previous studies in which Marangoni effect was used to counterbalance the coffee ring effect for inkjet printing, the solvents blended in our bar coating method can enhance the mass transport towards the contact line of air, liquid and solid substrate. The growth speed was increased by 5 times and crystal thickness was reduced to a few monolayers, even only one monolayer can be deposited on the substrate under room temperature by this method. The OFETs based on solution processed 2,7-Dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) show mobility higher than 20 cm²V^-1s^-1 with very good uniformity comparable with thermally evaporated devices on a large area, but the later one only have a carrier mobility of 6.5 cm²V^-1s^-1. The experimental finding clearly demonstrates the potentials of our method in fabricating next generation flexible organic circuits or smart sensors with more complicated structures.

The conductive properties of silver allow it to be useful in the production of devices such as solar cells and thin film transistors. Highly conductive silver thin films were fabricated at room temperature using in situ reactive silver precursor inks by microreactor-assisted printing without post-processing or stabilization. . Reactive silver nanoinks, synthesized in situ from the microreactor, were directly delivered onto glass and polymeric substrates without any surface treatment to form a highly dense and uniform silver feature. The distribution of the reactive silver nanoinks can be controlled simply by adjusting the flow rate of the continuous flow system. Silver lines were fabricated using the in situ reactive precursors delivered via a micro-channel applicator. The electrical conductivity of the silver film and feature were measured to be around 38 MS/m, corresponding to about half of the conductivity of bulk silver. The functionality of the silver line was confirmed through the operation of LEDs. This study demonstrates the possibility to fabricate patterned silver features at room temperature from in situ nanoinks without the aid of any post-processing.

We fabricated an ultra-flexible voltage amplifier system using pseudo-CMOS inverters based on p-type organic transistors. The voltage amplifier circuits operate at 2.2 V supplied from lithium ion battery and signal gain over 60 dB is achieved. The combination of ultra-flexible voltage amplifier circuits and biocompatible electrodes, which is so-called active electrodes, are suitable for monitoring various small biological signals such as electromyogram, electrocardiogram, and electroencephalogram.
Organic thin-film transistors (OTFTs) are promising electrical components for biomedical applications because of their unique properties for lightweight, mechanical flexibility and cost effective processability. To realize a precise biosignal detecting, flexible and biocompatible electrodes should be tightly placed to the biological target surface. Also, it is desired to amplify the detected small signals nearby the electrodes for minimizing background noise. For this reason, ultra-flexible organic amplifier circuits combined with biocompatible electrodes are suitable for a reliable biosignal sensing.
We have developed ultra-flexible voltage amplifier system using an organic pseudo-CMOS inverter, which consists of four p-type OTFTs. The TFTs show the mobility is 1.5 cm²/Vs, the subthreshold slope is 92 mV, and the on/off ratio is 10⁸. The voltage amplifier system, which includes a pseudo-CMOS inverter, feedback resistance, and input capacitor. Small input voltage for 10 µVpp at 3 Hz sine wave is amplified to 10 mVpp, which means the voltage gain is 60 dB. The large voltage gain is quite beneficial for detecting small biological signals. Especially, since the signal amplitude for electroencephalogram (Brain wave) is in the order of µV, which is three orders smaller than the other biological signals, the voltage amplifier system is effective for precise sensing of the electroencephalogram.

We have fabricated organic physically unclonable function (PUF) on polyimide flexible substrate, and evaluated its stabilities as security device. In this work, our PUF circuit consists of organic ring oscillators (ROs), and utilizes variability of those circuit characteristics for device identification as human finger print. In this work, we have used dinaphtho thieno thiophene and thiodiazole derivertive as p- and n-type organic semiconductors, respectively. For gate insulator, we have chosen hybrid gate dielectrics consisting of self-assembled monolayer and aluminum oxide to reduce operation voltage up to 2 V. Using those materials, we have fabricated 14 ROs and divided them into two groups named imaginal chip 1 and 2. Comparing with each oscillation frequency among combination C(7,2), we can generate 21 bits ID for each chip. We have also checked reproducibility of ID. Oscillation frequency has been measured 1001 times for each RO, in 500 sec. continuously. We generate ID 1001 times from 1 chip. This result becomes 21×1001 matrix (response matrix). And then, we evaluate expected ID from response matrix by averaging ID (vector) and binarizing its elements with threshold of 0.5. Intra-chip Hamming distance (HD) which is calculated from exclusive disjunction (XOR) between generated ID and expected ID means error of ID. Therefore, we calculate average HD for 1001 IDs to estimate error rate of ID generation. For our RO-PUF, average intra-chip HD (i. e. ideally HD = 0) is less than 0.02. It shows that our organic ring oscillator PUF has high reproducibility. We have also checked DC bias stability on p-type organic transistor in RO to discuss ID reproducibility of RO-PUF. After 500-sec. stress, drain current remains at 80% of initial value under drain voltage of -2V and gate voltage of -2.5 V. On the other hand, RO is also stable and keeps its frequency at 90% of initial value even after 500-sec. driving. In the same way to intra-HD, average inter-chip HD has been calculated from XOR between response matrix of chip1 and 2. Our RO-PUF shows inter-chip HD of 0.56. This inter-chip HD indicates uniqueness of chip IDs. If IDs are ideally long enough and completely random, average inter-chip HD becomes 0.5. It can be said our organic RO-PUF has high independence between chip1 and chip2.

Flexible complementary-oxide-semiconductor (CMOS) inverters are essential building blocks for periphery integrated circuits of flexible displays or flexible circuitry for versatile applications. Up to the present time, most of the proposed flexible oxide logic circuits are based upon zinc oxide (ZnO) or indium gallium zinc oxide (IGZO) devices implementing pseudo-NMOS architecture, implying the urgent requirement for high-performance p-channel oxide-TFTs to realize circuits with low-power consumption. Tin monoxide (SnO) TFTs are recently regarded as one of the most promising candidates owing to their high field-effect hole mobility and compatibility with low-temperature fabrication processes. However, only a few flexible SnO TFTs are reported, and the knowledge of the corresponding circuitry is limited. Here we demonstrate flexible CMOS inverters and ring oscillator circuits by integrating n-channel ZnO and p-channel SnO thin-film transistors on polyimide foil substrates, and study their dynamic behaviors for the first time. Both the ZnO and SnO TFTs have an inverted-staggered bottom-gate configuration and are fabricated by the rf-sputtering technique at a maximum process temperature of 225^oC. The static voltage gain of a flexible oxide-TFT-based CMOS inverter with a geometric aspect ratio of 5 is 12 at a supplied voltage of 12 V, and an oscillating frequency of 18 kHz is obtained from a five-stage voltage-control ring oscillator at a supply voltage of 12 V. The samples are then bent to various curvatures to examine the effect of mechanical strain on their electrical characteristics from transistor to circuit levels. Under a tensile strain, a minor degradation is observed in circuits, whereas the influence of compressive strain is less prominent. This result will be beneficial to the design of flexible oxide-based CMOS circuit.

This talk will focus on the impact of TFT architecture and technology and other thin-film devices on the performance of hybrid large-area/VLSI-chip systems for human-machine interfaces. We will specifically relate thin-film/device parameters to the systems, comparing a-Si and metal oxide experimental results. As a driver, three different hybrid systems for human-machine interfaces will be examined as models: (i) a “remote” gesture sensing system based on a sensing sheet that can sense gestures from distances approaching one meter, (ii) a “voice separation” system, consisting of an array of flexible microphones, which isolates individual speakers when multiple people are speaking at once, and (iii) a flexible and conformal EEG sensing system. All three systems are designed to sense over areas much larger than those which can be covered by traditional IC’s – from 10’s of cm to multiple meters – requiring “large-area” technology and thus thin-film components. A hybrid large-area/CMOS integration approach is required for data handling and communication, and self-powering requires integration of thin film power sources.

From a circuit point of view, analog oscillator circuits and low-noise amplifiers are critical for implementation of these systems. Oscillators are used to sense capacitance and to wirelessly transmit AC data and power in a near-field fashion from one flexible sheet to another without the use of wire bonds or physical metal-metal interfaces, which may not be reliable under bending and flexing. We will show the key device/fabrication parameters to enable oscillation well over the traditional cutoff frequency (f_t) limit, and compare a-Si and metal oxide circuits on both glass and ultra-thin plastic substrates, with oscillation frequencies over 35 MHz. The high quality of passive components compared to those available in VLSI is a benefit to large-area systems. High-frequency thin-film diodes with 100 MHz performance to convert transmitted AC power and data back to DC will also be described. Low-noise analog amplifiers for sensor interfacing are conventionally limited by 1/f noise from interface and midgap states, which are typically much higher in thin-film than in crystalline semiconductor technologies, although the relative large area of thin-film devices somewhat mitigates this effect. Signals below 1 kHz, such as EEG signals, are especially prone to such noise, and TFT “chopper-stabilized” amplifiers which shift the signal to higher frequencies (and thus lower noise) are presented. Finally, the inherent trade-off between operating at these higher frequencies and the power efficiency of the TFTs will be analyzed and compared for different technologies.

Conventional complementary logic circuits have been implemented, based on 2D planar structures with p- and n-type transistors fabricated and connected on the same floor in a device. Three-dimensional (3D) complementary integrated circuits, in which the two-types of transistors are vertically stacked on different floors, have the potential to significantly enhance transistor density, performance and functionality, compared to the conventional 2D circuits. Organic transistors are ideally suited for 3D vertical integration because of their layer-by-layer solution processability at low temperature. In this presentation, we report for the first time flexible and inkjet-printed 3D complementary organic field-effect transistors and logic circuits. We fabricate a p-type organic field-effect transistor on top of an n-type organic field-effect transistor with a shared gate joining the two transistors. Several different combinations of p- and n-type organic semiconductor materials including commercially available Tips-pentacene and (P(NDI2OD-T2), diF-TES-ADT and (P(NDI2OD-T2), as well as new materials such as DPP-SVS and PNDI-TVT were applied to verify the 3D transistor-on-transistor structure. The best device performance was obtained from the DPP-SVS and PNDI-TVT combination when processed on a PEN substrate at temperature as low as 110°C. (field-effect mobility values of 0.42 cm² V^-1 s^-1 and 0.20 cm² V^-1 s^-1 respectively, maximum static voltage gain of ~18 V/V and high noise immunity up to 60 % of VDD/2). In order to produce high-performance 3D inverters, the driving strength between two transistors with large mobility difference were evenly balanced by adjusting the dielectric capacitance of each transistor. This new matching scheme was achieved owing to the heterogeneous integration-ability of the 3D structure where different dielectric materials can be deposited with optimized film thickness. Based on the common-gate transistor-on-transistor structure, a 100%-yield complementary inverter array, universal logic NAND gates and a computing device such as full-adders were fabricated by drop-on-demand inkjet-printing method. Our study demonstrates a general strategy for the 3D integration of printed conducting and semiconducting layers to continuously increase the transistor density, performance, functionality.

A bias instability of organic field-effect transistors (OFETs) is one of the most critical obstacles to their practical use. Prolonged operation under an applied bias causes a drop in the channel current and a detrimental shift in the threshold voltage of OFETs, which prevents the normal operation of an electronic circuit. The bias-stress-driven electrical instabilities are attributed to charge carrier trapping inside the device. In this talk I will discuss the challenges and our progresses in understanding of charge trapping phenomenon in OFETs. First, I will introduce the charge trapping behavior in polymer gate dielectrics, and discuss the methods to improve it. Next, I will present new approaches for analyzing charge traps at the semiconductor-dielectric interface. The latter part includes our studies using photoexcited charge collection spectroscopy, a novel experimental method to probe the traps. Our detailed and systematical analyses for the bias instability of OFETs would contribute to unveiling the charge trapping mechanisms, and to realizing the robust and practical OFETs.

Organic field-effect transistors (OFETs) are promising device because of their favorable features such as light-weight, flexibility, and low cost fabrication. Since OFETs were invented, much efforts have been devoted to improve its performance through an application of feasible materials to organic and insulator layers, and an insertion of buffer layer at organic/gate dielectric interface. Consequently, the mobility of OFETs has increased drastically, however, a bias induced instability still has not been clarified. To resolve this issue and realize the practical use, a deep understanding of its mechanism is needed.
Because the instability is strongly related to the trap of charge carriers, it is important to evaluate the carrier behaviors in OFETs. Capacitance-voltage (CV) measurements, such as impedance spectroscopy and displacement current measurement, are powerful tools to observe carrier injection, accumulation and trap processes. Conventional CV techniques have been performed with connecting the source and drain electrodes to the ground. Therefore, it was impossible to examine the behaviors of accumulated charges during transistor operation because of lacking the drain voltage. Recently, we have proposed a three-terminal CV (TT-CV) and applied this method for the evaluation of the channel formation in OFETs*. In addition to the carrier injection process affected by the drain voltage, an additional structure in the CV curves clearly appeared due to the channel formation from the saturation to the linear region which has not been directly observed in conventional setup.
In this study, we apply TT-CV to top-contact type pentacene-based OFETs (Pn-FETs) with or without tetratetracontance (C₄₄H₉₀, TTC) buffer layer on SiO₂ in order to evaluate the degradation process. For continuous bias stress, gate and drain voltages were set to be -40 V and -18 V, respectively. A 72% reduction of the drain current at the operation time of 6×10⁵ s is observed in Pn-FET without TTC layer. TT-CV reveals that the traps are formed beneath the source and drain electrodes and channel region. On the other hands, only 24% drop from the initial value appears in Pn-FET with TTC layer, and no trap formation immediately under the drain electrode is observed in TT-CV. These results clearly indicate that (i) the traps are initially formed beneath the source electrode and grow to the drain electrode side by the bias stress, and (ii) TTC layer drastically restricts the trap formation at organic/insulator interface. The proposed method can be used as a tool for clarifying the operating mechanism of OFETs, including ambipolar and light-emitting transistors.
This research was supported by the Funding Program for World leading Innovative R&D on Science and Technology (FIRST Program), KAKENHI (Nos. 25288114, 16H04222), and the Global-COE project of Chiba University (Advanced School for Organic Electronics).
*Y. Tanaka et al., Org. Electron. 14, 2491 (2013).

Field effect transistors (FETs) are essential components in a wide range of electronic devices such as active-matrix displays, logic circuits or sensors. Compared with the inorganic counterparts, the flexibility in organic semiconductors allows many novel applications such as smart sensors for wearable electronics or biomedical devices. When utilizing the organic FETs (OFETs) as sensors for medical purposes, it is important to make sure they are compatible with the standard sterilization process and able to withstand various extreme environment such as hot steam, acidic or alkaline environment and aqueous solution without degrading their electrical properties. Here we reported flexible low-voltage transistors based on newly developed thermally stable organic semiconductor 2,10-diphenylbis[1]benzothieno[2,3-d;2',3'-d']naphtho[2,3-b;6,7-b']dithiophene (DPh-BBTNDT) with dual-layer encapsulation. A thin hybrid gate dielectric based on anodized Al₂O₃ and Octadecylphosphonic acid (ODPA) self-assembled monolayer (SAM) was utilized to ensure operating voltage lower than 3V. The OFETs showed a high mobility up to 2.21 cm²V^-1s^-1 and on/off ratio of 1x10⁶ . With the dual encapsulation structure, our device is completely embedded inside the protection layer and shows excellent stability under deionized water, 1X PBS, 10X PBS as well as buffer solution with pH values ranging from 1 to 13. The variation of the carrier mobility is only within 5% and the on-off ratio was almost identical. The device can also go through sterilization process including 100 hot steam for 30 minutes and 100boiling water for 30 minutes. This feature is extremely important for integrating this device with surgical tools which needs go through sterilization process before use. Based on the ultra stable OFET device, we take a step further to use it for C-reactive protein (CRP) detection (an indicator of inflammation). Such device has extremely high application potential on real-time CRP sensing during surgery.

The fabrication of thin-film passivation layers that prevent the penetration of oxygen and water vapor remains a major challenge in various fields of thin-film electronics. Reactive gases (e.g., O₂) and water molecules can cause electrical instability in thin-film electronic devices and reduce the lifespans of low work function metal electrodes. In fact, the fabrication of suitable barrier films with solution-based, low-cost, and low-temperature routes is the primary hurdle to the development of organic and/or flexible electronic and optoelectronic devices.
In this study, we successfully fabricated sol-gel-derived, crack-free, and condensed TiO_x thin films on polymeric substrates with a simple two-step heat treatment at low temperatures with improved barrier properties. To assess the barrier properties of the TiO_x thin films, Ca corrosion tests were conducted and their water vapor transmission rates (WVTRs) were measured. We found that the two-step heat treatment (at 45 °C for 90 min and 110 °C for 60 min) produces a close-packed TiO_x structure that substantially reduces the WVTRs of the coated polymeric substrates. The WVTRs of 86 nm thick TiO_x thin films on polyethylene naphthalate (PEN) substrates at a relative humidity (RH) of 90% were found to be 0.133 g m^-2 day^-1 at 38 °C and 0.0387 g m^-2 day^-1 at 25 °C. In addition, the WVTR value of the TiO_x thin films on PEN substrates are stable with respect to bending: it was found to increase by only ~13% after 100 repetitions of bending with a 20 mm radius. Finally, we have tried to employ the sol-gel-derived TiO_x thin films as the passivation layers of organic field-effect transistors.

Solution-processable dielectric materials have received great interest because of increasing demand for large-area and low-cost electronics that are generated without the use of high-vacuum equipment. Some sol-gel metal oxide dielectrics with high dielectric constants (k), which are synthesized from organometallic precursors, may meet the desired requirements for gate dielectrics in organic devices such as organic field-effect transistors (OFETs) and organic complementary inverters, since the high-k dielectrics could drive currents with low operating voltages. For commercialization of such devices, the patterning of each film component via a facile route has also been an important issue.
In this study, we introduce a photo-patternable precursor, zirconium acrylate (ZrA), to fabricate photo-patterned high-k zirconium oxide (ZrO_x) dielectric layers with UV light. Solution-processed ZrA films were effectively micropatterned with UV exposure and developing, and transitioned to ZrO_x through a sol-gel reaction during deep-UV annealing. The UV-assisted and ~10 nm-thick ZrO_x dielectric films exhibited a high capacitance (917.13 nF/cm² at 1 KHz) and low leakage current density (10^-7 A/cm² at 1.94 MV/cm). Those films could be utilized as gate dielectric layers of OFETs after surface modification with ultrathin cyclic olefin copolymer layers. Finally, we successfully fabricated organic complementary inverters exhibiting hysteresis-free operation and high voltage gains of over 42 at low voltages of -3 V.

Stretchable transistor is a key element for next generation of stretchable/wearable electronics. Especially, semiconductor has become a crucial material among all components to operate the device under high strain. In terms of mechanical stretchability, although the organic semiconductors have many advantages compared to inorganic materials, the organic semiconductors such as small molecule and semiconducting polymer that are commonly used for organic transistor are still venerable to high strain. Herein, we present a new concept of molecular design to confer intrinsically high stretchability on semiconducting polymer by introducing chemical moieties in the conjugated polymer backbone to promote dynamic non-covalent crosslinking of the conjugated polymer chains. The newly synthesized semiconducting polymer showed high field-effect mobility (> 1.0 cm²/Vs) at hgih strain (100 %) and maintained the performance even after 100 stretching cycles.

A key component hindering the production of high-performance and inexpensive printed transistors on flexible substrates is the inability to produce small channel lengths by inkjet and aerosol jet techniques. Here, we demonstrate the fabrication of micron-scale electrodes from a solution-processable graphene ink using soft nanoimprint lithography, allowing for an inexpensive and fast method to produce uniform electrodes for organic field-effect transistors. Residual-free electrodes were printed with channel lengths of 10 um, 25 um, and 50 um onto silicon dioxide/silicon wafer substrates with a variety of controlled height profiles. We tested the device capability of the graphene electrodes system using single-crystal rubrene.

Intensive research has been actively performed to fabricate organic thin-film transistors (OFETs) for a low-cost large area application. Our research group recently introduced the pen-printing technique for the field of organic transistors, which uses a capillary action. The versatility of the technique can be applied to solution processable organic materials to form the various patterns including dot and line shapes. However, the pen printing technique has a drawback to apply the industrial fields, which is the large-patterned scale around 100μm.
The optimizations for efficient and practical pen printing technique is performed by controlling surface energy and capillary-nib structure. In our study, the surface energies were controlled from 20 to 50 mJ/m², the angle of nib-end structures were controlled from 20 to 40 degree. As the results, the printed patterns decreased to 30 μm in a diameter, comparing the 100 μm scale in the previous studies. The results are expected to contribute to the commercialization of low cost large-area organic electronic devices manufactured from a variety of solution processable organic materials.

In this study, we fabricated a high-performance solution-processed In–Ga–Zn–O (IGZO) thin-film transistor (TFT) using rapid flash lamp annealing (FLA). 0.1M indium nitrate hydrate, Zinc nitrate hexahydrate, and gallium nitrate hydrate were dissolved in 2-methoxyethanol with a molar ratio of 7:1.5:1.5. The solution was stirred at 75 °C for 2 hours and spin-coated onto the 20 x 20 mm² sized Si wafer with thermally grown SiO₂ (100 nm) at 4000 rpm. The films were then irradiated by xenon flash lamp for as short as 12 s. After that, 50-nm thick Al was thermally evaporated on the film to form source/drain electrodes. Finally, The TFTs were post-annealed at 100 °C for 30 min on a hotplate to stabilize the TFT characteristics. The TFT with FLA time of only 12 s shows high performance with mobility of 17.7 cm²/Vs, threshold voltage of 5.41 V, on/off ratio of ~10⁷, and subthreshold swing of 0.39 V/decade.

Solution-processed high-dieletric-constant metal oxide materials are attracting much attention since it can replace conventional dielectric such as SiO₂ for low leakage current and low-voltage operation. To convert solution precursor to metal oxide film, various annealing method have been suggested such as excimer laser and deep ultraviolet. However, deep ultraviolet method requires N₂ or vacuum condition and the excimer laser method is not appropriate for large-scale production. Forthemore, both annealing method need to long annealing time. In this study, we report the xenon flash lamp annealing of solution-processed aluminium oxide gate dieletric for rapid activation under ambient atmosphere. The aluminium precursor films were exposed to the high energy light-pulse, and completely converted to dielectric films within 30 seconds.
0.6 M aluminium nitrate nonahydrate (≥98%, Sigma-Aldrich) was prepared in 2-methoxy ethanol and stirred it at 75 °C for 6 hours. The solution was spin-coated on p-doped silicon and pre-annealed on a hotplate for 10 minutes at 100 °C. After that, flash light were exposed to the aluminum oxide film for a range of 5 to 30 seconds. As depicted Fig. 1, the aluminum oxide gate dieletric exhibits dielectric constants of aluminum oxide layer are calculated to be approximately 6-7 and leakage current density of ~10^-9 A cm^-2 at 2 MV cm^-1.

Transparent oxide semiconductors have attracted significant attention for various electronic devices due to their excellent electrical and optical properties. These kind of semiconductors provide opportunity to apply transparent and flexible electronic devices. Particularly, high field effect mobility is required for the application of oxide TFTs as backplanes of transparent and flexible display. The constituent elements of most well-known transparent conducting oxides are indium, zinc and tin. Among them, indium was known for mobility enhancer. Indium provides plenty of oxygen vacancies and it causes large number of electrons in the films.
For the deposition of oxide semiconductors such as InO_x, atomic layer deposition (ALD) is a promising deposition method due to its growth uniformity and high quality films compare to other conventional deposition methods such as RF magnetron sputtering and chemical vapor deposition. On the other hand, depending on the precursor of indium and the reactant for oxygen, the film characteristics would be varied. In this study, [3-(dimethylamino) propyl] dimethyl indium (DADI) was used as a precursor of indium, which was liquid at room temperature so that it has relatively high vapor pressure compared with other precursors and it is expected to show high growth rate and low resistivity. Ozone and oxygen plasma were utilized for the reactants. Since they have different reactivities with the precursor, the growth and material characteristics of the obtained InOx films would be different.
The InO_x thin films were deposited by an ALD using oxygen plasma and ozone reactant, respectively. All the ALD processes were carried out at 200 and the relatively high growth rate of 0.7 Å/cycle was obtained for PEALD. The electrical properties were investigated by fabricating TFTs and other structural and chemical analyses. With varying the thickness (2 nm ~ 10 nm) of the InO_x active layer, the optimized thickness of the layer was obtained. We could obtain excellent electrical properties for the device with the thickness of 4 nm, such as effective mobility =61.4 cm^2/V S, Vth =-7.5 V, and S.S = 0.33 V/decade after the post annealing at 250.

Acknowledgement
This work was partly supported by Institute for Information & communications Technology Promotion (IITP) grant funded by the Korea government (MSIP) (B0101-16-0133, The core technology development of light and space adaptable energy-saving I/O platform for future advertising service) and the R&D Convergence Program of MSIP (Ministry of Science, ICT and Future Planning) and ISTK (Korea Research Council for Industrial Science and Technology) of Republic of Korea (B551179-13-02-02).

Polyvinyl alcohol polymer has been a well-known and extensively researched organic material suitable for a wide variety of applications, however, its use as insulating dielectric has been very limited. Albeit, it possesses a high dielectric constant value, its inherent highly leaky behavior has been a major obstacle forbidding such applications. Crosslinking of polymer chains to create a compact dielectric film has been extensively used to reduce leakage issue of the dielectric films. The use of glyoxal in crosslinking the PVA chains has been very limitedly studied though it can be a potential alternative to the other cross-linkers of PVA due to its low cost and non-toxicity. We have introduced glyoxal crosslinked PVA as gate insulator of pentacene based field effect transistors. In this work we have studied the role of a thin PMMA buffer layer in improving the structural ordering and crystallinity of the organic semiconductor and also analysed the efficacy of glyoxal cross-linked PVA as a gate insulating layer in effectively reducing the leakage current and hence attaining superior device performance and device stability compared to pristine PVA dielectric devices. The enhanced insulating properties and reduced surface roughness of cross-linked PVA are emulated in the better OFET performance parameters resulting in a saturation hole mobility of 0.21 cm²/V s, saturation drain current of 20 µA, and an on/off ratio of 2.2x10³ in contrast to 0.06 cm²/V s, 4 µA, and 1.6x10³ obtained for uncrosslinked PVA devices respectively. Our study can thus catalyze the limited use of glyoxal as a cross-linking agent of PVA in electronic application.

A molecular dynamics (MD) and density-functional-theory (DFT) study of amorphous Zn-Sn-O (ZTO) and In-Ga-Zn-O (IGZO) with focus on the use as transparent conducting oxides (TCO) materials is presented [1-4]. The amorphous structures generated by MD are in the following relaxed using the local-density-approximation (LDA) of DFT. The main focus is on defect levels in the electronic band structure of ZTO and IGZO. These subgap states are analysed in terms of densities of states, which are calculated by means of the LDA and with a self-interaction-correction (SIC).
We connect the electronic subgap states, which were observed recently [5-7] with structural features of the amorphous samples. According to our analysis the valence band tail, caused by the disordered O 2p orbitals, is superimposed by deep defect states that can be assigned to undercoordinated O atoms which is not in line with the assignment of those states to oxygen vacancies by Kamiya et al. [8]. Our alternative is further supported by the fact that doping with H atoms suppresses these states by creating O--H bonds, which improves the transparency and is consistent with experimental findings [5].
The deep levels below the conduction band edge arise mainly from undercoordinated pairs of metal atoms. The addition of oxygen can be a possible route to reduce such defect levels.

[1] W. Körner, P. Gumbsch and C. Elsässer, Phys. Rev. B 86, 165210 (2012).
[2] W. Körner, D. F. Urban and C. Elsässer, J. Appl. Phys. 114, 163704 (2013).
[3] W. Körner and C. Elsässer, Thin Sol. Films 555, 81 (2014).
[4] W. Körner, D. F. Urban, and C. Elsässer, Phys. Stat. Sol. A 212, 1476-1481 (2015).
[5] K. Nomura et al., J. Appl. Phys. 109, 073726 (2011).
[6] P. V. Erslev, et al. Appl. Phys. Lett., 95, 192115 (2009).
[7] S. Sallis, K. T. et al., Appl. Phys. Lett. 104, 232108 (2014).
[8] T. Kamiya, et al., Phys. Stat. Sol. C 5, 3098 (2008).

Halide ligands passivate the surface of collodial quantum dots, enhancing the stability and performance of quantum dot electronic and optoelectronic devices. Recently, films of lead sulfide (PbS) quantum dots prepared with tetrabutylammonium iodide (TBAI) ligands have been used to fabricate solar cells having an efficiency of ca 10 percent and field effect transistors (FET) whose hole mobility approached 0.22 cm² V^-1s^-1 [1,2]. However, even for these nominally air-stable halide-passivated films, transport measurements had to be made in an inert environment to prevent degradation. We report a room temperature encapsulation protocol using a thin (100 nm) layer of parylene C. This protocol enables transport measurement of quantum-dot FETs in ambient atmosphere for several days.
Combining charge-transport studies with scanning frequency-modulated Kelvin probe force microscopy measurements is a powerful approach for revealing the microscopic details of charge transport in quantum dot thin films [3]. These measurements give useful information about free carrier generation, the density of states, and trapping. Using a custom-built vacuum microscope, we perform an array of FM-KPFM measurements to elucidate charge injection, transport, and trapping dynamics in PbS TBAI thin film transistors.
[1] Lan, X.; et al.; Sargent, E. H.(2016), Passivation Using Molecular Halides Increases Quantum Dot Solar Cell Performance. Adv. Mater. doi:10.1002/adma.201503657

[2] Zhao, M.; et al.; Tang, Z. (2016), High Hole Mobility in Long-Range Ordered 2D Lead Sulfide Nanocrystal Monolayer Films. Adv. Funct. Mater. doi:10.1002/adfm.201601735

[3] Zhang, Y.; et al.; Salmeron, M. (2015) Dynamic Charge Carrier Trapping in Quantum Dot Field Effect Transistors Nano Letters doi: 10.1021/acs.nanolett.5b01429

In₂O₃-based materials, including ITO, are promising to be used as highly transparent and conductive films of optoelectronic devices. These are typically used in amorphous or polycrystalline structure. In₂O₃ is known to have two types of bixbite cubic (cubic-In₂O₃) and corundum (a-In₂O₃) structures. The control of crystal structures makes it possible to create the fabrication of new device structures such as metal-oxide-semiconductor field-effect transistors of a-In₂O₃ [1].
In this study, In₂O₃ films were grown on various substrates, such as (0001)a-Al₂O₃, (0001)GaN/a-Al₂O₃ and (111)YSZ, with the aim of controlling crystal structures by mist CVD. Mist CVD is a solution-based growth technique using a simple system configuration with low cost and low environmental pollution and can be performed even under atmospheric pressure.[2] This is a suitable technique for growing metal oxide films.
Indium acetylacetonates were used as source materials for these growths. The acetylacetonates were solved in deionized water with a small amount of hydrochloric acid. The solution was atomized using an ultrasonic transducer at 2.4 MHz and the formed aerosols were transferred to a quartz furnace using a carrier gas. In₂O₃ films were then grown on various substrates set in the furnace. The crystal and electrical characteristics of these In₂O₃ films were also investigated.
The polycrystals including (111)-oriented and (100)-oriented cubic-In₂O₃ as well as (0001)-oriented a-In₂O₃ were grown in the sample on a-Al₂O₃. In the samples grown on GaN/a-Al₂O₃ and YSZ, the (100)-oriented cubic-In₂O₃ and (0001)-oriented a-In₂O₃ phases were suppressed. Single crystalline (111)-oriented cubic-In₂O₃ films without twin structure were grown on YSZ, although twin structure was confirmed in the sample grown on GaN/a-Al₂O₃.
The typical carrier concentration and electron mobility of these films were 5-9 ×10¹⁸ /cm³ and 70-90 cm²/Vs, respectively. Correlation between crystal quality and electrical property will be discussed.

The authors would like thank Prof. Fujita and Dr. Kaneko of Kyoto University and Prof. Sato and Dr. Nagai of Kogakuin University for fruitful discussion and technical support. This work was partly supported by JSPS KAKENHI Grant Numbers #25706020, #25420341 and #25390071.

[1] K. Kaneko et al., Appl. Phys. Express 8, 095503 (2015).
[2] T. Kawaharamura et al., J. Soc. Mater. Sci. Jpn. 55 (2006) 153 [in Japanese].

There is a great interest in various branches of advanced materials industry for development of novel methods and improvement of existing ones to deposit conformal ultrathin metallic films. Microelectromechanical systems, thin film transistors, fuel cells, and solar heaters are just a few prominent examples, where ultrathin metal films can realize their potentials. In most of these applications, achieving the capacity to deposit a conformal thin film on a three-dimensional structure is the key factor. Atomic layer deposition is known for its potential for growth of conformal thin films with exceptional degree of control over thickness. This study evaluates and compares two methods for preparation of conformal nickel films. The first method involves direct atomic layer deposition of metallic films through using an organometallic precursor and hydrogen plasma. The results of this method are then compared with those of an indirect method; in which conformal nickel oxide films were deposited using the same organometallic precursor and oxygen plasma, followed by reduction in the furnace, in the presence of hydrogen gas. A full suite of characterization methods were conducted, in order to assess and compare the chemical composition, growth rate, surface roughness, mass density, crystallinity, and optical properties of the films. In order to establish the conformality of the films, deposition was also carried out on aluminum oxide foams, which were then investigated through scanning electron microscopy, whose the initial results will be presented.

Vanadium oxides (VO_X) takes various chemical states such as V₂O₅, VO₂ and V₂O₃; some of VO_X are strongly correlated materials, which reveals distinctive metal-insulator transition along the structural conversion. For transistors comprising a VO_X thin film, slight electric field controls the electronic conduction of the whole material more than a channel even at room temperature, that enables nonvolatile effect and enormous switching in a thin film transistor^[1,2]. The structural and electronic property of VO_X materials could be modified by pressure application as well as varying the temperature of crystalline materials^[3]. On the other hand, the effect of pressure application during the crystal growth of VO_X thin films on their structure and properties has not been understood well and there are few reports. In this study, we present phase controllable epitaxy and topotaxy of VO_X semiconductor thin films via solid-phase crystallization by thermal treatment under uniaxial compression, which findings would contribute to oxide transistor technology. The effect of pressure on structural and electronic controllability were also investigated. The 70 nm-thick precursor amorphous VO_X thin film was prepared on α-Al₂O₃ (0001) substrates by pulsed laser deposition at room temperature using KrF excimer laser (λ=248 nm, d=20 ns, 2 J/cm²) and a V₂O₅ ceramic target. The amorphous thin films were subsequently annealed under uniaxial compression of 1, 10 and 30 MPa and also without load, at 500°C for an hour in Ar purged vacuum. As a result, phase selective epitaxy of VO_{2 M} and V₂O₃ was obtained, depending on the applied pressure. The metal-insulator transition was certainly observed. The topotaxy of the VO_X thin films, the reversibility of crystal phases were proved by supplementary heat treatment under compression; the metamorphosis suggests formation of the stable phases at certain pressure and temperature condition, rather than one-way reduction reaction. In addition, similar topotaxy was also observed for the PLD grown uniaxial oriented crystal V₂O₅ thin film; in the case metastable VO2 (B) precipitated as well as non-stoichiometric V₆O₁₃ comprising both V⁵⁺ and V⁴⁺.
[1] M. Nakano et al., Nature 489 (2012) 459.
[2] S. Lupi et al., Nature Comm. 1 (2010) 105.
[3] Y. Muraoka et al., Appl. Phys. Lett. 80 (2002) 583.

Metal-oxide-semiconductor (MOS) devices are being extensively used in the electronic industry. The dielectric breakdown has been enhanced exponential due to the increase of gate tunneling current caused by the aggressive downscaling of devices. Studies reported that oxygen vacancies and hydrogen impurities could be responsible for charge trapping and assist gate tunneling current. However, a few studies focused on the electron potential barrier height, which is the primary parameter that controls the tunneling current. In this study, we investigate the effects of oxygen vacancies and hydrogen impurities on the electron potential barrier height at Al/SiO₂ interfaces. Band alignments study suggest that points defects at the interface could decrease the potential barrier height and and increase the charge transfer. Defect states analysis indicate that point defects at the interface create shallow and unoccupied defect states in SiO₂ band gap, which could be responsible for electron trapping. Gate current simulations reveal that gate current depends more strongly on barrier height than gate bias. In addition, we observe that defect-assisted conduction mechanism can be another critical factor that magnifies the gate current, so that increases the dielectric breakdown probability.

Group-IV-semiconductors, i.e., Si, Ge, SiGe, and GeSn, have higher carrier mobility than organic and oxide materials, which shows significant advantage for the application of high speed TFTs. In particular, GeSn with substitutional Sn concentration above 8% is expected to have direct-band structure, resulting in much higher carrier mobility than Si, Ge, and SiGe. However, thermal equilibrium solubility of Sn in Ge is very low (~2%). To solve this problem, in this study, we have developed a non-thermal equilibrium growth method, where amorphous-GeSn (a-GeSn) on insulator is crystallized by pulsed laser annealing (PLA).
In the experiment, a-Ge_1-xSn_x (0<x<0.2, 100 nm thick) films were deposited on quartz substrates. They were irradiated with KrF eximer laser (wavelength: 248 nm, fluence per pulse: 10-220 mJ/cm², pulse-number: 1-200 shots).
Firstly, the effects of laser flence on crystallization are investigated keeping a constant pulse-number (100 shots). After PLA (fluence per pulse: 10-220 mJ/cm²), Raman peaks due to Ge-Ge bonding were observed for all samples. In the low fluence region (10-80 mJ/cm²), FWHM of Raman peaks decreased with increasing fluence, indicating nucleation and nuclei growth in a-GeSn. Interestingly, solid phase crystallization (SPC) of GeSn was achieved by additional thermal annealing (180 ^oC, 1 h), where SPC did not occur for samples without PLA. In the middle fluence region (80-180 mJ/cm²), FWHM reached saturation, showing completion of crystallization. However, for high fluence above 180 mJ/cm², GeSn layers were ablated.
By choosing the typical fluence (140 mJ/cm²) in the middle region, we examined effects of pulse-number on crystallization. Sharp Raman peaks due to Ge-Ge bonding were observed for all pulse-numbers (1-200 shots). This indicates the formation of high quality GeSn even by 1 shot irradiation, which has been confirmed by transmission electron microscopy observation. Substitutional Sn concentrations in grown layers were evaluated from Raman peak positions. In the samples with initial Sn concentration of 5%, all Sn occupied substitutional sites for all pulse-numbers. On the other hand, for initial Sn concentration exceeding 10%, substitutional Sn concentration depended on pulse-number, where substitutional Sn concentration increased with decreasing pulse-number. As a result, GeSn crystals with high substitutional Sn concentration (~13%) are realized by 1 shot irradiation for samples with initial Sn concentration of 20%.
To investigate the physics behind PLA induced crystallization, cooling rate after PLA was estimated by in-situ optical reflectivity measurements. Results revealed that cooling rate increased with decreasing pulse-number. As a result, substitutional Sn atoms are found to be increased with increasing cooling rate. These results indicate pulse-number dependent non-thermal equilibrium growth by PLA is very effective to achieve GeSn with high substitutional Sn concentration (~13%).

A technique for low-temperature (≤250°C) formation of high-quality crystalline Ge films on insulator is desired to realize high performance thin film transistors (TFT) on flexible plastic substrates (softening temperature: ~300^oC). To improve quality of Ge crystals, Sn-doping (<4%) is very effective, because it enables passivation of point defects in Ge. This triggered the recent research of solid-phase crystallization of Sn-doped Ge (Sn concentration <4%) on insulating substrates. However, the growth temperature (425°C) reported to date is higher than the softening temperatures of plastic substrates. To decrease the growth temperature of Sn-doped Ge, in the present study, we investigate effects of Au catalysis on crystallization of a-GeSn.
In the experiment, a-Ge_1-xSn_x layers (x: 0−0.2, thickness: 100 nm) were deposited on quartz substrates, and Au island patterns (thickness: 100 nm, diameter: 500 μm) were formed on the a-GeSn layers. The samples were annealed at 150−250^oC to induce lateral crystallization.
Nomarski optical microscopy observations together with micro-probe Raman measurements revealed that crystallized regions (length: 5−20 μm) were formed around Au patterns for samples (x: 0−0.05) after annealing (250^oC, 10 min). On the other hand, for samples (x: 0.1−0.2), no crystallization occurred around Au patterns after the annealing. These results indicate that Au-catalysis-induced lateral crystallization is generated for samples (x: 0−0.05), while it does not occur for samples (x: 0.1−0.2).
Analysis of the lateral growth lengths was performed as a function of annealing time and temperature. For samples (x: 0−0.05), lateral growth lengths steeply increased for annealing time shorter than 10 min, while the growth slowed down after 10 min. These phenomena are attributed to two-stage Au diffusion, i.e., fast Au diffusion in a-GeSn layers (annealing time < 10 min), which generates crystallization of a-GeSn layers, and slow Au diffusion through the crystallized GeSn (> 10min), whose details will be discussed at the presentation.
Annealing temperature dependence of the substitutional Sn concentrations in grown layers was evaluated by the Raman peak positions. Results for samples (x: 0.05) revealed that substitutional Sn concentrations increased from 0.5% to 2.0% with increasing temperature from 150 to 250°C. These values well agree with the temperature dependent solid-solubility of Sn in Ge. This demonstrates good controllability of the substitutional Sn concentration by the annealing temperature, which is useful to passivate point defects in Ge. This technique will facilitate realization of advanced TFT for next generation flexible electronics.

Tin oxide (SnO_x) thin-film transistors (TFTs) are potential candidates to realize low-temperature complementary oxide-semiconductor-based (CMOS) inverters and circuits. It has been known that the SnO_x TFT behavior can be modulated by the stoichiometry of the tin oxide active layer. By utilizing this feature, challenges in low-temperature CMOS process involving two different material systems for n- and p-channels can be circumvented. P-channel SnO_x TFTs, mainly SnO TFTs, processed at a temperature compatible with flexible polymeric substrates have been demonstrated. However, the majority of high-performance n-channel SnO_x TFTs, mainly SnO₂ TFTs, reported still requires post-deposition anneal at a temperature of >300^oC, which is not suitable for flexible polymeric substrates and adds complexity to the CMOS processes. It has been reported that low-temperature n-channel SnO₂ TFTs can be obtained by adding an aluminum oxide underlying layer or a copper oxide capping layer to a SnO active channel. In this study, we propose an alternative approach to achieve high-performance n-channel SnO_x TFTs via a low-temperature process by introducing a zirconium dioxide (ZrO₂) capping layer. The SnO_x TFTs have an inverted-staggered bottom-gate configuration. Without the capping layer, the SnO_x TFT exhibits p-channel behavior and has a field-effect mobility of 0.09 cm²V^-1s^-1, threshold voltage of 3.1 V, subthreshold swing of 2.8 V/dec, and on/off current ratio of ~10⁴. After depositing a 100 nm ZrO₂ capping layer by e-beam-evaporation, followed by low-temperature annealing at 225^oC, the SnO_x TFT becomes n-type. The n-channel SnO_x TFT possesses a field-effect mobility of 0.5 cm²V^-1s^-1, threshold voltage of 0.9 V, subthreshold swing of 0.9 V/dec, and an on/off current ratio of ~2×10⁵, which is comparable to those processed with high annealing temperatures. This low-temperature approach shows the feasibility for producing high-performance n-channel SnO_x TFTs on flexible polymeric substrates. Further results will be reported in the symposium.

Tin monoxide (SnO) has been regarded as one of the most promising active channel materials for p-channel oxide thin-film transistors (TFTs). SnO TFTs possess attractive features of high hole field-effect mobility, optical transparency, good electrical stability, and low-temperature processability. Most of the high-performance SnO TFTs reported today were fabricated on rigid substrates, such as glass or Si wafers. Only a few were demonstrated on plastic foil substrates, but their performance under the influence of mechanical strain not been explored yet. In this work, we first demonstrated flexible SnO TFTs on SiN_x passivated polyimide foil substrates and then investigated their electrical performance and bias-stress stability under the influence of mechanical tensile strain. The TFTs were implemented in an inverted-staggered bottom-gate architectures. The SnO channel layer was deposited by rf-sputtering at room temperature, followed by a thermal anneal at 225°C for 30 min in air ambient. The as-fabricated on–polyimide SnO TFT exhibits a field-effect mobility of 0.40 cm²V^-1s^-1, threshold voltage of 0.96 V, subthreshold swing of 2.11 V/dec, and on/off current ratio of 10⁴. The electrical characteristics were measured when the devices were bent to various mechanical tensile strain levels with a custom-built apparatus simultaneously. A perceivable 22.5% decrease in linear mobility was observed when the device was under a tensile strain of 0.31%. To study the electrical gate-bias stress stability of SnO TFTs, the threshold voltage shift as a function of gate-bias stress duration was evaluated. Under a stressing condition of 10 V for 10000 s, threshold shifts of 0.72 V and 0.99 V were observed when the device was kept flat and subject to a tensile strain of 0.31%, respectively. The result shows the impact of tensile strain on the on-foil SnO TFTs needs to be considered for practical circuit implementation.

Organic thin film transistors are potentially strong for next generation electronic devices due to their several advantages like low cost fabrication, light weight, mechanical flexibility, and large area coverage. Charge transport in organic semiconductors with new device structure has been intensively and widely studied in recent years. We report p-type charge transport in pentacene organic thin film transistors (OTFTs) by using graphene oxide as the gate dielectric material. The devices were fabricated on ITO-coated glass substrate with two different metal contacts, viz. silver and silver palladium, as source and drain contact. Fabricated devices were controlled by the applied source, drain, and gate biases. Transport mechanisms of two devices were studied from output characteristics. The output characteristics in both the devices were obtained by sweeping the drain-source voltage (V_ds) from 0 to -3 V in steps of 0.01 while varying the gate voltage from 0 to -3 V in steps of 0.5 V. The I-V data with different gate voltages were analyzed and fitted with Fowler–Nordheim (FN) tunnelling model. Multistep hopping is found to be dominant conduction mechanism with low drain-source voltage (V_ds) and at very high voltage region, Fowler-Nordheim (FN) tunnelling mechanism is observed. In FN plots the slope has been calculated to find out the dependence between field enhancement factor and applied electric field. Field effect mobility and ON/OFF ratio of both the devices were determined from transfer characteristics.

Recently, amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) have been widely used for backplanes of actual display products like LG display OLED TV, Apple iPad, and Samsung monitor due to their advantages compared to amorphous Si TFTs, such as relatively high field-effect mobility, low off-current, and applicability to transparent/flexible devices. However the production yield of AOS TFTs in backplane is gradually decreasing, as the active-matrix displays are becoming larger size and higher resolution. For this reason, repair techniques are inevitably required for yield enhancement. In actual display industry, most companies typically use micro-chemical vapor deposition to repair defect region after laser etching process on active layer of completed TFTs. However, this existing repair technique by vacuum equipment results in high fabrication cost and complex process. Therefore, cost-effective and simple repair technique should be developed.
In this study, we investigate the repair techniques for IGZO active layer using solution process. In order to compare the effects of the repair techniques by vacuum and solution process, we deposited additional IGZO thin-films on the defective IGZO active layers by sputtering and solution process, respectively. As a result, the sputter-repaired IGZO TFT shows field effect mobility of 8.88 cm²/Vs, on/off ratio of 5.01 x 10⁸, and sub-threshold swing of 0.35. And the solution-repaired IGZO TFT has field effect mobility of 8.00 cm²/Vs, on/off ratio of 1.51 x 10⁸, and sub-threshold swing of 0.47. This indicates that electrical performance of the solution-repaired IGZO TFT is comparable to the sputter-repaired IGZO TFT. Furthermore, we performed the positive bias temperature stress test for the TFTs under V_GS = 20 V and V_DS = 10.1 V at 50^oC for 3600 s. The threshold voltage shift of sputter-repaired IGZO TFT was 4.36 V, and that of the solution-repaired IGZO TFT was 4.60 V. Therefore, the repair technique using solution process can realize and improve the electrical performance and stability of the defective TFT devices as an alternative to the existing repair technique, vacuum process.

Amorphous oxide semiconductor thin-film transistors (AOS TFTs) have many merits such as high mobility, high transparency, and low off current compared to typical amorphous Si TFTs. Though, AOS TFTs have instability problems against temperature, light, and electrical stress, the most critical problem is the instability from the adsorption of ambient oxygen species (O₂) on the back channel of AOS TFTs, because the adsorbed oxygen species (O₂) can trap electrons. Therefore, positive shift of threshold voltage (V_th) occurred under positive bias stress (PBS). For this reason, passivation layer (PVL) preventing O₂ adsorption on oxide TFTs plays a significant role in improving PBS stability. The PVLs typically consist of either inorganic or organic materials. However, PVLs of inorganic materials such as SiO₂, ZrO, and HfO₂ need high temperature annealing (> 300^oC) and have low flexibility. In contrast, PVLs of organic materials such as PDMS and PMMA are vulnerable to O₂ and moisture in the atmosphere. Here, we propose a new material, Nitrocellulose, as the PVL of amorphous indium gallium zinc oxide (a-IGZO) TFTs, which can make up for these demerits of organic and inorganic PVLs. As a result, positive shifts of the V_th under PBS test of a-IGZO TFTs without PVL, with PMMA PVL, and with Nitrocellulose PVL are 5.08, 3.94, and 2.35 V, respectively. The PBS test was conducted at V_GS = 20 V and V_DS =10.1 V for 10,000s in the air. Furthermore, a-IGZO TFTs using Nitrocellulose PVL have outstanding electrical performances compared to those without PVL: mobility, on/off ratio, and subthreshold swing (S.S) are enhanced from 9.01 to 19.10 cm2/Vs, from 5.10x10⁷ to 6.51x10⁸, and from 0.49 to 0.42, respectively. Consequently, a-IGZO TFTs using the Nitrocellulose PVL could simultaneously enhance PBS stability and electrical performances.

Organic light emitting field effect transistors (LEFETs) evolved from organic field effect transistors (OFETs) and organic light emitting diodes (OLEDs) into a new multifunctional optoelectronic device [1-3]. LEFETs combine the switching functionality of FETs with light emission of an OLED in a transistor device configuration. This dual functionality has potential for new applications including simplified pixels for high-definition organic-based emissive displays. Despite of the tremendous progress and technological potential of all-organic heterostructure LEFETs, the light emitting area is either too narrow or non-uniform and strongly dependent on the biasing conditions. Furthermore, high voltages often required to drive these devices (≈100 V), dramatically increases the overall power consumption which renders the technology unsuitable for display applications.
Here we present hybrid LEFETs fabricated using solution-processed organic and inorganic metal oxide semiconductors. We demonstrate an innovative new strategy to significantly enhance the key performance parameter of LEFETs -- operating voltage, aperture ratio, EQE and brightness in a simultaneous fashion. Remarkably, we found that the use of a work modification layer, the devices exhibit a large spatially stable light emitting area (Gate-bias independent emission area) with an aperture ratio of >75%%. These results represent a significant advancement over previously reported hybrid LEFETs and are an important milestone towards next generation display technologies.

1- Hepp, H. Heil, W. Weise, M. Ahles, R. Schmechel, H. Von Seggern, Phys. Rev. Lett. 91, 157406 (2003).
2- J. Zaumseil, R. H. Friend, H. Sirringhaus, Nature Mater. 5, 69 (2006).
3- Mujeeb Ullah, K. Tandy, S.D Yambem, M. Aljada, P. L Burn, P. Meredith, E. B Namdas, Adv. Mater. 25, 43, 6213 (2013).

For organic electronics in general and in particular organic display applications, transistors with high current output and high on/off-ratio, combined with a high transition frequency are necessary. The vertical organic field effect transistor (VOFET) offers technological advantages compared to conventional organic field effect transistors (OFETs), due to its advantageous geometric arrangement of stacked and overlapping electrodes. The short channel length allows for high output currents, while the off-current can be kept small using insulators at the source. This vertical design facilitates a high integration density and straightforward combination with other vertical organic devices. This feature has been exploited in our investigation. In contrast to the conventional lateral OFET, the basic physics and working principles have not been fully investigated till now. Of central importance are the formation, geometry, and size of the conducting channel.

We obtain the vertical current density distribution from the light emission of vertical organic light emitting transistors (VOLETs). These devices are a combination of an organic light emitting diode (OLED) and a VOFET. The vertical charge transport through the VOFET creates light emission in the emitter material of the OLED. Therefore, it is possible to locally resolve the current density via light emission. Additionally, we obtain information about the local charge carrier density and energy dissipation from drift-diffusion-simulations at different transistor states and geometries. From these data we are able to conclude the current path through the VOFET. From the comparison between measurement and simulation we get a description of the charge transport in the actual VOFET.

Using these measurements we show the dependence of the channel size and geometry on several parameters: the gate-source voltage, the drain-source voltage, and the source insulator geometry. The active area that contributes to the charge transport, determined by the so called channel depth, increases linearly with higher gate-source voltage. The dependence on the drain-source voltage shows a more complex behavior, for which we give a first characterization based on the standard transistor output equations. From the simulation and measured findings we propose a working mechanism of the VOFET similar to the lateral OFET. The accumulation of charge carriers at the semiconductor interface is similar for both devices. The distinction is the vertical current path directly at the edge of the source and the consequential broadening of the channel.

In summary, the VOFET operates in large parts analogously to an OFET with a special channel geometry. A better understanding of the basic phenomena of charge transport in such vertical transistor designs will open up new possibilities for further optimization, especially in the field of current maximization, tuning of the on/off-ratio, and integration and combination into other electronics.

The field of solution-processed photodetectors, including photodiodes and phototransistors, is expanding rapidly. Photodiodes, which show a linear responsivity to irradiance, are typically used in image sensors as the photo-active element. On the other hand, phototransistors show photoconductive gain and sub-linear responsivity to irradiance. Photoconductive gain improves signal-to-noise ratio (SNR) at lower irradiances while the sub-linear responsivity delays the saturation of charge in the pixel since quantum efficiency is lowered at higher irradiances. These combined effects can significantly improve the dynamic range of an image sensor. In addition, the SNR of an image is improved by orders of magnitude if the photodetector in a pixel integrates photogenerated charge during a frame period prior to readout by external circuitry. Despite the practicality of charge integration and potential of wide dynamic range, a solution-processed phototransistor image sensor has not yet been demonstrated to operate at video frame rates. Here we show partially-printed phototransistors using a novel channel architecture consisting of a high mobility organic semiconductor on top of an organic bulk heterojunction (BHJ). The semiconductor shows the same crystallization on the BHJ as seen in conventionally-made devices, which results in a mean mobility of 1.47 cm²/Vs and on-off ratio of over 10⁵ with little variability and no noticeable hysteresis in the on-state. The underlying BHJ allows absorption outside the spectrum of the high mobility semiconductor, yielding external quantum efficiencies (EQEs) above 1200% in the on-state. These phototransistors also integrate charge by efficiently accumulating photogenerated electrons in the channel in the off-state. Turning the device back on after integration results in readout of the integrated signal in less than 60 μs. The final imaging array is formed by inkjet printing conductive vias on the source-drain electrodes prior to screen printing conductive traces and inter-layer dielectrics to form addressable lines. The photoconductive gain, efficient charge integration and fast response time of these devices enables EQEs of over 100% at irradiances below 1 μW/cm² in the visible spectrum integrated at 100 frames per second (fps). The sublinear responsivity to irradiance of these devices results in a wide dynamic range of over 100 dB at 30 fps.

Exciton-polaritons are quasiparticles that form upon strong coupling between electronic excitations of a material and photonic states of a surrounding microcavity. In organic semiconductors and semiconducting single-walled carbon nanotubes the special nature of the excited states leads to particularly strong coupling, which can be used for a wide variety of physical effects (e.g., condensation, polariton lasing etc.) even at room temperature. While emission from exciton-polaritons is usually created by optical excitation, the high ambipolar charge carrier mobilities of narrow-bandgap conjugated polymers and single-walled carbon nanotubes make them suitable for electrically driven polariton light-emitting devices with extended functionalities. We previously demonstrated the integration of gold nanorod antennas in the active channel of an ambipolar, light-emitting field-effect transistor based on a high mobility, near-infrared emitting polymer (DPPT-BT) and the resulting voltage-switchable enhancement of electroluminescence due to the Purcell effect in the weak coupling regime (ACS Photonics 2016, 3, 1–7). Here we show that also strong coupling and near-infrared exciton-polaritons can be achieved in light-emitting field-effect transistors by using microcavities or plasmonic crystals. These devices may also offer the chance to further explore possible effects of strong coupling between semiconductors and plasmonic modes on charge transport properties.

Organic light-emitting transistors (OLETs) are increasingly gaining interest within both the scientific and technological community due to their 2-fold functionality of behaving as a thin-film transistor and at the same time being capable of generating light under appropriate bias conditions.
In this work, we report on the fabrication and optoelectronic characterization of red organic light-emitting transistors fabricated on glass/ITO/polymer gate dielectric with an unprecedented high external quantum efficiency (EQE) of approximately ≈5% in the limit of maximum brightness. This experimental result is comparable with standard OLED devices available in literature using same emitting dye.
Bottom-gate/top-contacts OLETs are fabricated on glass/ITO/PMMA substrates using a standard tri-layers structure, with the active area consisting of a stack of three different organic layers: a field-effect hole transport layer in direct contact with the gate dielectric, an intermediate host-guest layer where the recombination and light emission takes place and a field-effect electron layer.
In addition, in light of more specific market compatible application, we have substituted the gate dielectric (PMMA) with a different polymer with a higher value of dielectric permittivity to further allow the reduction of the operating voltages while retaining optical performances as previously achieved. Large EQE values and reduced operating regime compatible with commercial electronics both play a crucial role in the future exploitation of this novel technology platform in various optoelectronic fields

Among the specific challenges for the conventional lateral channel TFT is driving the high currents needed for high brightness OLEDs, while exhibiting uniform performance characteristics over large area displays. Manufacturers have sought solutions in improved channel materials. By laser annealing a-Si they form low temperature polycrystalline Si, which solves the problem for hand held displays, but this has proved challenging to make uniform over large areas. The amorphous quaternary compound indium gallium zinc oxide has demonstrated good uniformity over larger areas, but a high sensitivity to processing conditions has resulted in high failure rates (to date) that keep the cost of commercial OLEDs too high for the mainstream. Known as the (active matrix) AMOLED backplane problem this is perhaps the key reason that AMOLEDs (despite their visual advantages) have not dominated the display industry.

Academia has explored novel channel materials like graphene, but this only exhibits the requisite bandgap when configured in nanoscale widths along specific crystallographic axes that are difficult to produce. Semiconducting single wall carbon nanotubes (SWNTs) possess the needed bandgap, and their networks have high mobility, but separating the semiconducting from the simultaneously produced metallic nanotubes remains too costly.

We did not know it at the time, but beginning 10 years ago this year, we conceived of an alternative vertical TFT design, the CN-VFET, that has since been elaborated into one of the most promising solutions to the AMOLED backplane problem. A QVGA prototype of that solution won the I-Zone award for best prototype at the recent 2016 SID meeting.

The carbon nanotube enabled vertical organic light emitting transistor (CN-VOLET) simplifies the display pixel design to two components, the switching transistor and the CN-VOLET. This permits high aperture ratio (70%) bottom emission displays, which should benefit emitter lifetimes and greatly simplify display manufacturing. I will discuss the challenges and developments that led to this milestone.

Recently we developed a method to fabricate all-carbon-based, transparent, flexible and all-printed organic field effect transistors (OFETs) and complementary circuits in ambient conditions with scalable production techniques, but a clear demonstration of the feasibility of this method for the fabrication of real-life applications is still lacking.
In this work, after a brief analysis of the fabrication of reliable complementary circuits and photodetectors in a fully-printed approach with all-polymeric materials, we describe their integration into a stand-alone implementation realizing an all-organic integrated photo-active switch on plastic, an application usable in real-life contexts, e.g. for a twilight sensor or for industrial machinery control. The fabricated photo-active switch detects the amount of environmental light power and triggers a digital ON/OFF signal at pre-defined threshold conditions. In particular, the OFF signal is provided when the light power exceeds a preset P_T+ threshold and the ON signal is triggered when the light power drops under a second P_{T –} threshold, with P_T– < P_T+. This feature, intentionally designed, grants an intrinsic immunity to light fluctuations, a feature that may be desirable for particular applications operating in a real-life context. Indeed, a commonly required behavior for devices responding to environmental stimuli is to trigger their state when a predefined threshold condition is met, and then reject any possible smallsignal fluctuations (i.e. the devices should hold their new state until the stimulus undergoes a large variation). The photoactive switch described in this work is provided with this advantageous capability, guaranteeing its suitability for integration in applications requiring the detection of and reaction to environmental light conditions.
Here we single out and investigate a possible example: a twilight switch, a device used in outdoor lighting to automatically activate illumination at night or in general when environmental light is lacking. The immunity to fluctuations, which is a key feature in our implementation, effectively rejects small light intensity drops and peaks which are common in a real-life environment (i.e. due to the build-up of clouds or the passage of a body in front of the device).

Recently, the invention of the triboelectric nanogenerator (TENG) has provided an effective approach to convert ambient mechanical energy into electricity, which has great application in micro-energy, macro-energy, and active sensors. On the other hand, the triboelectric induced potential difference is an inner electrical signal created by the external mechanical force, which could be used as a gate signal to tune/control the carrier transport characteristics in field effect transistor as the same effect as applying a gate voltage. In 2014, by coupling triboelectricity and semiconductor, tribotronics as a new field is proposed, which is about the devices fabricated using the electrostatic potential created by triboelectrification as a “gate” voltage to tune/control electrical transport and transformation in semiconductors.
In the past two years, various tribotronic functional devices have been experimentally demonstrated. The tribotronic logic device has established the relationship between the mechanical force and CMOS logic electric level and universal combinational logic circuits have been demonstrated for first performing mechanical-electrical coupled tribotronic logic operations. The flexible organic tribotronic memory has demonstrated an active memory which can be written and erased by externally applied touch actions. The organic and MoS₂ tribotronic transistors have extended the tribotronics to the organic and 2D materials, respectively, and exhibited the material variety for the interactive application. By further introducing optoelectronics, a new field of tribo-phototronics has been consequently derived by three way coupling among triboelectricity, semiconductor, and photoexcitation. The tribotronic light-emitting diode and phototransistor have been developed for demonstrating the triboelectric charges enhanced light-emission and photoelectric conversion characteristics, respectively.
Tribotronics has established a direct interaction mechanism between the external environment and electronics, which is likely to have important applications in sensors, human silicon technology interfacing, MEMS, nanorobotics, and active flexible electronics. As an extension of the proposed piezoelectric nanogenerator in 2006, piezotronics in 2007 and triboelectric nanogenerator in 2012, tribotronics is another original and novel field in the development of nano-energy and nano-electronics. The concepts and results presented in this review show promises for implementing novel micro/nano-electromechanical devices that may derive plenty of potentially important research interests and applications in sensing, energy harvesting, human-machine interfacing, MEMS/NEMS and active flexible/stretchable electronics in the near future.

Organic field-effect transistors (OFETs) have increasingly gained interest during the last few years due to their potentials of enabling low-cost, lightweight, and large-area electronics on mechanically flexible and transparent substrates.
In this work, we report on the fabrication and detailed characterization of single-layer (SL) OFETs based on a recently developed n-type organic semiconductor based on a thieno-thiophene core, 2,5-bis(4-(perfluorooctyl)phenyl)thieno[3,2-b]thiophene (N-F2-6). Being OFETs properties very much dependent from the interfaces with the metal contacts and/or the substrate surface and/or the dielectric surface, the control of the degree of crystallinity, morphology and film uniformity over large area plays a crucial role in determining the performances of the transistor. Bottom-gate/top contact (BG/TC) OFETs were fabricated on ITO/glass substrates, with PMMA as dielectric material. We show that by modifying the fabrication process parameters and conditions (i.e. sublimation rates, substrates temperature, organic layer thickness), it is possible to optimize the interested interfaces, leading to the enhancement of the transistor properties and to values of electron mobility of μ_e= 0.1-0.2 cm²/Vs and threshold voltages of about 40V.
In particular, we show that the optimization of the n-type layer is important for a novel class of optoelectronic devices represented by organic light emitting transistors (OLETs), devices with a 2-fold functionality of behaving as a thin-film transistor and at the same time being capable of generating light under appropriate bias conditions. Thus, we will also report on the implementation of this new semiconductor in OLETs.

Different from changing local chemical composition in conventional band gap engineering, controlling the band structure through local-strain engineering is an exciting method for tailoring properties of two-dimensional (2D) transition metal dichalcogenides (TMDs). Here, various scale of wrinkles (10 nm to 10 μm in wavelength) were fabricated to induce strain in multilayer MoS₂ flakes (about 10 layers). Molecular dynamics simulations and energy analysis was applied to understand the mechanism of wrinkles formation and calculate the surface adhesion energy between MoS₂ and SiO₂ (0.1 to 0.4 J/m²). We report the first field effect transistor (FET) device based on wrinkled MoS₂ on SiO₂. A strain-induced reduction (~ 48 meV / % strain) of the optical bandgap was observed by photoluminescence, and a strain modification of electronic transport band gap was detected in FET. We also show that wrinkled MoS₂ FETs are capable of performing as chemical sensors. The tunable bandgap transistor demonstrated here will have a profound impact on optoelectronic and flexible electronic devices based on 2D TMDs.

We investigate the requirements on the barrier height and on the charge carrier mobility as they interact to restrict the current in contact-controlled source-gated transistors made with non-Schottky source barriers.

Source-gated transistors (SGT) are thin-film devices with a potential barrier deliberately incorporated in the charge injection pathway at the source. This leads to low-voltage current saturation, increased robustness in terms of stress stability and geometrical variability, and high intrinsic gain.

SGTs have been made in a wide variety of material systems and using various techniques (a-Si, poly-Si, ZnO, solution processed organic materials and nanoparticles, evaporated small molecules). Conventionally these devices are fabricated using Schottky barriers for convenience, but the dynamic range of the on-current is comparatively low. Using bulk or surface barriers realized by doping, or heterojunctions, instead of the Schottky source barrier increases the dynamic range of drain current above the threshold and reduces its temperature dependence.

Here we investigate the impact of the effective barrier height and of the effective field-effect mobility of the different semiconductor layers in the current-control source heterostructure on the drain current at different bias conditions. We report on measurements on silicon and fullerene structures, and support our understanding using TCAD simulations with Silvaco Atlas. Large threshold shifts (>10V) and significant drops in current (~10^-2) are observed when the above-mentioned properties are not carefully matched (e.g. low mobility of the middle of the three heterostructure layers), and usually without the benefit of early saturation and high gain.

The correct choice of material properties and process compatibility makes the task of designing heterostructure SGT devices far from trivial. Several optimization avenues are proposed. We envisage SGTs as a versatile, topical-application device for a wide range of applications of ultra-low-power, low-cost flexible electronics.

Solution-processed ambipolar organic thin-film transistors (TFTs) offer great potential for simple and low-cost fabrication by means of easy-to-fabrication process and both n-type and p-type operation in a single device. Nevertheless, the DC-gain, noise margin, power consumption of ambipolar organic circuits suffer from the fact that always one of the transistors in the inverter cannot be switched off completely. Hence, the typical Z-shaped inerter characteristics is shown in ambipolar inverters. We present novel split-gate ambipolar TFTs architectures (co-planar with gate-gap, non-planar, and inverted non-planar split-gate TFTs) to operate as an either p-type or n-type device depending on the bias voltage at the secondary-gate for complementary circuitry. Non-planar split-gate TFTs with no gate-gap showed orders of magnitude higher performances compared to co-planar split-gate TFTs. We also present 2D numerical simulations for comprehensive understanding of different split-gate device structures. Finally, reconfigurable complementary logic circuits using split-gate were demonstrated for the first time.

Benefitting from smaller natural length to prevent short channel effect, thin film transistors (TFTs) based on mono- or few-layer 2D materials have demonstrated the potential for future electronics. In our previous reports, we have introduced layer by layer growth of tin monoxide (SnO) and successfully fabricated TFTs using 2D p-type SnO channels. However, for the fabrication of any advanced electronic devices, e.g. complementary metal oxide semiconductors (CMOS), we need both p-type and n-type materials. A small band gap and a deep conduction band maximum makes SnO feasible for n-type doping. Though N-type conductions have been achieved by doping, so far there are no reports on TFTs based on n-type SnO. Herewith, we are reporting fabrication of n-type SnO for n-channel TFTs by doping with antimony (Sb). By growing the film using pulsed laser deposition, n-type SnO preserve the layered structure. Raman, UV-Visible spectroscopic, transmission electron microscopic analysis were performed to confirm the structure and phase of SnO. X-ray photoemission spectroscopy was performed to examine the binding environment of element Sn and Sb. Substitution of Sb³⁺ to Sn²⁺ compensates the hole carriers and provides electron conduction. TFTs fabricated using both n- and p- type SnO are excellent candidates for all 2D CMOS devices.

Extensive research has been done on amorphous InGaZnO (a-IGZO) for its application in thin-film transistors (TFTs)¹. For TFTs, the reduction of parasitic capacitance and improvement of the channel's interface with the source/drain are important challenges currently being addressed. Self-align methods such as Ti/Al reaction method² have been proposed to improve the a-IGZO conductivity and its contact with the source/drain. Moreover, a-IGZO conductivity can be further increased by rapid thermal annealing³ for electrode application in transparent self-aligned TFTs. Nevertheless, these methods require high temperatures of ~400°C limiting the type of applicable substrates.
We have previously reported how excimer laser annealing is a low temperature method (<30°C) that improves the characteristics of a-IGZO TFTs⁴. In this report, we show how a single shot of excimer laser can significantly reduce the sheet resistance (R_s) and thus increase conductivity of a-IGZO at low temperatures. Elemental analysis by Secondary Ion Mass Spectrometry (SIMS), X-ray Photoelectron Spectroscopy (XPS) and Energy-dispersive X-ray Spectroscopy, and cross-sectional imaging by Scanning Transmission Electron Microscopy (STEM) were performed to elucidate the mechanism.
a-IGZO is deposited at room temperature by RF magnetron sputtering on Si with thermal SiO₂ and subjected to heat treatment (150°C in N₂/O₂). A single shot of a KrF excimer laser (λ=248 nm) at different fluence energies (E) and different atmospheres (ambient air, Ar ~350 Pa, and vacuum <10^-3 Pa) was performed. The R_s was measured by standard four-point probe method. Irradiation with a single shot of KrF laser dramatically reduced the R_s of a-IGZO from >1000 Ω/sq (no irradiation) to as low as 0.05 Ω/sq. Irradiating in air at an E of 70 and 100 mJ/cm² decreased R_s to 349.31 and 39.67 Ω/sq, respectively. Higher R_s reduction was achieved by increasing E and irradiating in vacuum or Ar. Irradiation at 120 mJ/cm² in vacuum and Ar decreased R_s to 0.23 and 0.05 Ω/sq, respectively – comparable with transparent electrodes.
SIMS show a lower amount of H and OH in a-IGZO after irradiation in Ar and vacuum compared to in air. Analysis of deconvoluted O 1s XPS peaks (O_M – 530.2 ± 0.1, O_def – 531.2 ± 0.1, O_H – 532.2 ± 0.1) revealed a higher amount of oxygen vacancies (related to O_def) is present in samples with lower R_s. Area ratio of O_def/O_all in a-IGZO bulk was 49.8%, 53.9%, and 72.5% after irradiation at 100 mJ/cm² in air, 120 mJ/cm² in vacuum, and 120 mJ/cm² in Ar, respectively. STEM images show no substrate damage was induced by laser irradiation. These results confirm that excimer laser irradiation can control oxygen vacancy concentration and increase a-IGZO conductivity at low substrate temperatures <30°C.

1. T. Kamiya et al., Sci Technol Adv Mater 11, 044305 2010
2. N. Morosawa et al., J Soc Inf Disp, 20, 47 2012
3. H.-C. Wu et al., IEEE Elect Dev Lett, 35, 645 2014
4. J.P. Bermundo et al., J Phys D: Appl Phys, 49, 035102 2016

Studies on electrostatic carrier doping utilizing correlated oxide-FETs have developed as new avenue to not only realize Beyond-CMOS, but also probe underlying complicated physics in condensed matters. Among many correlated oxides, vanadium dioxide (VO₂) as a prospective candidate, possessing a dramatic resistance change with metal-insulator phase transition (MIT) around 340 K, has attracted much attention. Although VO₂ FETs are focused and have been prepared by conventional gate schemes such as SiO₂, Al₂O₃ and HfO₂, atomic mixture at the interface and/or the defects of channel interface generates high trap density, inducing slow and inefficient switches. Meanwhile, recent researches on MIT induced by electric double layer transistor (EDLT) have indeed been demonstrated, while an open question about the existence of chemical reaction still remains. Therefore, it is necessary to develop robust dielectrics for gate layer to realize not only lower trap density but also trigger huge sheet carrier density. In this study, we prepared VO₂ FETs using a hybrid gate insulator using organic polymer polychloro-p-xylylene (parylene-C) and high-k material Ta₂O₅ (ε_r=26). The parylene-C has a role as reduction of interface trap density and the hybrid gate with high-k material keeps high dielectric constant. In this symposium, we will report on the observation of reversible and immediate conductive switching by the hybrid gate [1] and on the achievement of over 8 % modulation of resistance change rate defined as (R_off-R_on)/R_off x 100 % in VO₂ nanowire channels. The results in this research provide a possibility for clarifying the origin of metal-insulator transition in VO₂ through the electrostatic field-induced transport modulation.
[1] T. Wei, T. Kanki and H. Tanaka et al, Appl. Phys. Lett. 108, 053503 (2016).

Much of what is understood about transparent conducting oxides (TCOs) comes from structure-property relationships that presuppose the presence of long-range order. Required for the new frontier of display technology, deposition on flexible substrates can be realized with the use of amorphous (a-) TCOs created through low-temperature deposition. The consequence of low temperature is a loss of long-range structural order, which negates the use of characterization techniques such as X-ray diffraction and simulations with periodic boundary conditions. We employ local structure, element-specific, X-ray measurements, performed at the Advanced Photon Source, to gain an understanding of how cation composition affects the local structure in a-TCOs. With this knowledge of structure, we develop structure-property relationships unique to a-TCOs.

The a-TCO system of indium gallium oxide (a-IGO) is a model system for developing structure-property relationships to investigate the influence of substitutional cations on the performance of a-TCOs. We will present a systematic study of the evolution of thermal and electrical properties, as a function of gallium content, in a series of a-IGO thin films. These property studies were understood on a fundamental level by pairing them with local structural studies, X-ray absorption spectroscopy (XAS) and anomalous X-ray scattering (AXS).

The onset of crystallization in pure a-IO reduces carrier mobility.¹ Our work shows that this temperature threshold can be increased from 125 to 425°C by substituting gallium for indium. We attribute this effect to gallium’s ability to remain 4-fold coordinate even when surrounded by a higher coordinate indium oxide matrix and thus resists the transition into the bixbyite crystalline phase. In terms of electrical performance, oxygen vacancies have been shown as the source of carriers in indium-oxide-based a-TCOs.² Gallium is shown to decrease carrier concentration when added to a-IO and create a semiconducting TCO. Our work shows that the decreased carrier concentration can be understood through the comparison of metal-oxygen coordination with resulting metal oxygen distances. We reveal that gallium does not produce carriers itself and reduces carrier concentration by diluting oxygen-vacancy-producing indium octahedra. From a deep understanding of gallium’s effect on a-IO, future substitutional atoms can be considered for the modification of a-TCOs to continue their expansion into flexible display technology and beyond.

This work is supported by the NSF MRSEC Program No. DMR1121262
[1] D. B. Buchholz, Q. Ma, D. Alducin, A. Ponce, M. Jose-Yacaman, R. Khanal, J. E. Medvedeva, and R. P. H. Chang, Chem. Mater., vol. 26, pp. 5401–5411, 2014.
[2] S. L. Moffitt, A. U. Adler, T. Gennett, D. S. Ginley, J. D. Perkins, and T. O. Mason, J. Am. Ceram. Soc., vol. 7, pp. 2099-2103, 2015.