Nanocrystal-based memories could potentially become an evolutionary replacement for the polycrystalline silicon used in conventional programmable flash memory for todayâ?Ts electronic equipment. In nanocrystal (NC) based metal-oxide-semiconductor (MOS) memory structures a fine tuning of the NCs characteristics (NC location in the gate oxide, size and surface density) is required for the pinpointing of optimal device architectures. Ultra-low energy (typically 1 keV) ion implantation (ULE-II) is a powerful technique for the controlled synthesis of two-dimensional (2D) arrays of Si NCs embedded in thin (10 nm) SiO2 layers. Both EEPROM-like and NVRAM-like transistors have been fabricated by coupling ULE-II and annealing under oxidizing ambient. These NC-based memory devices show comparable data retention and endurance characteristics than the actual SONOS-like structures. Recently, the charge pumping technique (CP) has been adapted to this particular system, allowing the measurement of the charge trap density, size and depth-distribution. A good agreement is obtained between these trap characteristics extracted by CP and the corresponding images of the NCs population obtained by EFTEM. This comparison confirms that charge trapping takes place in the NCs. In addition, low temperature I-V measurements shows that most of the charging occurs in NCs confined levels. The trade-off between programming and data retention gate oxide engineering can be improved by replacing the SiO2 matrix by high-k dielectrics. We present at last an innovative architecture where HfO2 acts as tunnel oxide between the Si substrate and 2D arrays of Si-NCs and Ge-NCs are fabricated by ULE-II in a thin SiN top layer. Low power operating NCs memories showing 10 yrs retention are obtained by using such stacks.

The concept of nanocrystal (NC) or quantum dot (QD) nonvolatile memories (NC-NVM) has been intensively explored in the last decade for CMOS and flexible electronic devices. Various approaches have been proposed to successfully combine the fast operation voltages with long data retention such as the tunnel barrier engineering approach and the use of QDs of metals with high work function. The work function engineering of the QDs may improve the performance of NVMs in terms of operation voltages and retention time. This can be achieved by forming semiconductor QDs exhibiting negative conduction band offset with respect to the substrate. Assuming a Si substrate with a thin SiO2 tunneling layer, gallium nitride (GaN) QDs fulfill these requirements. In this direction, we focused our efforts on the realization of GaN-QDs structures on thin SiO2 layers. The GaN-QDs were formed by radio frequency plasma assisted molecular beam deposition (RF-MBD) on 3.5nm SiO2 films on (100) n-Si substrates. Several deposition conditions for QDs realization were investigated in order to evaluate a range of QDs size and density distributions. LPCVD SiO2 layers ~15 nm thick have been used as capping dielectric. For comparison, a control sample without QDs, but treated in similar conditions and exposed to RF N-plasma, at the QDs growth step, was also fabricated. High frequency C-G-V-f characteristics measured using Al gate MOS capacitors on the fabricated samples, in order to investigate the charge trapping properties. Control sample exhibited no hysteresis after a round voltage sweep. Contrary, the QD MOS capacitors exhibited strong hysteresis at relatively small voltages due to electron trapping; hole trapping is limited probably due to the thick tunnel oxide. I-V characteristics were obtained in order to investigate the charge injection mechanisms. Finally, charge retention measurements carried out at room temperature revealed that a significant memory window remains after ten-years extrapolation.

Conventional flash memory with continuous floating gate faces increasing challenge brought by charge leakage and other scaling related issues. Si nanocrystal (NC) memory was introduced as an alternative to continuous floating gate memory and has attracted intensive attention for its CMOS compatible fabrication process, immunity to oxide defect leakage together with its promising scalability thanks to the discrete charge storage nodes. Tremendous efforts have been invested into NC memory research ever since, using new cell structures and new materials. Nevertheless, NC density and uniformity fluctuation has arisen as a critical concern as NC memory is unexceptionally approaching its scaling limit as other counterparts do. NC number variation from cell to cell imposes serious constraints on overall device performance with respect to programming, erasing, memory window and retention uniformity. Furthermore, the reducing number of NCs in ultra-scaled memory cells severely limits the memory state reliability and would eventually lead to cell performance failure. Non-planar device structure has been nominated a promising candidate for the scaling-down of modern electronics. As Intel announced the application of Fin-FET structure at 22nm nodes, more and more attention has been paid to extending electronic device structure to the 3rd dimension. The motivation behind this work is to explore and demonstrate non-planar floating gate memory cell structure with high-density uniform metallic silicide NC charge storage nodes to extend the scaling limit of NC memories without compromising the device reliability. Non-planar memory cell architecture was implemented by anisotropic wet etching of ultra-thin Si (100) active layer of commercially available SOI wafer to achieve aligned triangular-shaped Si nanowire array as channels of the memory transistor. NiSi nanocrystals of high density and good uniformity as floating gate were synthesized by vapor-solid-solid growth in a low pressure chemical vapor deposition system. Memory device was fabricated and characterized. The device shows good programming, erasing and retention performance and may be a viable candidate to replace conventional planar flash memory at the further-scaled memory technology nodes.

Nanocrystal (NC) memory technology is one of the leading alternatives to traditional poly-Si floating gate memory because of its improved scalability, speed and simpler fabrication. In this presentation we report a memory structure based on self-aligned Si NCs grown over Al2O3 covered parallel-aligned carbon nanotubes (CNTs) by gas source molecular beam epitaxy. Si NCs align on the apexes of the CNTs due to strain in the Al2O3 layer as a result of the CNT underneath it. These alignment properties are studied with relation to different growth conditions and sample parameters. Electrostatic force microscopy characterizations directly prove the charging and discharging of discrete NCs through the Al2O3 layer covering the CNTs. A CNT field effect transistor based on the NC/CNT structure demonstrates evident memory characteristics such as direct tunneling and Fowler-Nordheim tunneling phenomena at different programming/erasing voltages. Retention is demonstrated to be on the order of 104 s. Although there is still plenty of room to enhance the performance, these results suggest that CNT-based NC memory with diminutive CNTs and NCs could be an alternative structure to replace traditional floating gate memory.

Due to the scaling limitation of the conventional floating gate memory devices beyond the 20 nm technology node, nanocrystal (NC) floating gate memory devices have attracted attention as one of the strong candidates for nonvolatile memories devices because of its scalability, electrical isolation and low charge leakage. In the past decade, semiconductor nanocrystals such as Si, Ge, and metal nanocrystals such as Ag, Ni, Pt, Au, Co, have been reported. In particular, using metallic NCs has several advantages over their semiconductor counterpart, such as higher density of states, large work function and strong charge confinement, which allow memory devices to operate with higher density, lower power and better retention. Both academia and industry have invested tremendous efforts into research of NC memories, exploring new materials or novel gate structures. As an alternative way of improving memory performance, NC coreshell structure with additional barrier layer as trapping layer has been developed and adopted by researchers. However, most of the metal or semiconductor NC coreshell structures were formed to induce only native oxide shell by laser irradiation or annealing, which limits the coreshell materials and the performance improvement of NC coreshell memory. In this paper, we propose a simple but effective process to form the Au-Al2O3 coreshell structure. Through annealing in O2 ambience for thin Al/Au/Al stack layers at proper conditions, Au-Al2O3 coreshell NCs can be formed uniformly. A metalâ?"oxideâ?"semiconductor capacitor memory device with Au-Al2O3 coreshell NCs is also demonstrated in this work. For memory device, electrical measurements exhibited a considerable window, fast program/erase speed and good endurance characteristics. Specially, combining the high work function of Au NCs and the high potential barrier of the Al2O3 coreshell, promising and improved charge retention is achieved compared to the device without coreshell. Therefore, the proposed structure shows good potential for high performance flash memory application.

Graphene field effect transistor (FET) based flash memory was demonstrated by using nickel nanocrystals as charge storage nodes. The graphene films were synthesized using a thermal cracker enhanced gas source molecular beam epitaxy system and Co thin film was used as catalyst. Film characterizations by transmission electron microscopy and Raman spectroscopy show that the resulting film is mostly single and bi-layer graphene. The film is then transferred to a SiO2 surface and patterned to be used as the FET channel. On/off operation of the transistor memory was acquired by static pulse response measurement. The memory window of the device was found up to be 23.1 V by back gate sweep. This memory effect is attributed to charging/discharging of nanocrystals. Furthermore, excellent retention and endurance performance were observed.

Ge/Si nanocrystals (NCs) exhibit discrete atom-like energy levels due to three dimensional confinement. These controllable, geometry dependent properties of NCs make them attractive materials for NC memory applications and optoelectronic and photonic devices, such as lasers, infrared detectors, solar cells, etc. NCs exhibit a wide range of morphological variation, such as shape, size, and composition. These properties affect the strain, energy levels, confinement energy, and inter-band transitions. In order to understand the impact of morphology on the electrical and optical properties of large-scaled Ge/Si dome-shaped NCs, we performed atomistic, tight-binding, quantum-mechanical modeling as implemented in NEMO-3D. Geometries were optimized using the Valence Force Field (VFF) model. The effects of strain were included in the Hamiltonian matrix elements when calculating the electronic states. Base diameters were varied from 5 nm to 50 nm keeping the total height fixed at 10 nm. The Ge core is lens shaped with a maximum fixed height in the center of 3 nm. The Si capping layer has a fixed maximum height of 2 nm. The total number of atoms in the NCs ranged from 7088 to 745,176 corresponding to the 5 nm and 50 nm NC, respectively. . The observed electronic and optical properties of Ge/Si NCs are compared with pure Ge and Si NCs of similar sizes. The hole confinement energy in the Ge layer increases from 0.48 eV to 0.75 eV as the base diameter increases from 5 nm to 50 nm. This hole confinement can increase hole retention lifetime in NC memory. The energy gap of the Ge/Si NC varies from 0.92 eV to 0.40 eV when base diameter increases from 5 nm to 50 nm, respectively. The inter-band transition time for out-of-plane (vertical) polarization for Ge/Si NCs remains shorter than the pure Ge and Si NCs of the same size because of the smaller inter-band energy separations. Hence, the integration of such Ge/Si NCs into the silicon microelectronics platform promises the development of Si-based optoelectronic devices with complex functionalities. This work is supported by the National Science Foundation (NSF) under Award No. DMR-807232. We thank Dr. G. Klimeck and NCN/nanohub.org for providing NEMO3D. Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Corporation, for the United States Department of Energy under Contract No. DEAC04- 94AL85000.

Silicon oxide can provide a resistive change memory material in two-terminal devices. Described will be a series of switching events monitored by in situ TEM wherein metallic phases of silicon nanowires are generated within SiOx. These metallic filaments serves as the reversible fuse-like devices in the resistive change switches that exhibit 100,000 to 1 ON:OFF ratios in non-volatile, radiation hard (X-ray, proton and heavy ion) devices. This work has been extended to making "invisible" or transparent memory upon glass and flexible plastic substrates using ITO or graphene as the transparent electrodes. The invisible memory has also been demonstrated in crossbar arrays using the same transparent electrodes.

We demonstrate an one-transistor-one-capacitor (1T1C) device for the bit unit of ferroelectric nonvolatile random access memory (FRAM), which is compatible with flexible electronics, and based on the 1T1C device performance, we also develop FRAM arrays constructed using two-transistor-two-capacitor (2T2C) as each bit of memory cell. The 1T1C memory unit consists of one thin film transistor (TFT, n-type) for access control and one ferroelectric capacitor (FCap) for data storage. The n-channel TFTs is fabricated using cadmium sulfide as the semiconductor and the FCap is based on poly(vinylidene fluoride-trifluoroethylene) copolymer. The 2T2C memory unit incorporates two paired 1T1C: one for data storage and the other one for readout reference. The FRAM is fabricated using photolithography process and standard interconnect technology, which includes two inter-level dielectric layers. The maximum processing temperature is 150 degree C and 120 degree C for the TFT and the FCap, respectively. From the Id-Vg plot of the isolated TFT, the carrier mobility and threshold voltage can be extracted to be ~1 cm2/V-s and 5V, respectively. The hysteresis loop of the isolated FCap shows high spontaneous and remanent polarizations with a coercive voltage of 7.9V (for P(VDF-TrFE) film thickness as 150 nm), which corresponds to a coercive field of ~0.5MV/cm. More than 85% of the initial switching polarization remained with low nonswitching polarization after 1E+6 cycles of switching at room temperature. The FCaps was also tested in a temperature range from -60 to 60 degree C. For the fabricated 1T1C memory unit, the FCaps can be repeatedly accessed through the TFTs by applying a turn on voltage on the word line (WL), and large signal margin can be achieved on the bit line (BL) for different polarization states of the FCaps. In FRAM array, each bit of memory is independently addressed using WL and BL, and Plate line (PL) is pulsed to write and read data.

Most materials with large electric polarization are based on the perovskite structure ABO3, such as BaTiO3 and PbTiO3 (PTO). SnTiO3 is predicted to be ferroelectric with properties comparable to BaTiO3 [1-3]. Ferroelectric materials which are lead and bismuth free, yet without compromising performance are investigated for environmental considerations. In the case of PTO, attempts to replace Pb2+ by Ca2+ have the effect of reducing the tetragonality of the material and limiting the ferroelectricity. However only several compounds containing Sn2+ have been reported so far, because Sn4+ is generally more stable. A quick look at the periodic table would suggest that replacing Pb2+ by isoelectronic Sn2+ would give SnTiO3 (SNO) with the perovskite structure. For the first time we report on the experimental discovery of a SNO phase, in the form of thin films grown on various substrates by pulsed laser deposition [4]. They exhibit an unexpected epitaxial relationship, different from the predicted perovskite structure. Extensive x-ray diffraction and transmission electron microscopy experiments show that the films grown have an ilmenite structure. The films are insulating but do not display any ferroelectricity at room temperature, while ferroelectricity has been predicted for the perovskite structure only. However the films provide original magnetic and mechanical properties. Furthermore a very small quantity of the perovskite phase has been identified in the films which is promising for obtaining perovskite SNO. [1] Konishi, Y.; Ohsawa, M.; Yonezawa, Y.; Tanimura, Y.; Chikyow, T.; Wakisaka, T.; Koinuma, H.; Miyamoto, A.; Kubo M.; and Sasata, K. Mat. Res. Soc. Symp. Proc. 748, U3.13.1 (2003). [2] Matar, S.F.; Baraille, I.; Subramanian, M.A.; Chem. Phys. 355, 43 (2009). [3] Uratani, Y.; Shishidou, T.; and Oguchi, T. Jpn. J. Appl. Phys. 47, 7735 (2008). [4] T. Fix, S.L. Sahonta, V. Garcia, J.L. MacManus-Driscoll, and M.G. Blamire, Cryst. Growth Des. 11, 1422 (2011).

Since the scaling of the DRAM capacitor is a nightmare, a responsible strategy consists in simply suppressing the storage capacitor. Silicon-on-Insulator (SOI) technology offers the possibility to store the charges directly in the floating body of a MOSFET which is also used to read the data. These memories, usually referred to as 1T-DRAMs, use only one transistor and take advantage of floating-body effects that were considered before only as parasitic phenomena. In the last decade, many 1T-DRAM versions have been conceived: partially or fully depleted, simple-gate or double-gate, planar or vertical (FinFET), etc. We will review the most promising and recent concepts, by focusing on MSDRAM, ARAM, Z2RAM. The device geometry, scaling issues and different methods for programming and reading will be critically discussed. An even more advanced paradigm is the â?Tunifiedâ?T memory device. An ideal candidate is again the SOI MOSFET which basically features two (or more) independent gates: each gate can be given separate tasks (program, store or read the charge). We will show solutions for (i) combining, within a single SOI transistor, volatile and nonvolatile memory functionalities, and (ii) reaching multiple memory states.

Recently, a new architecture for floating gate (FG) devices that could extend the NAND flash roadmap for sub-20 nm technologies has been proposed1-2. In this concept, the standard poly-Si FG is replaced by a poly-Si(n type)\metal(p type) stack, so called hybrid FG or HFG. The higher workfunction of the metal limits the leakage from the floating to the control gate, which combined with high permittivity materials as interpoly dielectric (IPD), enables the scaling of the FG toward more aggressive dimensions. The concept has been demonstrated in 50-nm HFG CMOS integrated memory cells3. In the present work, we report on the materials issues involved in successful HFG device fabrication. For that purpose, we have selected TiN and TaN films as metal gate candidates. A comparative investigation is performed using two IPD materials: Al2O3 and HfO2 (and their combinations); IPD equivalent-oxide-thickness is targeted to be below 7 nm. The stacks are then submitted to annealing treatments performed at 500-1000 °C for 1 min in N2. The samples are characterized by gravimetric techniques, XRD, SEM, EDS-TEM and capacitance-voltage measurements. The results obtained on blanket layers are compared to integrated capacitor structures. The impact of the stack microstructure on device performance is discussed based on crystallization behavior of the thin films involved, oxygen composition and diffusion and IPD-metal reactions. Initial results show that the metal nitrides play a minor role in determining the crystallinity of the IPD layers. As expected, the crystallite sizes of the polycrystalline dielectrics are mainly influenced by the layer thickness and temperature used for the annealing. Furthermore, during high temperature annealing, oxygen diffuses from the IPD toward the metal gate. In the particular case of Al2O3, we found that the amount of oxygen into TiN is larger as compared to TaN. This higher oxygen content in TaN is also accompanied by intermixing at the TaN-Al2O3 interface, which is not observed for the case of TiN. The intermixing may be driven by a crystallographic transition occurring in TaN, which changes from cubic to cubic-hexagonal at ~1000 °C. Interestingly, the electrical evaluation of the Al2O3-based HFG devices showed that the program/erase window is larger for TiN as compared to TaN. This observation seems to indicate that the stability of the IPD-metal interfaces plays a more important role as compared to the presence of oxygen in the metal gate. The results aforementioned show that, similar to the case of metal gate/high k in CMOS, it is critical that the poly-Si\metal\dielectric HFG stack remains thermally stable and a detailed characterization of the evolution of the stack microstructure as a function of the annealing conditions is thus necessary to understand the HFG device performance. 1.P. Blomme et al, 2010 VLSI Techn. Symp. Proc., pp129. 2.M. Rosmeulen, US Patent 906,806 B2 3.P. Blomme et al, submitted to IEEE Electron Dev. Lett.

Charge trap memory (CTM) is widely studied as a candidate of the next generation of nonvolatile memory for its significant advantages such as localized charge storage and coupling-free structure, which is particularly important for 3D applications. Silicon nitride has been characterized as typical charge storage medium for CTM, however, to achieve larger memory windows under low program/erase (P/E) voltages, many high-k materials with small equivalent nitride thickness (ENT) such as HfO2, ZrO2 and Al2O3 are introduced as the charge trapping layer. Meanwhile, bandgap engineering of multi-layers structures like Si3N4/Al2O3/Si3N4, and Si3N4/SiON/Si3N4 has attracted attentions as an effective strategy to achieve fast P/E speed along with good retention. Although many charge trapping structures are demonstrated to improve the performance and reliability, there are few works to directly investigate the charge trapping and loss characteristics for high-k materials and structures, which will provide insights into fundamental assessment and optimization for charge trapping structures in CTM. In this work, we employ electrostatic force microscopy (EFM) to study the charge trapping and loss characteristics after injection at 12 MV/cm electrical field. The total charge densities in HfO2 and Al2O3 single layer are extracted from the measured contact potential differences (CPDs), which directly shows the charge trapping capabilities. It also proves that the interfaces provide dominate trap sites in trapping structures. Based on these findings, we demonstrate the HfO2/Al2O3 bi-layers trapping structure with improved performance by introducing the extra interfaces. Then the optimal structure is applied in CTM device with multi-layers structure of HfO2/Al2O3/HfO2 (HAH). By varying the position of inserted Al2O3 layer, The P/E speed and retention characteristics can be optimized, which based on the modulation of trapped charge distribution in the bandgap engineered HAH trapping structures. The HAH 5/2/5 nm device exhibits optimum performance of scaled 5 nm ENT, 10-year extrapolated retention window of 6.3 V and 105 times endurance at 0.5 ms and ±12 V P/E voltages, which is promising in Multi-level Cell memory applications. This study demonstrates a guide for fundamental assessment and further optimization of charge trapping materials and structures in CTM.

Low power consumption, improved data retention period and faster operation are the merits demanded by modern flash technology. Nonvolatile flash memory devices with discrete charge-trap mediums are used as an attractive alternative to conventional floating gate technology. Currently, silicon-oxide-nitride-oxide-silicon (SONOS) type flash memory structure utilizing silicon nitride as a charge storage medium is a promising material system due to its scalability, simple fabrication and enhanced endurance. High-k dielectrics are also of interest for use in charge-trap devices as tunnel oxide and control oxide since they improve scaling without data retention degradation. The application of graphene in non-volatile technology as a charge-storage medium has several advantages due to its appropriate work function. In this study, our aim is to compare the charge storage performance of graphene sheets with those of Silicon nitride layer in flash memory applications. We fabricated and characterized the memory effect of Al/Al2O3/Graphene sheets/HfO2/p-Si structure utilizing capacitance-voltage measurements. Based on modified Hummerâ?Ts method, graphene oxide sheets were derived from the acid exfoliation of graphite and spin-coated to tunnel oxide layer. Graphene sheets were obtained by thermally annealing the device and were examined with atomic force microscopy. HfO2 high-K dielectric layers are used as the tunnel oxide and Al2O3 as the control oxide, all were deposited by atomic layer deposition. For comparing the effect of graphene as a charge-trap layer on the memory device performance, we also fabricated identical memory cells with Si-nitride layer replacing graphene as the charge-trap medium. Si-nitride films were deposited with high SiH4/NH3 gas flow ratio by plasma enhanced chemical vapour deposition. Graphene flash memory exhibits memory window of ~2V at sweeping range of ± 4V. Dynamic program operation also demonstrates an increase in memory window for graphene for a write-pulse durations around 100 ns, which we attribute to novel effects related to oxygen binding. Graphene flash memory device was observed to offer enhanced retention characteristics compared to Si-nitride based non-volatile memories (as much as two orders of magnitude for similar device geometry). Application of graphene as a storage layer improves existing flash technology and satisfies the requirements such as scalability, low operating voltage, faster write performance, at least 10-year retention and CMOS-compatible fabrication.

As the demands of NAND flash to mobile device and SSD application grows, the number of stacked chips in a MCP (Mutil Chip Package) is rapidly increased, which results in large mechanical stress on NAND cell because of the warpage in thinner wafer. In this work, we have investigated the relationship between wafer warpage and reliability characteristics in NAND flash. Experimental data show that as compressive stress increases, P/E cycling and retention characteristics deteriorate. We will address how the wafer warpage affects the P/E cycling and retention characteristics in NAND flash.

Nanocrystalline (nc)-Si memory devices manifest low power consumption, fast programming/erasing speed, long retention time and superior endurance with non-destructive read, because (1) the Coulomb blockade and quantum confinement effect enable one single-electron transport. Few or even one single electron can guarantee a reliable memory state. (2) Electron charge/discharge through an ultrathin tunneling SiO2 film is dominated by the nc-Si dot. (3) A repulsive â?obuilt-inâ? electric field, created and controlled by the charge loss in the nc-Si dots, from nc-Si dots to silicon substrate may give rise to a long-term retention. (4) Programming and erasing in the direct tunnel regime and discrete nc-Si dots provide a high tolerance. The improved retention time has been demonstrated by consuming negligible erasing time in the multiple memory nodes. A smaller charge-loss rate than that of single layered nc-Si dots has been experimentally demonstrated. Charge storage in a surface nitride nc-Si dot is identified by two states: delocalized states in the entire nc-Si dot and localized states in the defects at the nc-Si/silicon-nitride interface. The former provides the fast programming and the latter enables the long-term retention.

Recent advancements in solid state technology have shown confidence that SSDs will be mainstream applications for the replacement of hard-disk drives. However, the endurance of NAND chips used for SSDs is limited because of irreparable damage to the floating gate cells. This phenomenon has been accelerated as the technology node is scaled down. There are many researches for enhancing reliability such as high-k dielectric engineering, plasma nitridation (PN), doping concentration control, and et al.. Among them, PN treatment on IPDs is performed and electrical properties of IPD layers are introduced for improving the reliabillity of NAND cells in this work. 2x-nm NAND flash memory devices are fabricated with various nitrogen concentrations during PN treatment and some samples are omitted PN process for comparisons. Current versus time curves of the samples are measured to confirm the effects of PN treatment. Before program/erase cycles, normalized current of the sample with high N concentration is decreased more and faster than that one of the control sample. This phenomenon is also occurred the comparison of the sample with lower N concentration and the control sample. The differences for current decays are originated from the trap sites generated with PN treatment. After P/E cycles, the normalized current of the sample with higher N concentration is reduced, compared with lower and control samples. After baking, Vth shift of the sample with higher N concentration is decreased less than the control sample. In this work, we suggest the current versus time measurement to investigate the effect of PN treatment. The enhanced PN treatment can improve the retention characteristic over 10%, compared with the control sample.

The p-n-p or n-p-n bipolar memory structure based on wide band-gap materials can achieve high speed (as fast as ns), low operation voltage and long retention time (million years) and therefore has great potential in the future memory application. Till now, the reports on this kind of memory are mainly based on SiC. Compared to SiC, ZnO has a larger bandgap of 3.37 eV and can be synthesized using low-temperature epitaxial growth method. In this study, we report an Sb-ZnO/ZnO/Sb-ZnO p-n-p memory structure on c-plane sapphire substrate. P-n-p memory structure with Sb-doped p-type ZnO and undoped n-type ZnO layers was grown on c-plane sapphire substrate by plasma-assisted molecular-beam epitaxy and fabricated using standard photolithography and lift-off process. I-V measurement showed good rectification behavior between p-type layer and n-type layer. Capacitance-voltage measurements demonstrated the memory effect of the p-n-p structure. The program characteristics and retention characteristics were studied and the results indicate that low operation voltage and long retention can be achieved in the ZnO p-n-p memory structure, which may be a viable candidate for the next generation nonvolatile memory.

Charge trapping (CT) memories, in which the information storage takes place by the trapping of charges into discrete traps inside a dielectric layer (typically Si3N4), are considered as promising candidate to extend the scalability of Flash memories towards 16 nm technology nodes and in 3D architectures. Despite promising results have been obtained with the TaN/Al2O3/Si3N4/SiO2/Si (TANOS) CT cell, new solutions such as engineered stacks and alternative materials are required to improve the cell performance. In this work, we propose Al-HfO2 (with κ = 30) as CT layer in a TaN/Al2O3/Al-HfO2/SiO2/Si (TAAHOS) cell, to achieve either an overall EOT scaling of the stack or to use a thicker oxide for the same Si3N4-EOT to improve retention. Al-HfO2/Al2O3 bilayer is grown on 4.5 nm SiO2/Si substrate by atomic layer deposition at 300 °C using (MeCp)2Hf(Me)(OMe), TMA and O3 as Hf, Al and oxygen precursors, respectively. Post deposition annealing of the stack is performed at 900-1030 °C. GIXRD measurements show that as deposited films are amorphous; after annealing Al-HfO2 layer is crystallized in a mixture of cubic and tetragonal phases, while the monoclinic phase is not detected, differently from the case of pure HfO2 [1]. Capacitance-voltage measurements evidence an increase in Al-HfO2 κ value from 20 to 30 upon annealing, consistently with the detected crystallographic phases. ToF-SIMS depth profiles reveal a rather well preserved thermal stability of the structure for annealing temperature of 900 °C, whereas at higher temperatures diffusion takes place. The memory performance of TAAHOS capacitors are studied as a function of Al-HfO2 thickness in the 7-22 nm range. The obtained results evidence that by varying the stack parameters (thickness, annealing temperature) and/or programming conditions it is possible to achieve large memory windows, of interest for multilevel programming, low power operations or fast programming speed. In stack including 22 nm thick Al-HfO2, very large memory windows (~ 14 V) are achieved at high applied voltages and long pulse times, whereas the charge loss at room temperature is only 6% after 106 s. Scaling of the CT layer down to 12 nm has a poor impact on retention, while reasonable Î"VFB ~5 V could be achieved for low voltages (i.e. 14 V, 12 V, pulse time of 100 ms) as well as by fast operation (Î"VFB ~5V at 20V, 10 µs). The performance of Al-HfO2 as CT layer in the TAAHOS cell is also compared to other high-κ oxides (i.e. HfO2, ZrO2 [2], and Al-ZrO2) and to a reference TANOS cell. Our results support the interest in high-κ oxides such as Al-HfO2 for high performance, low power and high reliability applications of CT Flash memory devices for future technology nodes. Financial support by the FP7 European project GOSSAMER (Contract No. 214431). [1] S. Spiga et al., Proc. ESSDERC 2010, 408 [2] G. Congedo et al., Microelectr. Eng. 88, 1174 (2011)

Memory functions are critical to all semiconductor products. High-k dielectrics are necessary not only to the advanced MOSFETs but also to memories, such as the ONO or floating gate, the resistive switching, the DRAM, and the SRAM devices. The nanocrystals embedded high-k structure has been demonstrated to be an effective gate dielectric for the high performance nonvolatile memory, e.g., a large memory window, a long charge retention time, and a low operation power. The memory function of this kind of device is dependent on the composing nanocrystalline material and gate bias voltage and polarity. Either electrons or holes can be trapped and detrapped in various devices. In this paper, authors present the result on a new molybdenum oxide embedded high-k memory device that shows unique characteristics of hole trapping, charge retention after breakdown, and light sensitivity to various lights. Material properties of this device will also be discussed. In summary, this is a potentially important memory device for future IC products. This work is supported by NSF CMMI 0926379 and 0926420 projects.