RF-MEMS tunable capacitors are suitable for tunable components of multiband/multimode mobile handsets because of their low loss and excellent linearity [1]. In order to use the RF-MEMS tunable capacitor in a mobile system, a high power-handling is needed. The RF-MEMS tunable capacitors have an issue of creep-induced deformation. The creep is caused by a ductile metal like aluminum alloy which is indispensable to attain the low loss. From this point of view, we have developed an RF-MEMS tunable capacitor that has compatibility of CMOS device integration processes and achieved high power-handling capability and excellent creep immunity. The tunable capacitor has a quadruple series capacitor (QSC) structure, which consists of two MEMS capacitor elements and two fixed metal-insulator-metal (MIM) capacitors connected in series between input and output terminals [2]. The QSC structure drastically improves the power-handling, since the voltage applied by RF signals can be reduced at the each MEMS element. We fabricated a digitally tunable capacitor bank that consisted of the eight QSC structure elements. The capacitance of the bank changes widely from 1.9pF to 5.5pF at 1GHz. The quality factor is good in 114 and 80 for the minimum and maximum capacitance, respectively. Next, an RF power handling characteristic was evaluated by measuring the pull-out voltage dependence on the input RF power. The result shows that the fabricated tunable capacitor bank can handle the RF signal up to +36dBm under the hot-switching conditions at even 85°C. The springs that support the top electrode of each MEMS capacitor element were formed by a silicon nitride (SiN) dielectric material [2, 3]. We examined simply parallel plate actuators to analyze the creep of springs and saw that the creep-induced deformation was reduced drastically by forming the SiN springs instead of aluminum springs. The creep deformation of the actuator with SiN springs was drastically reduced by one twenty-third at 85°C, compared to aluminum springs. We also carried out a cycle test for the actuator with SiN springs and observed no failures up to 10⁹ cycles at 25°C. We demonstrated an RF-MEMS tunable capacitor using a quadruple series capacitance structure with SiN springs. The excellent quality factor was achieved at the large capacitance owing to the low loss structure. The proposed RF-MEMS tunable capacitor is also shown to have high power-handling and good long-term creep immunity properties. References: [1] G. M. Rebeiz, RF MEMS: Theory, Design, and Technology, Wiley Interscience, 2003. [2] H. Yamazaki et al, â?oAn RF-MEMS Tunable Capacitor Using Quadruple Series Capacitor Structure and Brittle Material Springsâ?, Proc. of ADMETA 2010: 20th Asian Session, pp.80-81. [3] E. Ogawa et al, â?oA LONG-TERM RELIABILITY ANALYSIS OF A CREEP-IMMUNE RF-MEMS TUNABLE CAPACITORâ?, Proc. of Transducers 2011, pp. 2466-2468.

After decades of rapid increase, clock speeds of computers plateaued in 2003 due to the breakdown of Dennard's constant-electric-field scaling rules. The basic physics of CMOS field effect transistor (FET) operation, controlling current low via the imposition of a (electrical) potential barrier, is at the root of the problem which cannot then be overcome by engineering methods, alone. In order to respond to the challenge posed by clock speed plateau, it is necessary to embody novel physical principles in new designs. Inspired by the power of piezoelectrically driven MEMS switches, a new device, the Piezoelectronic Transistor (PET) is proposed. The PET utilizes a high response relaxor piezoelectric material to mechanically compress a correspondingly high response piezoresistive material upon receipt of an input voltage signal. The piezoresist then undergoes a pressure driven continuous metal insulator transition (MIT). The MIT, in one instance an intermediate valence transition, opens a channel for current flow. In this talk, it will be shown how the physics and materials science underlying the PET's elecromechanical operation coupled to its geometric design can circumvent the limitations of the FET. The result is a fast (~5GHz), low voltage (~0.1V) switch that consumes ~100x less power than CMOS. We emphasize that the properties of known materials are sufficient to realize the PET via theoretical analysis and simulation and present the 1st experimental demonstrations of critical components of the PET device. The project is funded through DARPA's MESO II program.

1. Previous Attempts Many research groups have tried to integrate ferromagnetic-based inductors into CMOS chips. Using ferromagnetic material has the following advantages: increased inductor reactance at low frequency, increased coupling of transformers and reduced fringe fields of all magnetic components. Reduced fringe fields allow an increase in the level of integration for system-on-chip schemes. But ferromagnetic material is not easy to integrate in CMOS chips. The main problem is the extreme thinness of the portion of CMOS chips that is usable for magnetic circuits (oxide-metal stack on top of the CMOS). With a typical stack thickness of 5um and flat coil geometry, 1 mm inductor will result in an aspect ratio of 200:1. Attempts to use the backside of the CMOS chip for the magnetic circuits were largely thwarted by the losses in the silicon between the metal coil and ferromagnetic layer. The silicon eddy current loss also significantly degraded performance of designs where the metal coil was sandwiched between two ferromagnetic layers within the metal-oxide stack of the CMOS, Furthermore, materials suitable for well-controlled deposition on the CMOS chip are very few. Therefore, no single material was satisfactory in terms of the magnetic permeability, hysteresis and eddy current losses. 2. Concept Description The main concept for the current research was the design of the ferromagnetic integration strategy into CMOS, being free from the disadvantages of the previous attempts. To do this, multiple criteria listed below must satisfied: a) Deposited materialâ?Ts thickness must be well controlled and small in order to not hamper flip-chip assembly. b) Deposited materials must be non-magnetic in bulk form (to facilitate RF sputtering, a precise deposition method) but must form a ferromagnetic layer on top of the chip. Materials satisfying this criterion were Fe-Co-Si-B alloy and ZnFe2O4. c) There must be no silicon around the magnetic circuits. In the proposed design, silicon is back-etched under the inductor. d) Magnetic components must produce a closed magnetic circuit and must be immune to delamination. To satisfy this criterion, same layers of ferromagnetic material were deposited on the top and bottom of the metal-oxide stack. e) The tradeoff between permeability and eddy currents must be easily controlled to satisfy the application requirements. To do this, a multilayer composite of Fe-Co-Si-B and ZnFe2O4 was used. f) The ferromagnetic materials must be compatible with CMOS post-processing techniques. This means the ferromagnetic must resist handling stress, and processing must be done at low temperatures. 3. Results Achieved Inductors with under-etched silicon, up to 8 ferromagnetic layers, and metal coil diameters around 0.8mm wide were fabricated. The peak quality factor increased from 8 to 11. The low-frequency inductance increased from 41.5nH to 67.0nH, and low-frequency quality factor increased from 0.6 to 5.1.

Since a few years, aluminum nitride (AlN) thin films have become a standard material for RF filters in mobile phones. It is mostly used in duplex filters working around 2 GHz composed of thin film bulk acoustic wave resonators (TFBAR) connected in ladder type circuits. Pure AlN thin films were found to have maximal d_33,f piezoelectric coefficients of 5.3 pm/V. The coupling coefficients of TFBARâ?Ts amounts to maximally k²=6.5 % considering standard materials parameters. Such a value is sufficient for covering the needs of current filter requirements for mobile phones. However, there are other filters types and applications that would require larger coupling factors in order to achieve larger bandwidths. Recently it was shown that Al substitution by Sc allows for an increase of the piezoelectric response. We prepared polycrystalline (001)-textured Al_0.88Sc_0.12N thin films by reactive, pulsed, direct current magnetron sputtering to measure all relevant properties for TFABR resonators. The target was a 200 mm diameter, 6 mm thick plate of an Al_0.9Sc_0.1 alloy of 99.9% purity and exact composition Al/Sc of 89.76 at. %/10.23 at. %. Selected area electron diffraction calibrated with the XRD (002) peak yielded a and c lattice parameters of 3.11 and 5.01 Ã., respectively. The c/a ratio decreased to 1.575 from 1.601 of pure AlN. The unit cell volume increased by 5%. Energy dispersive analysis of x-ray emission in the TEM revealed that 12 at. % of Al atoms were substituted by Sc, indicating a higher sputter or transfer yield for Sc. The microstructure of the films as investigated by means of TEM is very close to the known picture of fiber type T-zone growth of good AlN thin films for TFBARâ?Ts. The clamped piezoelectric coefficient d_33,f as measured by double side interferometry increases to 7.7 to 8.0 pm/V. TFBAR resonators with fundamental resonance at 2.2 GHz have been fabricated and characterized. The sound velocity in AlScN was derived by means of 2D finite element modeling of the layer stack, allowing for discrimination of loading effects by the electrodes. The value of 10â?T300 m/s is clearly lower than in pure AlN (11â?T000 m/s). A parasitic resistance was taken into consideration through application of an equivalent circuit model. As a result of these procedures we obtained k² to 11 % and Q factor of 400 for the complete resonator, furthermore a dielectric constant of 12.5, and a dielectric loss tangent of 0.5% (both @2.2 GHz). The stiffness constants c^D₃₃ and c^E₃₃ were derived as 345 and 320 GPa. The resonance frequency temperature drift of 26.1 ppm/K was found to be about the same as for pure AlN. The evolution of piezoelectric constant e₃₃, the dielectric constant, and the stiffness constant were found to be close to the values predicted by ab-inito calculations.

This paper presents 3D heterogeneous integrations for RF applications. A miniaturized duplexer and a MEMS tunable filter, combining the advantages of LTCC, passive integration and MEMS technologies, were constructed to demonstrate its feasibility and effectiveness. Frequency property influence in the 3D integration of a PZT actuated MEMS switch using a single crystal silicon asymmetric beam is studied. A duplexer module has been constructed using 3D heterogeneous integration method. The duplexer consists of a film bulk acoustic resonator (FBAR) transmission (Tx) filter, a single-to-balanced double mode SAW (DMS) receiver (Rx) filter, and notch and matching circuits. Part of the notch and matching circuits were built inside the LTCC wafer and the rest were directly formed on the LTCC wafer surface. The SAW and FBAR filter are mounted above passive circuits formed on the surface of LTCC wafer. The fabricated module measures a compact 2 mm x 2.5 mm x 0.55mm. A low insertion loss of less than 1.7 dB has been achieved in either Tx or Rx band. Resistive vias builted inside the LTCC wafer were used to isolate the RF signal from DC driving line in a MEMS-varactor-based tunable filter. The movable upper electrode and DC driving electrodes of the MEMS varactors are connected to DC driving pads through inner resistive vias and inner wiring. These built-in resistive vias are placed directly under the MEMS without occupying any surface area. The insertion loss of the MEMS tunable filters is improved from -6.8dB to -2.3dB thanks to the integrated resistive vias blocking RF leakage into the DC driving path. Our metal-to-metal contact RF-MEMS switch has a single crystal silicon (SCS) fixed-fixed beam, on which a PZT unimorph actuator and a bottom RF signal electrode are patterned. The beam is separated from the fixed part by a slit. A bridge-shaped top RF signal line is formed above the beam by electroplating with narrow air-gap. An RF-ground surrounds the switch to improve impedance matching. The fixed beam is designed in an asymmetric shape, and in order to reduce actuation voltage, the portion with the bottom electrode is narrower and longer than the other portion with the PZT actuator. Our beam was very stiff (>2,000 N/m of spring constant) in order to reduce undesirable deflection. Measured performance of the insertion loss was 0.2 dB up to 2GHz, and 0.3 dB up to 5GHz. The isolation was -33 dB up to 2GHz, and -25 dB up to 5 GHz. The main factor of the insertion loss is the resistance of the sputtered bottom signal line which is 0.9 ohmï? . Simulation of the frequency property influence of 3D integration was carried out with the RF MEMS switch with a ground plane placed over it. The ground plane is used as a worst case coupling effect of the control IC, which has a wide metal layer built in. Isolation and insertion loss was simulated with a parameter of distance between the RF MEMS switch and the ground plane.

This presentation will give an overview of Micro-Electro-Mechanical Systems (MEMS) and Nano-Electro-Mechanical Systems (NEMS) application to hard-disk drives (HDDs). Examples will include: Magnetic head (thermal actuator for thermal fly-height control, thermal sensor for head-disk contact detection), tracking-servo micro-actuators (suspension based, moving-slider, and moving element), acceleration sensor for vibration feed-forward, Bit Patterned Recording (nano-fabrication of master pattern, nano-imprint), and Heat-Assisted Magnetic Recording (near-field transducer).

Future ubiquitous wireless sensor networks will require small and thin autonomous sensor nodes, which contain a radio, power manager, transducers, and energy harvesters. To realize an autonomous operation of the sensor node, nanowatt-level power management circuit has been developed. The circuit required the energy harvester to be within millimeter-size, and generate at least nanoampre-level current. For this purpose, we have proposed a vibrational MEMS energy harvester with slit-and-slider electrodes and electret, and the current of 0.17 nA has been generated. However, the generated current was not sufficient to operate even the power management circuit because it was one-order lower than the required one. Therefore, it is important to boost the current in the limited millimeter-sized structure. This can be done by improving charge in electret. Another approach, which we undertook here, is to change of the structural parameters. In this work, we focused on the gap between the slit-and-slider electrodes in the energy conversion region as the structural parameter. The point is to achieve a large variable capacitance change between the electrodes. We fabricated a millimeter-sized MEMS vibrational energy harvester by bonding the slit electrode chip with the slider electrode chip while narrowing the gap between the slit-and-slider electrodes. We prepared bonded devices with gaps of 5, 15, and 30 μm. To evaluate the effect of narrowing the gap between the electrodes, we measured electromechanical characteristics. Under a bias voltage, which induces electric charge between the electrodes, the devices were vibrated by a shaker in the direction parallel to the devices. When the external vibration is applied to the device, the movable slider plate suspended by springs is displaced. Corresponding to the displacement, the capacitance between the electrodes is varied, which induces a current on the load resistor in a lock-in amplifier. The acceleration of the stage and the bias voltage were set to two meter per second squared and 30 V, respectively. For the gaps of 5, 15, and 30 μm, the currents of 0.37, 1.09, and 1.62 nA were obtained. The current was inversely proportional to the square of the gap, which corresponds to the fomula for a capacitance with a fringe effect. We confirmed nanoampere-level current generation with the external bias voltage, which corresponds to a charged electret. The current of the 5-μm gap is about more than 10 times larger than that for the 30-μm gap, indicating that the generated output power is dramatically increased by narrowing the gap. This result shows that narrowing the gap increases the generated output power effectively in the millimeter-size vibrational MEMS energy harvester, which will contribute to the development of energy sources for sensor nodes.

The use of nanomaterials for sensor applications has been widely explored in the past since they provide higher sensitivity as well as lower detection limits as compared to their bulk or thick film counterparts. In general, enhanced sensor responses in nanomaterial-based gas sensors are attributed to the high surface-to-volume ratio of nanomaterials. However, the detailed impact of various size effects, including the role of quantum confinement in determining the sensor response is still not well established. Here, we explore the quantum size effects on the sensing performance of the ultrathin InAs membranes gas sensor. For this study, we employed layer-transferred InAs ultrathin films on SiO2/Si substrates, resulting in InAs-on-insulator (XOI) structure. The top surfaces of three different InAs thicknesses (8, 18, 48 nm) were functionalized with Pd nanoparticles to enable H2 sensing. InAs is an ideal material platform for exploring the quantum size effects given its large Bohr radius of ~35 nm, which results in the population of only one 2-D subband at room temperature for sub-10 nm thicknesses. Using these sensor devices, we experimentally and theoretically examined the role of InAs thickness scaling on the gas sensor response. We observed substantially improved sensor responses as the InAs thickness scales down. The role of the InAs thickness scaling on sensor performance is two-fold. First, electrostatic control of carrier concentrations by Pd-functionalized surface reaction with H2 is enhanced with the thickness scaling. More importantly, quantization effects, clearly observed in the ultrathin InAs membrane, significantly alter the electron mobility of the sensor device and cause drastic change in currents upon H2 exposure, resulting in high sensor responses. The latter is due to the enhanced surface scattering rates of electrons in quantum confined membranes which make them more susceptible to surface phenomena. The work here presents a new insight into the role of carrier quantization in the response of sensor devices with important practical implications.

This paper reports a NEMS (Nano Electro Mechanical Syetems) tunable color filter based on subwavelength grating with high color uniformity and low drive voltage. The developed tunable color filter was demonstrated a structural color change at drive voltage of 6.7 V. MEMS tunable color filters based on subwavelength grating are expected to have high diffraction efficiency and wavelength selectivity [1]. We have previously developed a NEMS tunable color filter that consists of an array of parallel-plate actuators with a nano gap, which was demonstrated a structural color change at drive voltage of 20 V [2]. Monolithic integration process with MOS driver circuit has been reported in Transducers â?T11 [3]. However, each actuator placed with the nano gap had a crosstalk of an electrostatic attraction force, which made non-uniformity color and relatively high drive voltage. For improving the uniformity and decreasing the drive voltage, we newly propose a GVG (Ground-Voltage-Ground) type NEMS tunable color filter deployed with an array of a parallel-plate actuator with three pairs of electrode. The electrostatic parallel-plate actuator for the color filter is formed from three silicon beams. A fixed electrode is located in the middle, and movable electrodes are set on either side. A drive voltage and ground level are provided to the fixed middle electrode and movable electrodes, respectively. The pitch of the subwavelength grating is changed due to the electrostatic force. Movable electrodes are attracted to the middle fixed electrode without any crosstalk. In an analytical model for FEM (Finite Element Method), we design the subwavelength grating to be 220 nm wide, 380 nm gap and 30 microns long and 150 nm thick. The suspension is set to 10 microns long and 150 nm wide. The pull-in voltage is found at 4 V. In addition, the simulation result is depicted that the GVG structure provides a uniform displacement in arrayed actuators, which produces uniform color in whole filter area. The fabricated tunable filter was 30 µmÃ-30 µm in area, which is configured by a 25 pairs of parallel-plate actuators. The grating beam was 240 nm wide, 150 nm thick, and 30 microns long with the gap of 260 nm. The suspension dimensions were 10 µm long and 200 nm wide. The color filter was measured by a spectrometer. The experimentally shifted color is plotted on the CIE chromaticity chart, (x,y)=(0.348, 0.467) at initial position and (0.325, 0.449) at 6.7 V. The color uniformity was also obtained in the filter area. In conclusion, the GVG type NEMS tunable color filter is possible to operate by standard CMOS-LSI circuit. The tunable color filter reported here is expected to develop a new display application. [1] K. Hane, et al., Applied Physics Letters, Vol. 88, p.141109 (2006) [2] H. Miyao, et al., 219th ECS meeting, 1-6 May, 2011, Montreal, Canada, pp. 213-218. [3] H. Honma, et al., Proc. TRANSDUCERS â?T11, 5-9 June, 2011, Beijing, China, pp. 2928-2931.

MEMS (Micro Electro Mechanical Systems) as switches and filters fabricated on LSI are required for multi-band wireless systems, in which good mechanical properties are required for the MEMS and small feature size for the LSI. Such MEMS on LSI can be implemented by following three methods. The first method is a surface micromachining and AlN Lamb wave resonators are fabricated for on-chip multi-frequency oscillators. The second method is a MEMS fabrication after wafer adhesive bonding on a LSI wafer. MEMS micromechanical resonators and FBAR (Film Bulk Acoustic Resonator) are fabricated using AlN. The third method is a bonding of MEMS wafer to LSI wafer. SAW (Surface Acoustic Wave) filter is fabricated on a LSI. This method does not require the damage-free MEMS fabrication to LSI, however the density of MEMS is limited and stray capacitance is increased because of the bonding pads. The MEMS should be encapsulated on a wafer because the moving MEMS are damaged by a direct plastic molding. Wafer level packaging has been developed for this purpose. LTCC (Low Temperature Co-fired Ceramics) which have electrical feedthrough for interconnections has been developed. Owing to the matched thermal expansion of the LTCC with that of the Si the LTCC can be anodically bonded to the MEMS-on-Si wafer for the purpose of the wafer level packaging.

Integrated Circuits and MEMS self powering needs are currently growing. For ultra low power devices and embedded applications that require ultra-lightweight systems with small footprints and autonomous operation, the primary energy source is typically a battery, that is substantially larger than the system it powers. The thin, flexible and low cost nature of polymer electronics can enable electronic integration, with no system area overhead, where more expensive, rigid and brittle silicon-based counterparts are no longer compatible. In this work we present recent advancements in the development of ultra-stable polymer solar cells (PSCs) and ionic-polymer based hybrid energy storage (PES) devices capable of storing harvested solar energy in a low cost thin-film stack. Such a solution offers novel areas of flexibility in terms of voltage configuration and packaging for instance. The design, architecture and fabrication of a fully integrated energy harvesting system for powering integrated circuits is discussed and demonstrated.

Recently, bacterial infections have become a serious social problem, such as an outbreak of E.-coli.-O104 infection in Europe this year. To avoid such outbreak or to find methods for treatment, the knowledge about bacterial behavior is very important. To investigate the nature of bacteria, series of trial and error testing varying experimental conditions such as temperatures, pH, etc. in vitro have been performed. These experiments take time and many efforts of researchers. The device that enables us to know the nature and the behavior of bacteria at a time is desired. Applying micro-fluidic channels and chambers made with Bio-Micro-Electro-Mechanical Systems (Bio-MEMS) has successfully shown to be effective way to observe the structural-dependent behavior of bacteria such as E.-coli. [1]. Bio-MEMS devices having functions for controlling the chamber conditions on a chip are further expected for observing bacterial behavior. We propose a Bio-MEMS device having the micro chambers that operate as test tubes, by which we can observe bacterial behavior under various conditions at a time on a chip. When the bacteria are inserted into the inlet chamber that is connected to the micro chambers through micro-fluidic channels, we can recognize which conditions bacteria favor by observing which chamber they head for. This work mainly focuses on the fabrication of the chip for observing the temperature-dependent behavior of bacteria, as a prototype of such Bio-MEMS devices. The chip of the device consists of two stacked Si layers. The upper layer of the chip has five chambers: The one is for the inlet of the bacteria and the other four are the target chambers for bacteria, which are placed around the inlet chamber via micro-fluidic channels. The chambers and channels are filled with liquid in which bacteria move by sensing temperature gradient between the inlet and target chambers. The lower layer of the chip has heaters to independently raise the temperature of four target chambers. The upper and lower layers were fabricated separately using 4-inch Si wafers. Protecting fragile MEMS portions such as micro fluidic channels from damages during the fabrication is the key to obtaining the desired device. So, we used the wafer bonding and laser dicing after completing the fabrication processes for each wafer. The structures of the upper layer were fabricated with MEMS processes; a double-sided lithography and a deep reactive ion etching. The resistive heaters of the lower layer were made with poly-Si. Each wafer was bonded together with adhesive fluoropolymer. Then, the laser dicing, or stealth dicing cut the bonded wafer into chips. This completed the fabrication process. Our device enables us to investigate the nature of bacteria under various temperatures. Thus, on-chip testing by the Bio-MEMS device paves the way for investigating the bacterial behavior. [1] Jaan Mannik et al., PNAS, Vol. 106, No. 35, pp. 14861-14866 (2009).

ABSTRACT We developed an optimized inductively coupled plasma (ICP) etching process of V-grooves in GaAs. A statistically-designed experiment was performed to optimize the etching parameters. The resulting parameters are discussed in terms of the effect on the etching rate and profile. This process uses a small amount of mask corrosion and the control of the etching mask gap to give a 45-50 degree V-groove etching profile, which is independent on the crystal orientation of GaAs. The relationship between the gap width and the etching profile, the etching rate is also discussed. In the etching development, scanning electron microscope (SEM) and atomic force microscope (AFM) were used to observe the surface morphology and the pattern profile. In addition, X-ray photoelectron spectroscopy (XPS) and transmission electron microscope (TEM) were utilized to obtain the elemental composition, the contamination, and the damage in the top 10nm of the etching surface. It is found that extremely small stoichiometric change and surface damage of the etching surface can be achieved while keeping relatively high etching rate and ~45 degree V-groove etching profile. This etching process is applied to the fabrication of pyramidal corrugated quantum well infrared photodetector focal plane arrays, which is expected to have better performance than the regular prism-shaped C-QWIPs. The expected results will be verified by optical and electrical measurements. In addition to infrared detectors, this process technology can also be applied to GaAs V-groove solar cell, quantum wire light-emitting diodes, quantum wire lasers, and other GaAsâ?"based devices.

The technological revolution is essential for innovation. With the saturation in miniaturization of microelectronics as well as the maturity of MEMS, now the heterogeneous integration technology combining various fabrication methods is required. We can utilize micromachining, VLSI (very large scale integration) silicon microelectronic technology, compound semi-conductor technology, nano technology, bio technology, organic/inorganic chemistry, printing and molding to create a versatile manufacturing technology. Each technology offers the capability to realize specific functionality in different scales with different materials. This talk deals with the concept towards the heterogeneous integration of devices and functionality into micro/nano systems and the current development trend. The heterogeneous integration technology includes three features: (1) Hetero-scale integration from nanometer to meter scale, (2) Hetero-material integration from bio and organic materials to semiconductors, (3) Hetero-process integration of bottom-up and top-down processes. I will discuss those features, using the examples from my own laboratory and a Government-supported project named BEANS.

The Pixtronix Digital Micro Shutter (DMSâ"¢) display technology provides the lowest power consumption at the best image quality for all mobile multimedia applications. This technology is based on MEMS micro-shutters formed on active TFT backplanes. These MEMS shuttering devices have enabled the development of color sequential, time division gray scale, direct-view displays achieving wide color gamut, high brightness, high contrast ratio and wide view angles, all at roughly ¼ the power consumption of competing TFT-LCD or AMOLED displays of the same size and luminance. This paper explores the design, performance and reliability of the enabling MEMS shuttering element. Features of the design are detailed as they relate to robust performance and manufacture. Pixtronix displays are shown to be manufacturable in existing LCD fabrication lines, significantly reducing time to market and increasing profitability.

Continuous scaling of electronic devices and circuits, increased speed and integration densities resulted in problems with thermal management of advanced computer chips [1]. Further progress in information, communication and energy storage technologies requires more efficient heat removal methods and stimulates the search for thermal interface material (TIMs) with enhanced thermal conductivity. The commonly used TIMs are based on polymers or greases filled with the thermally conductive particles such as silver or silica. The conventional TIMs require high volume fractions of the filler material (up to ~70%) to achieve thermal conductivity of about 1â?"5 W/mK of the composite. Recently, some of us discovered that graphene has extremely high intrinsic thermal conductivity, which exceeds that of CNTs [2-4]. To utilize this property for thermal management applications, we used the inexpensive liquid-phase exfoliated graphene and few-layer graphene (FLG) as filler materials in TIMs. The thermal properties of the obtained graphene-epoxy composites were measured using the â?olaser flashâ? technique. It was found that the thermal conductivity enhancement factor exceeded ~ 2300% at 10% of the graphene/FLG volume loading fraction. This enhancement is larger than anything that has been achieved with other filler materials. The physics-based modeling analysis of thermal properties of TIM composites suggests that graphene can outperform other carbon allotropes and derivatives as the filler. Graphene-based TIMs have a number of other advantages related to their viscosity and adhesion, which meet the industry requirements. Our results suggest that graphene can become excellent filler materials in the next generation of TIMs for the electronic, optoelectronic and photovoltaic solar cell applications [5]. The work in Balandin group was supported, in part, by the SRC â?" DARPA through FCRP Functional Engineered Nano Architectonics (FENA) center and the Winston Chung Global Energy center at UCR. [1] A. A. Balandin, Chill Out: New Materials and Designs Can Keep Chips Cool, IEEE Spectrum, 29, 35 (2009). [2] A. A. Balandin, S. Ghosh, W. Bao, I. Calizo, D. Teweldebrhan, F. Miao&C. N. Lau, Superior Thermal Conductivity of Single-Layer Graphene, Nano Lett. 8, 3, 902 (2008). [3] S. Ghosh, W. Bao, D. L. Nika, S. Subrina, E. P. Pokatilov, C. N. Lau,&A. A. Balandin, Dimensional crossover of thermal transport in few-layer graphene, Nature Mat., 9, 555 (2010). [4] A. A. Balandin, Thermal properties of graphene and nanostructured carbon materials, Nature Mat., 10, 569 (2011). [5] For details visit Balandin group web-site: http://ndl.ee.ucr.edu

The increasingly highly doped, conductive substrates resulting in lossy on-chip passive components is one of the main drawbacks of standard CMOS processes which worsens with moving toward higher frequencies like 60 GHz. Realizing of an on-chip 3-dB quadrature coupler at 60 GHz is impractical due to its large size and hence high loss, though it's a key component in various circuits such as balanced amplifiers and balanced mixers. In this paper for overcoming the problem, we have used WLP (Wafer Level Packaging) technology and proposed a new tandem coupler using offset broadside coupled lines for power combining in 60 GHz band. WLP technology is a promising way for cost saving and integration of high quality passive components with active circuits. Our developed WLP technology has three layers of metal, namely, ground, 1st metal and 2nd metal. Considering that the minimum allowed line space and line width is 15 um and the height of the 2nd metal from the ground is 20 um, some standard 3-dB coupler structures like broadside coupled-line coupler was not a suitable choice for our WLP process. The designed coupler occupies an area of 0.288 square millimeter, has simulated maximum insertion loss of 0.62 dB, a return loss of better than 30 dB, a phase unbalance of better than 0.35 degrees, a gain unbalance of better than 0.09 dB and an isolation better than 35 dB from 57 GHz to 66 GHz. Measured results will be presented in the full paper.

The unprecedented technology advancements in miniaturizing integrated circuits on silicon (SOC) and in integrating systems in a package (SIP) have demonstrated the impact that dimension scaling engineering can have for communication, computing, and consumer electronics. While a silicon manufacturing technology has been applied to constructing various Micro Electro Mechanical System (MEMS) for integrating additional sensing and actuation functions into microelectronics silicon chips, post silicon MEMS chips packaging remains to be very challenging. On the other hand, post semiconductor manufacturing processes (PSM), including packaging and printed circuit board (PCB) technologies with a few micrometer line and space resolution and sub-mil vias are readily achievable. Such PSM technology can be used to manufacture micro electromechanical systems (MEMS) for sensing and actuation applications. A lamination-based manufacturing process allows for a broader selection of materials and fabrication processes than silicon-based manufacturing, and therefore provides greater design freedom for producing functional microdevices. In many cases devices can be fabricated that are more suited to their applications than their silicon counterparts. Furthermore, such microdevices can be built with a high degree of integration, pre-packaged, and at low cost. Indeed, the PCB and packaging industries stand to benefit greatly by expanding their offerings beyond serving the semiconductor industry and developing their own devices and products. This paper illustrates that good quality MEMS devices can be manufactured in laminates, and discusses some of the unique benefits of such devices. This laminate MEMS technology promises for not only manufacturing microdevices but also heterogeneously integrating them with silicon microelectronics into their package with the same manufacturing processes.

An ultra-small tactile sensor with the functions of signal processing and digital communication has been prototyped by using MEMS-CMOS integration technology. The designed analog-digital mixed ASIC allows many tactile sensors to connect a common bus line, which drastically reduces the number of wire. The wafer-level integration and packaging technology realizes a chip-size-package (CSP) with small footprint (2.5mmÃ-2.5mm) and low profile (0.27mm), which is convenient for surface mounting on a curved robot body. The MEMS structure and the ASIC are stacked at wafer level, and the I/O pads which are sealed at bonding interface are connected to the backside of the tactile sensor using novel through-silicon-vias (TSV). The TSV are made in tapered grooves, which are sawed using a dicing blade. Finally, the integrated tactile sensor was tested, and the digital data which was fired autonomously like a tactile receptor of human was observed. In recent year, the tactile sensor which can be densely distributed on relatively large area (1~2m2) is needed for humanoid robots. However, the wiring and data processing become critical issues as the number of tactile sensor increases. The integration of a MEMS tactile sensor with ASIC solves the issues by digital communication and data processing function. Digital communication enables the mounting of many sensors on a common few-wires cable, which is drastically reduces the number of wire. ID number, sensing data and CRC (Cyclic Redundancy Check) are contained in the digital output data to distinguish the digital data on the common cable. The sensing part stacked on the ASIC is a Si diaphragm capacitive force sensor, which also works as a grounded sealing for the ASIC surface. To achieve surface mounting, the electrical feeding-through of the I/O pads from the bonding interface to the backside is necessary. In contrast to standard TSV technology, which uses deep-reactive-ion-etched holes, we used tapered grooves fabricated by mechanical dicing with a V-shape blade. 55 degree tapered and 70μm deep grooves are fabricated around the ASIC chip area. The grooves are insulated by PECVD. Then, redistributed electrodes from the I/O pad are extended to the bottom of the grooves, and the grooves are filled by benzocyclobutene (BCB). After the wafer bonding between the Si sensing structure (200μm thick) and the ASIC (780μm thick), the filled grooves are exposed by back-grinding the ASIC wafer. The exposed pads are redistributed again and forms LGA (land grid array) type electrodes. The developed integration and packaging technology is applicable to standard CMOS, versatile and low cost. After the fabrication, the tactile sensor was tested. The yield of the electrical feed-through is 100% (160pin/160pin). 80bit long digital data, which were autonomously fired every second, was observed. The sensing data without force stimulus shows a sensor capacitance of 1.7pF, which roughly agree with the designed value.

In recent years, there have appeared serious problems concerning the relative increase in the aged population and the reduction in the working population in many countries. Therefore, care of the aged and automation in manufacturing have become very important in solving these problems, and human-support robots with skillful performance have attracted much attention. In order to produce the skillful and dexterous robot, excellent sensors are required to detect condition of the object and especially tactile sensor is much valuable for holding the object in the nurse care and the automation. We have developed the tactile sensor using the microcantilevers with gauge film, fabricated by MEMS technologies and embedded in the elastomer, and the sensor can detect normal and shear forces simultaneously. However, there appear some problems. One is the signal noise in the sensor output generated in the long wire from the sensor elements to the amplifier. The other is a number of wires for collecting many signals of distributed sensor arrays. In this work, the tactile sensor chip and the LSI amplifier chip have been integrated heterogeneously to shorten the wire length and reduce the noise in the output voltage. Moreover, it is considered that integration of the tactile sensor and the signal amplifier can reduce the sensor size and wiring numbers, and allows installation of more sensors on fingertips of the robot. Firstly, the LSI amplifier chip was mounted on the surface of the tactile sensor chip (chip-on-chip). After fabrication of wires and microcantilevers with gauge film on the SOI wafer using surface micromachining, the microcantilevers were embedded in the elastomer (PDMS). Then, the LSI amplifier was inter-connected with sensors through electrical pads by Au wires. The noise (peak to peak) can be reduced from 750 mV to 120 mV by heterogeneous integration of the tactile sensor and the LSI amplifier. Next, the LSI amplifier was mounted on the backside of the sensor chip using through-silicon-via (TSV) holes instead of Au wires. The thickness of SOI wafer was reduced to 300 μm by polishing and via holes of diameter 55 μm were made by deep reactive ion etching (RIE). Silicon nitride film was deposited on the sidewall of the holes by LPCVD and the holes were filled with Cu plating. Then, projecting surface of TSV Cu was polished by chemical mechanical polishing (CMP). The average resistance of TSV holes, 3-4 Ω is enough low and insulation between holes is good (its resistance is over 50 MΩ). Moreover, these resistance values are not changed by dipping into buffered HF solution (NH4HF2: 20%) for 5 hours of sacrificial etching so that TSV holes are not damaged to fabricate the microcantilevers. Therefore, it is demonstrated that the LSI amplifier chip can be mounted on the backside of the sensor chip and the size of sensor chip can be shrunk to 5 mm square using TSV.

In our previous works, a charge transfer type of pH-sensor had been proposed. This pH-sensor was able to amplify the sensing signal by charge accumulation without using an external amplifier and was able to achieve a high S/N ratio as compared to the conventional type Ion-sensitive-field-effect-transistor (ISFET). However, when electron energy between sensor bottom and ICG (Charge Injection Gate) bottom are close (in other words, when output level is low), this pH-sensor has a potential barrier between the ion-sensitive area and ICG. This potential barrier causes unexpected charge that is remained on the sensing area. We called this â?~the charge of the false signalâ?T. So the number of accumulation was limited to 2 or 3, because this charge of the false signal accounts for 20% of the maximum output range, and also is amplified simultaneously with the charge of the true signal. To solve this problem, we proposed a new type of sensor. This sensor has a second gate on the potential barrier to suppress it. However, this structure needed the double layer Poly-Si process and was unsuitable in order to miniaturize sensor pixels for a two-dimensional array sensor. We propose a new type of pH-sensor in this paper. This sensor has a gate (Q-trap gate) that is formed next to the pH-sensing area by a first Poly-silicon. The new sensor operates by, first filling the potential well at the bottom of sensor area for the electron, and next, transforming the potential level of Q-trap gate from low to high. As a result, the deep electric potential well is formed under the Q-trap gate. On this operation, the charge of false signal is trapped from the pH signal charge that is stored up in the electric potential well under the sensing area. After this operation, transmission gate (TG) between the sensor area and the floating diode is turned on, and the true signal charge without the charge of the false signal is transferred to FD. By doing this, we can get the true signal voltage. We made this new type of pH sensor and evaluate it with 2um CMOS 1P1M process. As the evaluation, we have confirmed that the false signal charge was erased completely. As a result, the charge of the false signal accounted for 20% of the maximum output range in the conventional structure, has no effect on this new type of pH sensor. And we could accumulate the pH signal 15-times. (The number of accumulate was limited by the measurement equipment). So, we will be able to develop a super-high-sensitive two-dimensional array sensor shortly by using this Q-trap structure without the complicated wafer process. Reference [1] Kazuaki Sawada, T. Shimada, T. Ohshima, Hidekuni Takao, Makoto Ishida "Highly sensitive ion sensors using charge transfer technique, SENSORS AND ACTUATORS B, Vol.98,pp. 69-72, 2004 [2] Ref: J. Matsuo, T. Hizawa, K. Sawada, H. Takao and M. Ishida, "Charge Transfer Type pH Sensor with Super High Sensitivity", TRANSDUCERS'07, 2, pp.1881-1884 (2007)

Among the numerous techniques that are available for the detection of biomolecules, AlGaN/GaN Heterojunction Field Effect Transistors (HFETs) based sensors present an attractive alternative. They offer simpler, faster and label-free detection route. The key advantages of using III-Nitride heterostructure based FET sensors include higher sensitivity, arising from the two dimensional electron gas (2DEG) at the heterojunction interface, and better chemical/thermal stability even at elevated temperatures without a complicated fabrication process. The intrinsic charge of the biomolecules affects the surface states of the HFET thereby affecting the carrier concentration at the 2DEG channel. The proximity of the 2DEG to the surface helps in achieving very high sensitivity in these devices. The biofunctionalization at the gate electrode alters the transistor characteristics, leading to the fast and label-free detection of biomolecule analytes. Device fabrication process started with the successive steps of mesa etching, and deposition of both ohmic and Schottky contacts. After the wire bonding, photopatternable spin-on silicone was used to encapsulate the device except for the gate region. To immobilize the aminated probe DNA (5â?²-/5AmC6/CGCTTGAAGAGGTCAATGGCCA-3â?²), the device was immersed into an ethanol solution of 11-MUA,(_{HS(CH,2)10,CO,2,H})for 18 hrs. The OH-terminated functional group was then activated with the mixture of EDC (_C,8,H,17,N,3.HCl) and sulfo-NHS (_{C,4,H,4,NNaO,6,S}) to react with the amine group present in the probe DNA. This covalent attachment of the aminated probe has been chosen to increase the specificity of the sensor. The incorporation of the 11-MUA on the gate electrode results in a self-assembled monolayer (SAM) by gold-thiol bonding which electrically behaves as a dielectric capacitor. Thus, the detection is based upon the successive capacitive coupling of the intrinsic charge from the DNA and the redistributed ions from the buffer in the double layer. Both I-V and I-t characteristics of the transistor were measured during the immobilization and hybridization of the DNA molecules. Based on the change in current after hybridization, we were able to differentiate the hybridization of the complementary target DNA (5â?²-TGGCCATTGACCTCTTCAAGCG-3â?²) from that of 3 base pair mismatched target DNA (5â?²-TGGACATTGACCTATTCAAGAG-3â?²). Therefore, we have successfully demonstrated specific detection of DNA using III-nitride HFETs with amine-based biofunctionalization.

Development of silicon sensing devices with Integrated Circuits using MEMS/NEMS technology will realize an ideal sensing chip, which may be called as â?oSmart micro chipsâ?, and results in ideal sensor chips, which have several sensor devices, signal processing circuits, rf transmitters, and power supply using natural energy. In this presentation, smart micro-sensor-chips for monitoring of neural activities, real time monitoring of pH image to biochemical, biomedical and clinical applications are presented in our developed chips. Also, a novel Radio Frequency (RF) induced power supply system and on-chip antenna for micro sensor nodes is studied. Integration of radio frequency transmitter (RF) technology with CMOS/MEMS micro-sensors is required to realize the wireless smart micro-sensors system. In our developed chips, one is Si microprobe electrode and tube array chips for recording of neurons in the tissue and drug deliver use. The probe array can be fabricated on IC chips, using standard IC process followed by a selective Si probe growth. The developed chips is a smart silicon microprobe array chips to record neural activities for analysis of the mechanism of retina and brain, or for neural interfacing. The microelectrode array chip with extremely-fine, in other words, low-invasive silicon probes of 1-2um diameter, and fabricated using standard CMOS process followed by the selective vapor-liquid-solid (VLS) growth method. Using the chip, the feasibility of in-vitro recording of neural activities in a carp retina and of in-vivo recording of the peripheral nervous activity of a rat was demonstrated. Another one is pH image sensor chips. 32 Ã- 32 pH image sensors were successfully fabricated by using the CCD/CMOS image sensor technique, and real time imaging of a chemical reaction and pH distribution was carried out. The pH variations by a chemical reaction are observed by 200 ms step (i.e. 5 flames per sec). The pH image sensor was able to be applied to many application fields such as a biomedical and biochemical field. The technique of this pH sensor is based on the principle of a charge-coupled-device (CCD). The ion-sensing region is the thin Si3N4 film that acts as an ion-sensitive membrane. The images were taken by 200 ms step (i.e. 5 flames per sec). we tried to observe a living related material. Integrated techniques for the RF transmitter and power supply circuits by CMOS compatible and MES processes have been successfully developed for ideal smart sensing chips. The signal emission was confirmed near a few m distance. The integrated RF induced power supply system with a large capacitor of Surface Mount Devices (SMDs) is also developed. By these research results, smart micro sennsing chips could be realized.

In the past decades, the application of microelectronic and micro/nanotechnologies to the fabrication of solid-state devices stimulated emerging research in micro/nano sensors and actuators. The versatility of semiconductor and micro/nano materials promise new systems with better capabilities and improved performance-to-cost ratio over those of conventionally machined devices. In recent development of nano devices, one key bottleneck has been the integration of nanostructures with Microsystems/CMOS circuitry. This talk will discuss state-of-art integration methodologies of nanostructures with Microsystems/CMOS with past and on-going efforts. These research results cover various issues in the synthesis and assembly of one- and two-dimensional nanostructures and heterogeneous integration using MEMS as the building blocks including synthesis and assembly of carbon nanotubes, silicon nanowires, graphene and zinc oxide nanowires. One common innovation in these projects is the use of localized heating and synthesis such that nanostructures can be grown in a room temperature chamber. Synthesis, directional growth and self-assembly of one-dimensional nanostructures with Microsystems have been demonstrated by means of localized resistive heating, inductive heating; and local electrical field directed, in-situ monitored self-assembly processes. Current research programs will be briefed in the following areas: integrated nanoelectromechanical systems using nanotubes, nanowires, graphene and electrospun nanofibers. This talk will conclude with discussions on future research directions.

Silicon based bio-chemical sensors such as electrolyte-insulator semiconductor (EIS) and ion-sensitive field effect transistor (ISFET) have become increasingly important subjects of research due to their potential; compatibility with state-of-the-art complementary metalâ?"oxideâ?"semiconductor (CMOS) manufacturing technologies, disposability and label free sensing of biomolecules. Bio-chemical sensor based on ISFETs, however, simultaneously exhibited a main weakness in terms of device instability caused by ionic damages for long-term usage. Also, the poor sensing margin of ISFETs, theoretical maximum value is 59 mV/pH based on Nernst equation at room temperature, has highlighted serious threats for stability and reliability of devices. In this work, we realized high sensitive dual-gate (DG) ion-sensitive field-effect transistors (ISFETs) beyond Nernst limit of 59 mV/pH using silicon-on insulator (SOI) substrate. The electrical characteristics of the SOI MOSFET and the sensing properties of the SOI ISFET were evaluated using single gate or dual gate operations. As a result, although a relatively low sensitivity of 43.6 mV/pH was obtained by the top gate operation, the back gate operation significantly enhanced the pH sensitivity up to 379.2 mV/pH. This is because the sensitivity of DG ISFET is modified by the capacitive coupling between top gate oxide (sensing membrane) and bottom gate (buried oxide) of silicon channel. The electrical characteristics of the SOI MOSFET and sensing properties of the SOI DG ISFET were evaluated by single or dual gate mode operations. Also, an acceptable result associated with the long-term instability of ISFETs such as hysteresis and drift was obtained from the dual-gate operational mode. Therefore, the DG SOI-ISFETs, which are compatible with CMOS process, is very promising bio-chemical sensor for bio-medical applications.

Gene transfer techniques including gene gun are powerful tools in physiological sciences. In advances in nanotechnology, nano-scaled penetrating probes such as AFM probe and CNT have been used for the gene transfers, providing their advantages of local and pinpoint DNA transfers into the target cells. However, further technical requirements such as multipoint/batch and deep area gene transfer techniques are still problematic. For a new class of the gene transfers, we have developed the nanoscale-tipped microprobe array with a high aspect ratio fabricated by VLS growth of silicon microprobe, followed by the silicon chemical etching-based nanotip formation. The length and diameter of the probe-body were set at 20 μm and 2 μm, respectively, and the radius of curvature of the probe-tip was set at less than 100 nm. Individual nanoprobes were spaced 100 μm apart. For the multipoint DNA trap, these nanoprobes were metalized with 100 nm-thick gold by sputtering, and encapsulated with 1μm-thick parylene excepting for the gold-tip sections. After fabricating the nanoprobe device, we demonstrated DNA transfers into cells. The procedure comprise three major steps: (i) cells are cultured for 2-3 days, (ii) after dropping a solution including DNA onto the cultured cells, nanoprobes are penetrated into the cells for transferring DNA. (iii) on the next day, the cells are observed by fluorescence microscope. All cells presented were HEK293 and we used YFP (2μg/μl) by ubiquitous promoter. DNA transferred cells were observed by the fluorescence positive response during the fluorescence observations (Ex= 488 nm, Em= 530 nm). We also prepared cells without the nanoprobe penetration (cells were dipped in the same DNA solution), and confirmed no DNA transferred cells. However, the yellow cells were clearly observed by using the nanoprobe penetration, indicating that DNA was transferred into individual cells. In addition, another advantage of the nanoprobe array-based DNA transfer was confirmed as multipoint DNA transfer into individual cells at the same time. Such nanoprobe array-based DNA transfers are simple, fast and reproducible. Additionally, deep area DNA transfers would be possible by using the nanoprobe with a high aspect ratio, promising multipoint, local, and deep area gene transfers as a powerful experimental tool in numerous biological experiments.