High dielectric constant (high-k) materials to limit off-state tunneling current “leakage” for ULSI technologies is now widely adopted in Si-based CMOS production. Extending the scaling of integrated circuit technology to "the end of the roadmap" has now resulted in the investigation of transistors incorporating alternative channel materials, such as graphene and III-V compounds. The control of the interfacial chemistry between a high-k dielectric and these materials presents specific challenges. For III-V compounds, the bonding configuration is obviously more complicated, and thus an enhanced propensity to form interfacial defects, that may be electrically active, is anticipated. "Passivation" of these defects is a major avenue of research. Graphene, in contrast, can be relatively inert and presents challenges for high-k dielectric deposition as controlled functionalization of the graphene surface is required. We outline our recent work using in-situ deposition and analysis methods to study the ALD high-k/high-mobility interfacial chemistry, the resultant defects detected, and prospects for their passivation.

The increase in integration density of microelectronics makes it necessary to investigate materials with permittivities beyond ZrO2-based dielectrics to further fulfil Moore's law. Despite of extensive investigations, dielectrics with permittivities >100 (e.g. SrTiO3, BaTiO3) have not been integrated in microelectronics so far, because their comparatively low band gap gives rise to high leakage currents [Kersch].
Ultrathin calcium titanate (CaTiO3) films have been investigated here as a promising dielectric with k values of ~100 as an optimal compromise between high permittivity and a sufficiently large band gap of 4.2eV. Electrical characterization has been performed in detail on complete metal-insulator-metal stacks for layers with different electrodes and oxide thicknesses [Krause1]. Structuring of the top electrode (TiN or Ru) followed after post deposition anneals between 500-700°C. The samples with 4x4cm2 substrate size and capacitor dimensions of dia. 100-500µm prove the process control within industry standards.
For fully crystallized, 10nm thick CaTiO3 layers, reproducible capacitance equivalent thickness (CET) of 0.48-0.50nm on Pt electrodes with moderate leakage currents have been reached, rivalling other ABO3 oxides. The high band gap of CaTiO3 even allowed the use of electrodes with smaller work function like TiN and nanocrystalline carbon [Graham] ensuring cost effective processing. Indeed, complete Pt-free capacitor stacks show target leakage currents <1E-7A/cm2 @1V with a CET <1.0nm and proves that Schottky emission is not the driving factor for leakage current, as no significant difference in leakage currents vs. thickness for different electrodes is observed.
To further reduce the leakage currents, CaTiO3 crystallization was controlled to provide an intermediate degree of crystallinity between amorphous and fully (poly-)crystalline oxide [Krause2]. Single crystallites are surrounded by an amorphous matrix, which passivates the grain boundaries and therefore reduces leakage current of the capacitor. This reduction arises with an increase of the effective permittivity to 55 compared to an amorphous capacitor stack and a value of 25.
These results and extensive physical and electrical characterization show the great potential of CaTiO3 for future memory applications.
References:
[Kersch] Phase stability and dielectric constant of ABO3 perovskites from first principles, J. Appl. Phys. 106, 2009
[Krause1] Evaluation of the electrical and physical properties of thin calcium titanate high-k insulators for capacitor applications, J. of Vacuum Science & Technology B 29, 2011
[Graham] An investigation of the electrical properties of metal-insulator-silicon capacitors with pyrolytic carbon electrodes, J. Appl. Phys. 108, 2010
[Krause2] Reduction of leakage currents with nanocrystals embedded in an amorphous matrix in metal-insulator-metal capacitor stacks, Apl. Phys. Lett. 99, 2011

In0.53Ga0.47As has an intrinsic high electron mobility making it an attractive alternative semiconductor material for use in MOSFET applications (1). Scanning tunneling spectroscopy (STS) has been employed to show that the As-rich (2x4) surface reconstruction of In0.53Ga0.47As(001) contains an electrically unpinned surface Fermi level both before and after dosing with the trimethylaluminum (TMA) gate oxide precursor. It is possible the limit on the practical Dit associated with InGaAs(001)-(2×4) is passivation of the many As missing dimer defect sites as these defect sites contain metal-metal bonds. These defects sites are common to all InGaAs(001)-(2x4) surfaces ranging from GaAs to InAs (2). Scanning tunneling microscopy (STM) and density functional theory (DFT) show that the metal-metal bond defects can be passivated with HOOH(g).
Acquired filled state STM images of the degassed, decapped In0.53Ga0.47As(001)-(2x4) surface reconstruction show the characteristic zig-zag shapes of the rows, which are due to the presence of the mixture of wide double ideal As dimer unit cells and narrow single dimer defect unit cells. DFT was employed to model bonding geometries of TMA on In0.53Ga0.47As(001)-(2x4). The full coverage DMA/InGaAs(001)-(2×4) has a 0.2 eV wider bandgap than the clean surface consistent with passivating the CB edge states on undercoordinated As atoms. The full coverage DMA/InGaAs(001)-(2x4) model with the missing As dimer unit cell along with its calculated density of states shows a prominent VB edge state in contrast to the passivated ideal unit cell model. These VB edge states are primarily located on the In-Ga metal-metal bonds and adjacent bonds to As atoms. To remove these VB states it is likely an electronegative atom such as O must be inserted into the In-Ga bond. The CB edge states are located primarily on the tricoordinated In and Ga atoms in the In-Ga bonds. The DFT model of double site passivation by -OH shows the removal of CB edge states and preserved low VB states. Experiments were performed with HOOH(g) to see if missing As dimer defect states could be removed with just -OH passivation. To passivate the surface with -OH, vapor from 30% HOOH/H2O was employed at 25°C to minimize any reactions with arsenic. After ~1000L dose of HOOH(g) at 25°C followed by annealing at 211°C for 30 min and a second anneal at 250°C for 30 min, STM was performed. No As displacement was observed and mixture of wide and narrow row sites characteristic of the defects on the clean surface is nearly gone. This is consistent with -OH bonding to the In and Ga atoms. After a further annealing at 350°C for 30 min, the surface is more ordered; again, nearly all the row sites appear wide consistent with -OH bonding to the tricoordinated In and Ga atoms. These experiments show it is possible to passivate with -OH without disrupting the As atoms.
1. J.A. Del Alamo,Nature, 479, 317 (2011)
2. Edmonds et.al, ECS Transactions, 50, 4 (2012)

To scale down CMOS devices while keeping high performance, the requirements on the dielectrics such as a high capacitance and low leakage is getting challenging. In most high-κ systems, it is found that a sub-silicon oxide layer is still necessary at the interface, thus lowering the overall capacitance. Moreover, different metal gates lead to different effective work functions. Proper interface dipoles or charges must then be introduced to fine-tune the overall flat-band voltage (VFB).
This research aims to control the interfaces of MOS capacitors. We used MBE to grow oxide films on Si with three different initial monolayers - oxygen rich, metal rich, and co-deposition for both MgO and Al2O3. Annealing experiments were performed in order to improve the electrical properties. TEM was used for structural characterization.
For both as-grown MgO and Al2O3 films, a negative VFB shift with more oxygen in the first monolayers was found. The VFB of the MgO films are shifted but still close to the theoretical VFB value whereas there is a relatively large positive shift for the Al2O3 films. The VFB shifts to negative direction with increasing annealing temperature. The VFB difference between the samples with different initial growing conditions almost disappears after 450 °C annealing. Dit decreases with increasing annealing temperature. Dit of MgO films decreases to 1 × 1012 cm-2eV-1 after annealing. In the Al2O3 system, after annealing the lowest Dit of 3 x 1011 is observed.
Several models have been developed to explain the VFB shift. One is the oxygen vacancy model 1. Positively charged oxygen vacancies are created according to MgO = MgSi&’&’ + OOx + VO.. The positive charges cause a negative shift of the VFB. Thicker SiOx films are formed under an oxygen rich initial growing environment. When metal atoms diffuse into the thicker SiOx layers, more positive oxygen vacancies are created, and thus induce a larger negative VFB shifts. This phenomenon is more pronounced after annealing.
However, the oxygen vacancy model cannot explain the systematic positive VFB shift in the Al2O3 as-grown films. Another model called the oxygen density model 2 is considered. There is a tendency to move oxygen atoms from a high oxygen density layer to a lower one, and a dipole is formed. Since Al2O3 has a much higher oxygen density than MgO, a more pronounced positive VFB shift is found. The atomistic model 3 can also explain this different VFB shift direction. In this model, the shifts correlate with the work function / electronegativity of the metal. However, these latter two models cannot explain the VFB shift of different ML as discussed before. Clearly the overall observed results can only be explained by considering that the two different mechanisms are operational at the same time.
___________________________
1 Guha S et al 2007 Appl. Phys. Lett. 90 092902
2 Kita K et al 2009 Appl. Phys. Lett. 94 132902
3 Lin L et al 2009 Appl. Phys. Lett. 95 012906

We have developed an new approach which can provide much, if not all, of the analytical power of electron paramagnetic resonance (EPR) in studies of semiconductor /dielectric systems by monitoring several varieties of MOS device currents including current resulting from charge pumping measurements, trap assisted tunneling dominated gate leakage currents, and recombination currents in MOSFETs configured as gated diodes as a function of small to very small magnetic fields. The technique is loosely based upon ideas first expressed by Kaplan, Solomon, and Mott ( J.Phys. Lett. v.39, L51-54(1978)) in their explanation of the very large spin dependent recombination (SDR) response observed in some silicon based devices. They were first to point out that the magnitude of the effect should be, at least to first order, independent of the magnetic fields and frequencies at which the SDR is detected. We have taken this idea to its limit, making EDMR like measurements without an oscillating magnetic field at very low quasi- static fields. These measurements can allow the observation of the electron-nuclear hyperfine interactions which provide the most definitive structural information provided by EPR via by what is (at least in principle) a very simple measurement. This measurement should have a large sensitivity advantage for broad or complex spectra resulting from hyperfine interactions. Such interactions are a fundamental problem in EPR studies of III V compound semiconductor based MOS systems. We have demonstrated the capabilities of the new technique on a variety of SiC based MOSFETs, bipolar junction transistors and thin dielectric films.Of particular interest, we demonstrate that the approach works particularly well with charge pumping measurements on fully processed MOSFETs.

Electrically active defects that either trap carriers or act as centers of fixed charge are critically important in MOS devices. Their effects are particularly pronounced for arsenide-based semiconductors intended for NMOS devices because of 1) the relative ease of forming surface defects on these crystals, 2) the lack of an insulating native oxide (such a SiO2) to inhibit tunneling of electrons from the substrate into near-interface defects in deposited gate dielectrics, and 3) the low density of states in the conduction band of the semiconductor that enhances the effect of charge traps on the measured capacitance compared to materials such as Si or Ge. Alloying GaAs with InAs reduces the band gap of the former by lowering the energy of the conduction band edge, reducing the overall density of defect states in the band gap and thus the density of interface traps. Further reduction in both bulk dielectric defect densities (e.g. border traps and fixed charge) and interface trap densities can be achieved by appropriate pre-dielectric and post-dielectric processes.
This presentation will review recent results on pre-atomic layer deposition defect passivation, including trimethyl aluminum and oxidant pre-dosing of initially clean and oxide-free InGaAs (100) surfaces, plasma treatments of initially air-exposed surfaces, and post-dielectric defect passivation using hydrogen. Reliable interface trap density measurements that combine capacitance-voltage and conductance-voltage analysis indicate trends in interface trap density across the band gap (down to ~ 1012 cm-2eV-1 near midgap) and in border trap density as a function of the different passivation treatments. Results obtained from MOS capacitors fabricated on As2-decapped InGaAs (100) substrates are compared with reported density functional theory predictions and scanning probe measurements of InGaAs surface defect passivation.

III-V based metal oxide semiconductor field effect transistors (MOSFET) are strong contenders to replace Si in the future generations of high mobility transistor devices (Alamo et al., Nature 2011, 479, 317-323). InP is a potential candidate for use as a barrier layer between an InGaAs channel and high-k dielectrics (Radosavljevic et al., IEDM 2010, 126-129). Addition of this barrier layer moves the channel materials away from the high-k dielectrics, with the aim of minimizing the defects generated due to oxidation of the channel materials. However, the interfacial quality between InP and the high-k dielectrics still affects the electrical performance of the devices, having an impact on subthreshold swing and drain induced barrier lowering (Gu et al., Appl. Phys. Lett. 2011, 99, 152113). Based on previous in situ atomic layer deposition (ALD) Al₂O₃ half cycle studies on InP using X-ray photoelectron spectroscopy (XPS) (Brennan et al., Appl. Phys. Express 2011, 4, 125701), for acid etched and native oxide InP samples, the concentration of P-oxides is seen to increase after exposure to the first pulse of the metal trimethylaluminum (TMA) precursor. Also, a previous study looking at the impact of post deposition annealing on the electrical performance of these structures indicated that an increase in P rich oxides is correlated to an increase in the interface state densities (Dit) (Galatage et al., Appl. Phys. Lett 2011, 99, 172901).
In this work, a thin interfacial layer (IL) of Si (1nm) is deposited by plasma enhanced chemical vapor deposition with the aim of scavenging In and P-oxides states from the interface, prior to ALD of Al₂O₃ and prevent oxide regrowth during deposition. Using in situ XPS to prevent atmospheric exposure after high k dielectric deposition, we will investigate the interfacial chemistry of the Al₂O₃/Si/InP stack and the thermal stability of the interfaces following in situ annealing up to 400 °C and 500 °C under ultrahigh vacuum.
This work is supported by the Semiconductor Research Corporation FCRP MSD Focus Center, the Nanoelectronics Research Initiative and the National Institute of Standards and Technology through the Midwest Institute for Nanoelectronics Discovery (MIND) and the NSF (ECCS-0925844).

GaN MOSFETs with normally-off operation have outstanding features such as being able to operate under high-temperature, high-frequency, and high-power conditions. Therefore, GaN MOSFETs are promising for power switching applications. For GaN MOSFET, a high quality gate insulator is required to be a low interface-state density (D_it) between gate insulator and GaN, a high breakdown voltage and a high reliability, respectively. Here, we report on the experimental demonstration of applying SiO₂/Al₂O₃ gate stack to GaN MOSFET. In order to investigate the interface properties of gate insulator/GaN and the electrical characteristics of insulators, n-type GaN on Si (111) substrates were applied for fabrication of GaN MOS capacitors. We first have investigated the formation process of SiO₂ films by Microwave (2.45 GHz: MW) Plasma Enhanced Chemical Vapor Deposition (PECVD), LP (Low Pressure)-CVD, and Capacitive Coupled Plasma (CCP)-CVD for the gate insulator of GaN MOS devices. MW plasma is capable of exiting a low-electron temperature and a high-electron density at the substrate surface position. The SiO₂ films were deposited below 400^oC by MW-PECVD and CCP-CVD and at 800^oC by LP-CVD. As the results, the GaN MOS capacitor with MW-PECVD SiO₂ has shown the lowest D_it of SiO₂/GaN with 4.5×10¹¹ cm^-2 eV^-1, the highest breakdown electric field with over 11 MV/cm, and the largest charge-to-breakdown (Q_bd) with over 1 C/cm², respectively, of these GaN MOS capacitors. However, the D_it is still higher compared with Si devices. Therefore, we have investigated the other gate insulator. Al₂O₃ has a large direct wide bandgap, a large conduction band offset and a large valence band offset on GaN, respectively, as well as SiO₂. So, we applied Al₂O₃ to the gate insulator of GaN MOS devices. The GaN MOS capacitor with Al₂O₃ has a low D_it with 2.3×10¹¹ cm^-2 eV^-1 by suppressing the Ga diffusion to gate insulator. However, it has a low breakdown electric field with below 7 MV/cm. From the both advantages of MW-PECVD SiO₂ and Al₂O₃, SiO₂/Al₂O₃ stacked structure has been employed for good interface property and a high insulating in GaN MOS devices. In this experiment, Al₂O₃, the thickness of which was verified from 1.5 nm to 5 nm, was formed on GaN and then 50 nm SiO₂ was deposited on Al₂O₃. As the results, by applying the 3 nm Al₂O₃, the GaN MOS capacitor with SiO₂/Al₂O₃ stacked structure shows a low D_it as well as Al₂O₃, a high-breakdown field, and a high Q_bd as well as MW-PECVD SiO₂, respectively. Next we have fabricated AlGaN/GaN hybrid MOS-HFETs with SiO₂/Al₂O₃ gate stack and MW-PECVD SiO₂ gate insulator and compared the properties of these transistor. Both MOS-HFETs shows good normally-off operation with the threshold voltage of 4.2 V. The on-state characteristic of MOS-HFET with SiO₂/Al₂O₃ is superior to that with MW-PECVD SiO₂. The maximum field-effect mobility of MOS-HFET with SiO₂/Al₂O₃ is 192 cm²/Vs, which is superior to that with MW-PECVD SiO₂ of 161 cm²/Vs.

In the field of high-k gate dielectric engineering on high-mobility channel materials, there have been many attempts to obtain a superior interface quality by inserting several ultra-thin layers, such as Si, Ge, Gd2O3, and Al2O3 [1]. More recently, Kundu et al. used molecular beam epitaxy (MBE)-grown ZnO films as an interfacial passivation layer on a sol-gel-derived ZrO2 film in the GaAs system and reported an improvement in the electrical properties [2]. Instead of using the ex situ grown, relatively thick (~2 nm) ZnO passivation layer [2], in this study, we deposited ultra-thin ZnO layers on p-type GaAs substrates with different numbers of atomic layer deposition (ALD) cycles and subsequently grown ALD-HfO2 films as a gate dielectric layer in situ.
In order to investigate the ZnO passivation effect, the ALD process started with various numbers of ZnO forming cycles on the GaAs substrates with and without a native oxide, i.e., as-received and HF+(NH4)2S-cleaned GaAs substrates, respectively, and ended with an in situ growth of the 8 nm-thick ALD-HfO2 films. According to the frequency-dependent capacitance measurement, a significant reduction in the frequency dispersion was observed in both the accumulation and inversion regions by performing only 10 cycles of ALD-ZnO passivation process even on the as-received GaAs substrate, without an increase in the capacitance equivalent oxide thickness: the frequency dispersion in the accumulation region was reduced from ~14 % to ~4.5 %. By using the native oxide-removed and S-passivated GaAs substrates, a further reduction in the inversion region was also achieved. Microstructural/interfacial analyses have been probed by high-resolution electron microscopy and x-ray photoelectron spectroscopy, respectively, and other electrical characteristics will be also presented.
[1] M. Houssa, E. Chagarov, and A. Kummel, MRS Bull., 34, 504 (2009).
[2] S. Kundu, T. Shripathi, and P. Banerji, Solid State Commun., 151, 1881 (2011).

III-Nitride-based Metal-insulator-semiconductor high electron mobility transistors (MISHEMTs) structures can efficiently suppress gate leakage in vertically scaled transistors for higher frequency operation, and also enable ultra-low leakage for power switching circuits. In this work, we discuss the presence of fixed interface charges at the dielectric/semiconductor interface, their effect on the energy band profile and electron transport, and methods to reduce this fixed interface charge density.
Recent work has shown that a high density of fixed charges (~1 mu;C/cm2) is induced at ALD-grown Al2O3/GaN and Al2O3/AlN structures[1,2]. It was shown that this charge is not modulated by electric field, but it does significantly modify the electrostatics in the system. The high interfacial fixed charges reduce the mobility of the 2-dimensional electron gas (2DEG)[3] through remote ionized impurity scatter, and induce high electric fields in the oxide thus increasing tunneling-related leakage currents. Theoretical investigation of remote impurity scattering for dielectric/AlGaN/GaN structures and the effect dielectric/AlGaN interface charge density, 2DEG concentration, and AlGaN thickness will be presented. Remote impurity scattering was found to be the dominant mechanism when the 2DEG density is below 5x1012 cm-2. The interfacial charge has significant effect on the mobility as the cap layer thickness is scaled down below 5nm.
Post-metallization anneal (PMA) can be used to reduce the fixed interface charge at the Al2O3/GaN interface in Ga-polar, N-polar and non-polar GaN layers. We present experimental data using Al2O3 layers with different thickness deposited by ALD. After oxide deposition and gate metallization, PMA was carried out at different temperature: 400C, 450C and 500C. A quantitative analysis was carried out to determine conduction band discontinuity, electric field in the dielectric layer, and interface fixed charge from C-Vmeasurements for each polarity. A linear relationship between the flat-band voltage and oxide thickness was observed, indicating non-zero electric field in the oxide, even during flat band conditions in the GaN. Successively higher PMA were found to decrease the interface charge. The field in the oxide under flat band conditions in GaN was reduced from 1.92 to 0.22 MV/cm corresponding to a large decrease in the interface net charge density from 1x1013 cm-2 to 1x1012 cm-2. The gate leakage current was also suppressed due to the reduction in the electric field. The reduction of interface charge density using post-metallization anneal was found to occur not only in Ga-polar GaN, but also in N-polar GaN, non-polar GaN, and AlGaN/GaN structures. [This work was funded by the ONR DEFINE MURI (Dr. D. S. Green)]
Reference: [1]M. Esposto, et al., Appl. Phys. Lett., 99, 133503 (2011) [2]S. Ganguly, et al., Appl. Phys. Lett., 99, 193504 (2011) [3]T.-H. Hung, et al., Appl. Phys. Lett., 99, 162104 (2011)

Interface state density (Dit) is a key parameter in determining metal-oxide-semiconductor (MOS) device performances; it involves the atomic, and hence the electronic, structure at the interface. Interfacial electronic structure of high k dielectrics on single-crystal GaAs(001)-4x6 and In0.20Ga0.80As(001)-4x2 surfaces will be presented, using synchrotron-radiation core-level photoemission as a probe. Demonstration of atomically clean III-V surface will be firstly given followed by the dielectric interface grown by atomic layer deposition (ALD) with cycles. Data with this bottom-up method reveal interaction between the atoms in precursor and the surface atoms in III-V substrate, whose knowledge has been greatly masked by the top-down method where the dielectrics were deposited onto a surface with native oxides. The pristine Ga-rich GaAs(001)-4x6 surface is terminated by As, while the InGaAs(001)-4x2 surface by In. No As-As dimers are found at these surfaces. The initial precursor as trimethyl-aluminum (TMA) or hafnium ethylmethylamide (TEMAHf) selectively bonds with the surface atoms either physisorbedly, or chemisorbedly by losing one or two methyl groups. Consequently, the following water add-on affects differently with the bonded precursors, and the etching effect occurs at the interface. Our study showed that the growth of dielectric oxides does not follow the layer-by-layer fashion, and all reactions of high k dielectrics with (In)GaAs(001) were restrained at the top-surface layer without introducing high charge states. For comparison, one cycle of TMA and H2O totally passivates the As-rich GaAs(001)-2x4 surface, and the aluminum oxide grown by molecular beam epitaxy (MBE) alters greatly the surface structure. The photoemission data explain the magnitude of Dit in the range of low 10e12 range.

Formation of high-quality III-V and Ge channels on Si wafers is one of key processes for us to take advantage of the high mobility of these materials in the CMOS devices. A promising channel-formation technique is the epitaxial lift-off (ELO) process in which an epitaxial layer grown on a III-V substrate is transferred onto a Si wafer by selectively etching a release layer formed between the epitaxial layer and substrate [1]. The ELO technique can readily produce defect-free channel layers, while the heteroepitaxial growth of the III-V/Si and Ge/Si structures generally suffers from various defect formation due to the lattice mismatch and double domain formation. The wafer-scale layer transfer is, however, unrealistic because the lateral etching of the release layer takes too long time. In this paper, we demonstrate wafer-scale layer transfer of GaAs and Ge onto 300 mm Si wafers using the patterned ELO process.
As for ELO of GaAs, an AlAs release layer (5-150 nm) and a GaAs channel layer (1.0 mu;m) were grown successively on a GaAs(100) substrate by MOCVD. The GaAs/AlAs layer was patterned into square structures (300×300 mu;m2) using a lithography technique. Then the GaAs wafer with the patterned GaAs/AlAs layer was bonded to a 300 mm Si wafer by using the surface-activated bonding technique at room temperature. Finally, the AlAs release layer was selectively etched in an HCl aqueous solution. Thus, ELO of GaAs layer onto Si was completed, while GaAs mother substrate was reclaimed. ELO of Ge channel layer was also achieved in a similar manner by using the Ge/AlAs layer grown on the GaAs substrates.
The quality of the ELO GaAs layer was evaluated by photoluminescence (PL) and X-ray diffraction (XRD) measurements. FWHM of PL peak for the ELO GaAs layer was comparable to that for the as-grown GaAs epitaxial layer on the GaAs wafer. From the lattice constant evaluated by XRD spectra, we confirmed that the strain of the ELO layer was less than 0.1%. AFM observation showed that the surface roughness of the ELO GaAs layers depended on the thickness of the AlAs release layer. The best RMS roughness (10×10 µm2) was 0.2 nm which was only slightly larger than that for the as-grown GaAs epitaxial layer surfaces (typically 0.1-0.2 nm). We also succeeded in fabricating GaAs-on-insulator (III-V-OI) and Ge-on-insulator (GOI) wafers, in which Al2O3 layers of 10 nm thickness were used as the buried oxide (BOX) layer. The wafer-scale pattern ELO technique opens up the new way for us to manufacture the CMOS devices incorporating the high mobility channels by using the standard tools of the LSI manufacturing. [1] T. Maeda et al., SSDM 2011, p.1442.

The use of III-Vs in FETs has been hindered by our inability to properly passivate their surfaces so that the Fermi-level could be shifted freely across the whole band gap. Further development of III-V MOSFETs requires a better understanding of defects at the dielectric:semiconductor interface and properties such as band alignments. Here we calculate the chemical trends of various intrinsic interfacial defects of InAs, InP and GaSb compared to GaAs using ab-initio methods. We find that Nitrogen is a very effective passivant because interfacial configurations that can cause gap states like As-As dimers or some As-O bonds are unstable when As is replaced by N.
We calculated the relaxed atomic structure and partial density states of states (PDOS) at the defect-free Al terminated Al2O3 : GaAs (100) interface. To obtain band offsets without the DFT band gap problem, we use the sX hybrid functional to calculate band structures and band offsets. We consider various defects: like-atom bonds (dimers), dangling bonds (DBs), and Ga or As sites with the wrong number of oxygen neighbors. We also varied electron occupancies of DB and dimer states, which can bring states into the gap.
The relaxed atomic structure and defect state for the Ga DB is calculated when it is empty or filled with 1 electron. The DB energy level lies outside the gap for an empty DB in GaAs. When partly occupied, the DB state comes into the gap because the Ga bond angle relaxes towards pyramidal. Taking the transition state as mid-way between the level for empty and part-filled case, then its lies above the conduction band minimum (CBM). The As DB state on Hf2O3:GaAs(110) is also studied. A similar defect occurs on (100). For the filled DB, the state lies below the VB edge. When partly empty, the As site becomes flatter, and this state rises into the gap at +0.2 eV, causing gap states
We also studied the interfacial anion-anion dimers for GaAs, InAs, InP and GaSb. For GaAs, the As-As antibonding state lies near the CBM. If filled by 1 electron, the bond weakens, and the state drops into the gap. In InAs, the As-As σ* state lies at the same energy as in GaAs - well above InAs&’s CBM. For InP, the P-P bond is stronger, so its σ* state lies well above the CBM. In GaSb, the Sb-Sb bond is weaker but considering the small band gap of GaSb, the Sb-Sb σ* state is also above CBM. Therefore in InAs, InP, and GaSb the dimer antibonding states are all above the CBM and do not contribute to Fermi level pinning. These states can become important, as EF can enter the CB.
If the last layer of As is replaced by nitrogen, this causes a substantial change in behavior. We find that N-N dimers are unstable and will not form. Only certain combinations of N-O bonds are stable. Direct Al-N bonds are very stable. Thus, N passivation with metal first ALD is also a good combination for well passivated interfaces, as well as InP-capped quantum well channel as used by Intel.

One of the most critical issues for Ge/III-V MOSFETs, which have been regarded as a promising CMOS structure under sub 10 nm regime, is formation of superior gate stacks satisfying the requirements of thin equivalent oxide thickness (EOT) and excellent MOS interface quality enabling high channel mobility and low S factor. In this paper, we focus on viable III-V/Ge gate stack technologies realizing these requirements and the impact on MOS channel mobility.
As for Ge gate stacks, we present ultrathin EOT Al2O3/GeOx/Ge and HfO2/Al2O3/GeOx/Ge gate stacks, fabricated by a plasma post oxidation method, and the electrical properties of n- and p-MOSFETs using these gate stacks. EOT of HfO2/Al2O3/GeOx/Ge gate stacks has been scaled down to 0.76 nm with low gate leakage and low interface state density (Dit). (100) Ge pMOSFETs with high peak mobility of 596 and 546 cm2/Vs have been realized for EOT of 0.82 and 0.76 nm, respectively. Also, (100) Ge nMOSFETs with high peak mobility of 754 and 690 cm2/Vs have been realized for EOT of of 0.82 and 0.76 nm, respectively. We evaluate limiting factors of electron and hole mobility in Ge n- and p-MOSFETs. It is found in a high Ns region that the Ge MOS channel mobility is significantly degraded by both trapping of free holes and severe surface roughness scattering. It is shown that the mobility in the high Ns region can be improved by reduction in surface roughness through a layer-by-layer plasma oxidation process.
As for InGaAs gate stacks, we show the impact of Al2O3 inter-layers on interface properties of HfO2/InGaAs MOS interfaces. It is found that the insertion of 0.2-nm-thick ultrathin Al2O3 inter-layer can effectively improve the HfO2/InGaAs interface properties such as the frequency dispersion and the stretch-out of C-V characteristics and Dit. The 1-nm-thick capacitance equivalent thickness (CET) in the HfO2/Al2O3/InGaAs MOS capacitors is realized with good interface properties and low gate leakage of 2.4×10-2 A/cm2. It is shown, on the other hand, that Dit inside the conduction band (CB) of InGaAs, evaluated by combination of split C-V and Hall measurements, significantly reduces effective mobility in in high Ns, attributed to overestimation of Ns by split C-V. The amount and the energy levels of this interface states inside CB can be modulated by MOS interface quality and In content of InGaAs channels. Another critical factor for the mobility reduction in III-V MOSFETs is the thickness fluctuation scattering of the ultrathin body channels. We propose MOS interface buffer channel structures, where InGaAs buffer layers sandwich InGaAs channels with higher In content in order to mitigate the influences of MOS interface defects and the channel thickness fluctuation. Actually, we have observed the significant mobility enhancement in the In0.3Ga0.7As/In0.7Ga0.3As/ In0.3Ga0.7As-OI structure over single In0.7Ga0.3As-OI structures.

Extensive research activities in recent years have focused on developing high-k dielectrics, such as Al₂O₃ and HfO₂, on n-In_0.53Ga_0.47As for metal-oxide-semiconductor field effect transistors (MOSFETs) with high-mobility III-V semiconductor channels. One of the most serious challenges for III-V channel MOSFETs is the inherently large density of traps (D_it) at the high-k/III-V semiconductor interface, which tends to become particularly severe for highly scaled dielectrics with equivalent oxide thicknesses (EOTs) < 1 nm. In this presentation we show that novel surface preparation methods allow for highly scaled of HfO₂/Al₂O₃/n-In_0.53Ga_0.47As and HfO₂/n-In_0.53Ga_0.47As gate stacks with EOTs of 0.5 nm and D_it < 5x10¹² cm^-2 eV^-1. In particular, we report on the influence of hydrogen and nitrogen plasma treatments, respectively, before atomic layer deposition (ALD). Interface trap densities are characterized by capacitance-based and conductance methods. We show that nitrogen plasma cleaned stacks exhibit much reduced frequency dispersion in depletion that is due to midgap D_it even for highly scaled stacks. High-quality HfO₂/Al₂O₃ bilayers and HfO₂ MOSCAPs exhibit accumulation capacitance densities well above 2 mu;F/cm ² . We report on the physical differences, including interfacial layer thicknesses, for the differently cleaned gate stacks, and discuss the reasons for the improved performance of the nitrogen-plasma cleaned stacks.

Among In_xGa_1-xAs (x=0-1), GaAs offers distinct advantages of high electron mobility and easier integration on Si, with a smaller lattice mismatch of GaAs/Si than that of In_0.53Ga_0.47As/Si.
In addition, MOS devices using GaAs with a band gap of 1.42 eV are less prone to junction leakage, band to band tunneling, and other adverse effects than those using small band-gap In_0.53Ga_0.47As channels.
Despite intensive studies to passivate GaAs with ALD-Al₂O₃ and -HfO₂, interfacial trap density (D_it) distributions of excessively high values were commonly observed, also with a large peak near the midgap. However, the recent efforts using in-situ ALD-HfO₂, UHV e-beam deposited rare-earth oxides, and molecular beam deposited Al₂O₃ have reduced and even eliminated the large Dit values around midgap. It was also found that the employment of GaAs (001)-4x6 has given significant D_it reduction near the mid-gap, comparing with the usage of As-rich (2x4) and As- covered (4x4) surfaces. With these attained experimental results, GaAs(111)A with a Ga-terminated surface may render better electrical properties.
In this work, using in-situ synchrotron radiation photoemission, we have found that on the GaAs(111)A surface the bulk progression of alternating Ga and As layers is capped by a single layer containing four As and three Ga atoms in a 2x2 surface unit cell. The nominal Ga surface atoms are drawn down into the As layer, bonding to As atoms with three coplanar sp² hybridized bonds, which gives rise to the Ga vacancy model. Both the Ga 3d and As 3d core-level spectra exhibit surface emission. Upon an epitaxial growth of Gd₂O₃, the surface lines merge into the bulk line, meaning that Gd₂O₃ effectively passivates the surface atoms. According to the As 3d spectrum, however, 25% of the surface atoms remain unpassivated. The Gd₂O₃ epitaxial films 2 and 4 nm thick are single crystalline hexagonal and monoclinic phases, respectively, thoroughly studied using synchrotron radiation x-ray diffraction. The Gd₂O₃/ and Y₂O₃/GaAs films have been rapid-thermal-annealed to 900°C and remained intact, indicating high-temperature stability. JE and CV of the p-MOSCAPs are comparable to the best results of the UHV-deposited rare earth oxides on n-GaAs (100) 4x6 surfaces.

As driven by continual demands of enhanced-transport in channels and reducing power dissipation, high carrier mobility channel materials of III-V compounds and Ge are now the consensus candidates beyond the Si CMOS 15 nm node, to extend the Moore&’s Law. This talk gives an overview on our recent efforts undertaken in realizing the inversion-channel high k/InGaAs MOSFET as a viable technology. Research on the nano-scale high k oxide/III-V interface is crucial, as the heart of the MOSFETs. The engineering of this key interface on the atomic level was made possible by the innovation of in-situ atomic layer deposition on molecular beam epitaxy grown III-V pristine surfaces. Comprehensive temperature dependent electrical conductance analysis plus deep level transient spectroscopy (DLTS), in conjunction with scanning spectroscopy and microscopy including STM/STS and photoemission spectroscopy by synchrotron radiation were conducted to characterize the atomic and electronic structure of the interface thoroughly, thus resolving the long-standing puzzle of the interplay between interfacial structures and electronic properties. Record-high device performance in drain current, transconductance, and sub-threshold swing of self-aligned inversion-channel InGaAs MOSFET has been demonstrated.
Work done in collaboration with M. Hong, C. A. Lin, Y. C. Liu, T. D. Lin, Y. C. Chang, M. L. Huang, Y. H. Chang, P. Chang, W. C. Lee, Y. D. Wu, L. K. Chu, W. W. Pai, Y. P. Chiu, T. W. Pi.

High mobility channel materials, eg.In_0.53Ga_0.47As, in conjunction with high dielectric constant (high-k) oxides, are currently the focus of concerted research effort for future high speed logic applications. Interface state densities in the high-k/In_0.53Ga_0.47As system are typically reported^1-2 in the range mid-10¹² to 10¹³cm^-2 eV^-1, too high for practical device applications. Few studies in the literature have reported CV responses consistent with true minority carrier behaviour for In_0.53Ga_0.47As MOS devices.^3-5
The objective of this work is to identify the key signatures of a high-k/In_0.53Ga_0.47As surface inversion response in order to differentiate such behaviour from the typical D_it related response observed for high-k/In_0.53Ga_0.47As. The paper will present the simulated CV and GV of high-k/In_0.53Ga_0.47As MOS structures as a function of ac signal frequency, for the case of no interface defects or border traps, which identify the following features associated with a surface inversion minority carrier response: a plateau in the CV and GV responses in inversion; a peak in G/omega; corresponding to the transition frequency; a minimum capacitance at high frequency⁶ which scales as a function of the semiconductor doping; and an activation energy for the minority carrier response which demonstrates a transition from a generation-recombination regime (E_g/2) to a diffusion controlled response (E_g) as temperature increases. These features are all distinct from a D_it response, providing a framework to distinguish high D_it levels from a minority carrier response of an inverted surface.
Extending on results presented in [3], the paper will also present experimental results for MOS devices fabricated using n-type and p-type In_0.53Ga_0.47As, using an optimized 10% ammonium sulfide ((NH₄)₂S) treatment, with variations in the Al₂O₃ thickness (4nm, 8nm, 12nm), and In_0.53Ga_0.47As doping concentration (1x10¹⁶cm^-3 to 1x10¹⁸ cm^-3). The experimental CV and GV responses exhibit the expected responses for surface inversion, and in particular, where the minimum capacitance varies with In_0.53Ga_0.47As doping⁶. These results indicate that, with appropriate surface preparation techniques, D_it levels can be reduced to values ~ 8x10¹¹ cm^-2eV^-1 at mid-gap energies, and more importantly, the very high D_it levels generally towards the In_0.53Ga_0.47As valence band edge (E_v)⁷, can be reduced to levels which allow surface inversion in both p and n high-k/In_0.53Ga_0.47As MOS devices.
¹Hwang et al,Appl. Phys. Lett,96,102910 (2010)
²Radosavljevic et al, IEDM (2009)
³O&’Connor et al,Appl. Phys. Lett,99,212901 (2011)
⁴Lin et al,Appl. Phys. Lett,100,172110 (2012)
⁵Trinh et al,Appl. Phys. Lett,97,042903 (2010)
⁶Callegari et al,Appl. Phys. Lett,54,332 (1989)
⁷Brammertz et al,ECST 19,375 (2009)

Although the qualities of III-V native oxides are poor, deposition of high-k dielectrics using atomic layer deposition (ALD) have shown promising progress. Most recently, work on ALD HfO2 on In0.53Ga0.47As has resulted in good electrical properties1. However, high interfacial states still exist, as evident by notable Dit “hump” and frequency dispersion in the C-V response2,3. Lately it has also been observed that FGA of the Al2O3/In0.53Ga0.47As system results in a reduction in the Dit near the conduction gap edge4. While improvements in Dit following FGA are evident through C-V and MOSFET performance, the underlying origin of the improvement is not clear. In order to gain more understanding of the influence of FGA on HfO2/ In0.53Ga0.47As structures, we performed a combined study using attenuated total reflectance infrared (ATR-IR) spectroscopy, x-ray photoelectron spectroscopy (XPS), electrical measurements and transmission electron spectroscopy (TEM) to investigate the interfacial layer development between HfO2 and In0.53Ga0.47As for initially deposited, N2 anneal only and FGA, each at 350°C for 30 minutes. The HfO2 was deposited on epi-ready (native oxide) n-In0.53Ga0.47As/n+-InP samples using atomic layer deposition. Reduction in the interlayer oxide is observed after FGA where As-O bonds are observed to decrease using ATR-IR. A reduction in the Arsenic (As) oxide states are also observed after FGA using XPS as compared to the N2 annealed only sample. These findings are consistent with the observation of a reduced interlayer by TEM analysis, suggesting that H2 could possibly be playing a role in the decomposition of As oxides. Some arsenic diffusion could also explain the decomposition of As oxides observed by XPS analysis of As oxidation states. An increase in the maximum accumulation capacitance (Cmax) and marked improvement in CV response is found following the FGA and N2 anneal processes which is consistent with the ATR-IR, XPS and TEM measurements. The improvement in the CV behavior, and the increase in Cmax, is less pronounced with N2 anneal than with FGA anneal, suggesting that the improvements are not solely due to a thermal process, and that the H2 is playing a role in the modification of the interlayer native oxides during annealing.
1T.D. Lin, Y. H. Chang, C. A. Lin, M. L. Huang, W. C. Lee, J. Kwo, and M. Hong, Appl. Phys. Lett., 100, 172110 (2012)
2E. O&’Connor, S. Monaghan, R. D. Long, A. O&’Mahony, I.M. Povey, K. Cherkaoui, M. E. Pemble, G. Brammertz, M. Heyns, S. B. Newcomb, V. V. Afanas&’ev, and P.K. Hurley, Appl. Phys. Lett., 94, 102902 (2009)
3R. Suzuki, N. Taoka, M. Yokoyama, S. H. Kim, T. Hoshii, T. Maeda, T. Yasuda, O. Ichikawa, N. Fukuhara, M. Hata, M. Takenaka, S. Takagi, J. Appl. Phys., 112, 084103 (2012)
4V. Djara, K. Cherkaoui, M. Schmidt, S. Monaghan, E. O&’Connor, I.M. Povey, D. O&’Connell, M. E. Pemble, P. K. Hurley, IEEE Trans. Electron. Dev. 59, 1084, (2012)

At the same equivalent oxide thickness, the low transport mass and resulting high saturated and injection velocity of III-V materials may provide for high on-state currents, thus III-V materials, particularly In_xGa_1-xAs (xge;0.53), have been considered for LSI applications. The InGaAs/InAlAs material system lattice matched to InP has been widely studied for high speed electron devices. However, aiming at replacing Si channels below 10 nm Lg generations, the InGaAs channel thickness must be scaled to ~3-5 nm in order to maintain reasonable electrostatic control. Given the conduction band offset between In_0.53Ga_0.47As and In_0.52Al_0.48As (~0.5 eV), upon scaling the InGaAs channel thickness, the eigenstate energy will increase in the InGaAs channel and cause electron spillover into the InAlAs barrier leading to a parallel conduction path in the barrier and the degradation of transport properties. A barrier material with higher conduction band offset is therefore indispensable for realizing InGaAs MOSFETs for sub-10-nm generations.
In this paper, an AlAs_0.56Sb_0.44 layer lattice matched to InP is proposed as a novel barrier material for InGaAs channel MOSFET. AlAs_0.56Sb_0.44 with 1.74 eV conduction band offset to In_0.53Ga_0.47As at the Gamma point could provide better electron confinement compared with an In_0.52Al_0.48As barrier. We have investigated the growth and doping behavior of AlAsSb layer by solid source molecular beam epitaxy. Silicon and tellurium were studied as n-type dopants. However, similar to most of Sb-based materials, AlAs_0.56Sb_0.44 demonstrates a limited active carrier concentration of around 2x10¹⁸ cm^-3. Instead of using AlAsSb as modulation-doped layer, we propose inserting a Si-doped InAlAs layer in the AlAsSb barrier as modulation-doped layer. We demonstrate InGaAs/AlAsSb 2DEG structure with 10 nm channel thickness, showing electron Hall mobility up to about 10000 cm²/Vs at 300 K and 32000 cm²/Vs at 77 K. A highly scaled 5 nm InGaAs/AlAsSb 2DEG structure maintains the electron mobility up to about 4900 cm²/Vs at 300 K. This study demonstrates that AlAsSb is a promising barrier material for highly scaled InGaAs MOSFETs.

The gate-architecture in mature Si-CMOS technologies has already changed from planar to Fin-gate, and sooner or later will be gate-all-around (GAA) or surrounding-gate architecture. At the same time, Si channels will be replaced by InGaAs and Ge channels.
Recent advances in epitaxial techniques such as Vapor-Liquid-Solid (VLS) method and selective-area growth (SAG) have enabled the heterogeneous integration of III-V nanowires (NWs) on Si substrate [1]. We have firstly achieved position-controlled InGaAs nanowire vertical transistor and InGaAs nanowire high-electron mobility transistors on Si [2]. Here, we report on demonstration of high conductive InAs nanowire channels on Si with effective-oxide thickness (EOT) of 0.90 nm.
At first, we grew InAs NWs on p-Si (111) by low-pressure horizontal MOVPE system. Growth conditions were as follows; partial pressure of TMIn, [TMIn] = 4.87 x 10-7 atm, partial pressure of AsH3, [AsH3] = 1.25 x 10-4 atm, growth temperature = 560 oC, growth time = 10 min. Next, same growth was continued for 10 min with introducing SiH4 doping to make axial n-n+ junctions inside the InAs NW. After these growths, hafnium alminate (HfAlO) was deposited by atomic layer deposition for high-k gate dielectric, followed by the deposition of tangsten (W) by plasma sputtering for gate metal. To remove the gate metal and high-k dielectric resides on the top portion of NWs, protecting layer for etching of low-k insulator resin was formed firstly by spin-coating and then by reactive ion etching (RIE) to etch back to the desired thickness, followed by dry and wet etching of W and HfAlO. This process defines the gate length. In this case, the gate length was 100 nm. After that, separating layer between gate and drain top contact was formed by spin-coating of low-k resin and then it was etched back by RIE to expose top region of NWs. Finally, drain and source metal was evaporated on the top of NWs and backside of the substrate, respectively.
As for vertical transistor using InAs nanowire-channel, measured current was normalized by using the outer perimeter of the gate metal (240 nm). The performances of device are summarized as follows; average SS was 90 mV/dec, threshold voltage ~ 0.60 V, and on-off ratio, Ion / Ioff reached to 104 in average. The drain current was 1.50 mA/mu;m at VDS of 0.90 V. The transconductance was 1.5 mS/mu;m at VDS of 0.90 V. These highly conductance of InAs nanowire channel would be good candidate material for future HEMTs on Si substrates.
[1] K. Tomioka et al., Nano Lett., 8 (2008) 3475.
[2] K. Tomioka et al., Nature 488 (2012) 189.

The semiconductor industry is placing increasing emphasis on emerging materials and devices that may provide solutions to short term extensions of Si CMOS, as well as end-of-the-CMOS-roadmap problems beyond 2020. Near term, Ge and III-V high channel mobility materials are attractive replacements for Si CMOS, but unfortunately Ge or InGaAs MOSFETs have not lived up to their promise, partly because of problems with the gate dielectric interface. We will discuss, for instance, novel Atomic Layer Deposition (ALD) schemes for BeO gate dielectrics for InGaAs NMOS, and ALD gate dielectrics for Ge:C strained channel PMOS.
Less evolutionary pathways to extending Si CMOS may include graphene because it has carrier Fermi velocities higher than other semiconductors. However, since graphene is gapless, these graphene FETs (GFETs) have high OFF-state leakage and non-saturating drive currents which is problematic for digital logic, but attractive for high frequency analog device applications. The remarkable electronic properties of graphene can also lead to novel beyond-CMOS logic devices, such as single particle Interlayer Tunneling-based FETs (ITFETs), and many-body tunneling based Bilayer pseudoSpin FET (BiSFET), which can potentially be a low power replacement for the MOSFET. We will discuss how, once again, ALD gate dielectrics are key to fulfilling this vision. Since graphene is chemically inert, there are challenges with seeding ALD layers for GFETs and ITFETs which will be discussed.

Ferroelectric (FE) negative capacitance (NC) phenomenon can be utilized to reduce the power dissipation in MOSFET below the fundamental limit. [1] Experimental evidence of ferroelectric negative capacitance has recently been reported by multiple groups. [2,3] In the recent proof-of-concept demonstration of negative capacitance, we showed that for a given ferroelectric material system, the negative effect appears in a certain temperature range, which is closely related with the Curie temperature of the ferroelectric material.[3] In order for the negative capacitance to be technologically viable for CMOS applications, two critical questions need to be addressed: (1) is there a CMOS compatible crystalline ferroelectric material system can provide negative capacitance effect at the MOSFET operating temperatures? (2) Can the NC effect be achieved in sub-10 nm thickness regime of ferroelectric thin films? In this talk, we address both of these questions by experimentally demonstrating negative capacitance in the sub-10nm thick monocrystalline ferroelectric, (Ba0.8Sr0.2)TiO3 (BSTO) for the first time.
Superlattice heterostructures of ferroelectric BSTO and dielectric LAO was fabricated on GdScO3 (GSO) and DyScO3 (DSO) substrates via pulsed laser deposition. It was observed that the capacitance of a LAO (5nm)/BSTO (6nm) x 10 times and a LAO (2.9nm)/BSTO (7.5nm) x 10 times superlattices both of them grown on GSO substrates was larger than that of the constituent dielectric LAO at room temperature. This confirms that the constituent FE BSTO layers in both samples act as negative capacitors at room temperature. The effects of epitaxial strain, thickness and Curie temperature of the ferroelectric layer on the negative capacitance temperature range of the bilayer and superlattice heterostructures are investigated both theoretically experimentally. The role of these different factors will be discussed in this talk.
References:[1]S. Salahuddin et al., Nanolett. 8, 405 (2008) [2] A. Rusu, IEDM, 2010. [3] A. Khan et al., APL, 101 (2011).

The insertion of ultra-thin dielectric layers is known to lower n-type Schottky barrier heights. The mechanism is shown to require both the creation of a net interfacial dipole, and unpinning of the Fermi level by suppression of metal-induced gap states [1,2]. The existence of a net dipole requires a lack of cancellation of dipoles at the two interfaces. This requires a different metal (Ge)-O bond density at the two interfaces [3]. This in general requires a different oxygen chemical potential on each interface which is not trivial to accomplish. This would need the inserted dielectric to be a diffusion barrier, not just able to create dipoles, favoring the use of Al2O3 based or nitrided dielectrics. The conduction band offset is also important, favoring TiO2, a balance must be struck to involve both factors.
1. R R Lieten, et al, J Electrochem Soc 158 H358 (2011)
2. A M Roy, J Lin, K C Saraswat, IEEE ED Letts 31 1077 (2010)
3. L Lin, H Li, J Robertson, APL (2012); Microelec Eng 88 1461 (2011)

Tantalum alloys are currently investigated as possible gate electrode materials on high-k dielectrics for advanced CMOS nodes. Because of the reduced thickness of the gate layers (below 2nm), the interaction with underlying insulator is of great importance regarding the metal deposition parameters, especially when plasma is involved. In a previous work [1], interaction of Plasma Enhanced Atomic Layer Deposition (PEALD) Tantalum Carbo-Nitride (TaCN) with Hafnium Oxide (HfO2) was studied and it appeared that low Equivalent Oxide Thickness (EOT) and good current leakage gain at low thermal budget can be obtained by carefully tuning plasma conditions. Angle-Resolved X-Ray Photoelectron Spectroscopy (ARXPS) highlighted metal/dielectric interaction with increase of O in PEALD-TaCN at HfO2 interface and apparition of N in HfO2 layer after metal deposition.
Metals are known to oxidize post deposition at vacuum break, resulting in a degradation of the electrical characteristics [2]. Because deposition of an in-situ oxygen barrier has a lot of constraints, PEALD-TaCN affinity with oxygen, demonstrated on HfO2, could be a way to address this problematic. So in the current work, a 2nm PEALD-TaCN was deposited on top of 2nm PVD TiN / 2nm ALD-HfO2. XPS material characterization after each deposition step was achieved to assess TiN and HfO2 modifications. First, it is confirmed that PVD-TiN shows little interactions with HfO2, together with an important oxidation of TiN induced by air break. Then, after PEALD-TaCN deposition, XPS measurements evidenced that O content in the TiN layer is strongly reduced, together with an increase of N content. PEALD TaCN deposition parameters (temperature, reactant gaz, plasma gaz, plasma) were investigated to separate their contributions on the observed reduction of oxygen in TiN inter layer.
Electrical results (EOT, ΔVfb and the gain in current leakage) were extracted on simple capacitor devices. An EOT as low as 8.3 Å was obtained with a 2 nm HfO2/2 nm TiN/2 nm TaCN stack. The low EOT obtained in this work may be explained by PVD-TiN protection of HfO2 from PEALD-TaCN plasma degradation. It also appears that TaCN avoid further oxidation of TiN, when samples are taken to atmosphere which insures no EOT increase. The obtained electrical results with 8.3 Å EOT, P+ gate electrode ΔVfb = +0.25 eV and a reduction of current leakage by a factor of 105 compared to SiO2 reference satisfy the ITRS specifications at low thermal budget for sub-20nm advance node.
[1] F. Piallat, et al., Microelectronic Engineering, in press (2012)
[2] H. Cichy, et al., Thin Solid Films, Vol. 195 (1991)

Aggressive scaling laws for advanced CMOS integration nodes require the use of a low thermal budget metal electrode to meet the right work function (WF) for both P and N MOSFETS. With its good stability on high-k, titanium nitride allows to achieve low EOT values and good WF adapted to PMOS side (4.8-5.1eV) at low thermal budget (<500°C). Aluminum-based metals deposited on TiN/HfO₂ have shown low WF (4.3-4.1eV) relevant for NMOS transistors with a low EOT (0.85-1nm) associated to TiN oxygen scavenging [1,2]. In these studies, it is stated that work function shift is induced by aluminum diffusion through TiN towards the TiN/HfO₂ interface which is not the case in the present study. Aluminum may have another effect in terms of stabilization of the gate which is the topic of the present work.
We report here on the behavior of aluminum alloyed with titanium deposited on TiN/HfO₂ at low thermal budget (<500°C). Very low work-function (4.2 eV) and EOT = 0.83 nm have been extracted on dedicated capacitors structures which consist in Physical Vapor Deposited (PVD) TiAl/TiN on Atomic Layer Deposited (ALD) HfO₂ gate stack. To understand the n-type WF value obtained, material characterizations using STEM-EDX and back side ToF-SIMS were conducted. Even if aluminum diffusion was observed, it is not present at the TiN/HfO₂ interface. This result suggests to consider other issues than the one reported in [1, 2]. Complementary back side XPS analyses indicate that a redistribution of nitrogen between TiAl and TiN attesting sub-stoichiometric TiN_x formation could explain the low WF. Moreover, same aluminum-free Ti/TiN stacks with TiN_x (x<1) formation show aggressive scavenging with a total reduction of oxygen present not only in the SiO₂ interlayer (IL) but also in the high-k oxide at low thermal budget which is not observed with aluminum. We believe that alloying aluminum with titanium stabilizes the high-k/metal stack with respect to oxygen and subsequently avoids an aggressive scavenging of HfO₂ and SiO₂ (IL). One possible mechanism will be described during the conference.
In conclusion, we controlled oxygen scavenging using TiAl that enables very low EOT (0.83 nm) while keeping a low WF adapted to advance N-MOS gate-last transistors.
1.C. L. Hinkle et al. APL 100, 153501 (2012).
2.A. Veloso et al. 2011 Symposium on VLSI Technology Digest of Technical Papers.

For SiON/poly-Si gate stack, the impact of oxide thickness scaling on reliability parameters has been studied throughout many technology generations, revealing ever shrinking reliability margins because of the performance driven thinning of the SiO(N) dielectrics [1]. This reliability driven scaling limitations were expected to be largely overcome by introducing physically thicker high-k dielectric (HK) in combination with metal gates (MG) in HKMG MOSFETs [2-4]. However, in practice, thickness scaling with SiO(N)/HfO₂/TiN dual-oxide gate stacks - the industry-preferred HKMG stack - is again driven by SiO(N) Interfacial Layer (IL) thinning, because the HfO₂ layer is already kept near minimal thickness. [7] In this paper, the impact of IL scaling on the negative and positive bias temperature instability (NBTI and PBTI) and on time dependent dielectric breakdown (TDDB) are closely related to the fundamental properties of the dual-layer HKMG stack. It is argued that the rapidly shrinking reliability margins with IL thickness scaling will continue to drive a technology road map which relies less on oxide thickness scaling. The recent early introduction of FINFET devices in the 22 nm node can be viewed as an example, where performance can be boosted with less aggressive oxide scaling to meet reliability requirements.
Acknowledgments: This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.
[1] E.Y. Wu, et al., Semiconductor Sci. Technology 15, 425 (2000).
[2] M. Chudzik, et al., VLSI, pp. 194-195 (2007).
[3] K. Mistry, et al. IEDM, pp. 247-50 (2007).
[4] S. Pae, et al., IRPS, p. 499 (2009).
[5] K. Choi, et al., VLSI, p. 138 (2009).
[6] T. Ando, et al., IEDM, p. 423 (2010).
[7] E. Cartier, et al., IEDM (2011) and Refs. therein.

Dynamic random access memory (DRAM) is used as the main memory of every modern computer, due to its high density, high speed and efficient memory function. The major requirements for next generation of DRAMs are high capacitance density, low equivalent oxide thickness (EOT<1nm), low leakage current density (J<10-8 A/cm2) and low thermal budget (500-600 oC).To fulfil these requirements high dielectric constant materials (K>80) are necessary. Rutile-TiO2 is considered a promising material for capacitors in future generations of DRAMs since the rutile phase exhibits very high dielectric constant, ranging from 90 to 170, depending on the lattice orientation.
However rutile often coexists in thin film form with lower dielectric constant TiO2 phase, i.e., anatase, thereby resulting in the reduction of effective dielectric constant. Post deposition annealing at temperatures above 800 °C has to be performed to obtain pure rutile phase films. This thermal budget is unacceptable for DRAM process. However, the growth of pure rutile films at low temperatures can be stabilized by choice of an appropriate substrate. RuO2 exhibits high conductivity, high work function (5 eV) and crystallizes in the rutile structure with the lattice parameters close to that of the TiO2 rutile phase. So RuO2 is considered as promising electrode material for TiO2 based capacitors.
In this work we report the synthesis and characterization of rutile TiO2 films and also fabrication and characterization of MIM capacitors .Titanium dioxide thin films have been synthesized on Ru/Si substrates using pulsed DC Magnetron sputtering at room temperature. The electrode material (Ru) has been deposited by RF-sputtering. Spectroscopic ellipsometer has been used to measure the thickness and optical constants of the films. Raman spectromicroscopy and FTIR were used to study the crytallanity of the films. XPS and RBS were used to charactrerize the composition of the films. AFM and optical profilometer were used to measure the surface roughness and film thickness. SEM was used to measure the topography and grain size. MIM capacitors (Ru/TiO2/Ru/Si and Ru/TiO2/Ru/TiO2/Si)) were fabricated using shadow mask with 300 µm x 300 µm as the area of the capacitors. The devices were characterized by C-V and J-V measurements using Agilent LCR meter (4294A) and semiconductor device analyser.
AFM, optical profilometer, and SEM studies show the films have smooth surfaces. XPS and RBS data show that the films are stoichiometric and compositional uniform. Raman and FTIR spectra show the presence of all the modes corresponding to pure rutile TiO2. The dielectric constant of these films was as high as 130 at 100 KHz. High capacitance densities (49 fF/µm2) and low EOT (0.7 nm) have been achieved. We have fabricated rutile TiO2 based MIM capacitors with high capacitance density and sub-nm EOT at room temperature.

It has been shown [1,2] that perovskite oxides SrTiO3 and BaTiO3 (BTO) can be grown
epitaxially on Si and Ge, respectively. It would be interesting to achieve the reverse, i.e. to
grow for example, Ge on BTO. It is not known, however, whether one can achieve wetting of
BTO by Ge. The surface energy of Ge(001) varies widely depending on surface reconstruction
and passivation layer, and the surface energy of BTO(001) also varies depending on both, the
termination and chemical environment. The key piece of information is the energy of the Ge/
BTO interface that is difficult to determine experimentally. Using density functional theory,
we examine eight possible Ge/BTO interface structures (six of them with Ge as the substrate
and two with BTO as the substrate) and calculate their energies to determine which one has the
lowest energy, and whether wetting can be achieved. We also examine the valence band offsets
for each structure, and compare the theoretical values with photoemission data.

Current commercial metal-insulator-metal (MIM) devices that rely on SiO2, SixOyNz or Si3N4 based dielectrics have been engineered to exhibit very good performance characteristics but the maximum capacitance density is limited by the upper limit of their dielectric constants (k ~4-7) thus preventing the miniaturisation of analog circuitry at the same rate as its digital counterpart. To combat this deficiency a drive to develop materials with far higher k values has ensued, however despite a wide range of high-k materials being achieved to date these materials do not exhibit the leakage, charge trapping, stability and reliability properties that are essential for commercial utilization.
In this study we demonstrate for the first time that atomic layer deposition can reliably produce a stable HfxSi1-xO2 capacitive material [1] that fulfils ITRS capacitor requirements [2]. Data is presented for a wide range of MIMCAP devices on Si/SiO2 isolation substrates with oxide thicknesses ranging from ~2 nm to ~350 nm and combinations of Al, Ti, TiW and Pt as top and bottom electrode materials [3].

We have demonstrated that when growth conditions are carefully selected a unique set of combined material properties is produced that elevate it above the current state of the art for capacitive materials. The material system presented exhibits a k value of ~17, negligible charge trapping, a high breakdown electric field (7.5 MV/cm) and an effective zero alpha (quadratic voltage coefficient of capacitance) while exhibiting low leakage current density at device operating voltages [3]. Furthermore, the material exhibits these excellent properties as grown and demonstrates CMOS temperature processing compatibility (le;1050°C) removing the bottleneck to integration of high-k passives with CMOS. In this paper we highlight the advantages achieved by the ALD material growth, the material properties and the applications potential in a range of devices including analog mixed signals (AMS) units, capacitive tuning, radio frequency devices, micro electro-mechanical systems (MEMS) and dynamic random access memories (DRAM).
[1].Monaghan S, and Povey, I. M.: ‘A High Dielectric Constant, Linearly-Behaved, Capacitor and Method for Making Same&’, Patent application filed on 21 October 2011; European Patent Office number EP11186166.2; and United States of America Patent Office number 61549751. PCT filed 21st October 2012.
[2].The International Technology Roadmap for Semiconductors: 2011 Edition; Potential solution for RFAMS in 2018 and beyond; RF MEMS in 2014 and beyond; and DRAM in 2017 and beyond. http://www.itrs.net/Links/2011ITRS/Home2011.htm
[3]. S. Monaghan, I. M. Povey, Electron. Lett., 48 (4), 230-232 (2012)

Higher carrier mobilities, lower bandgap and lower melting point of Germanium (Ge) compared to Silicon enable drive current, supply voltage reduction and lower thermal budget requirements for logic technology scaling. This has resulted in significant research interest in Ge CMOS. [1] A key challenge in Ge CMOS is the thermal and chemical stability of the Ge-oxide (GeO2) interfacial layer (IL) used for gate stack passivation.[2] Nitridation of Ge-oxide IL (GeON) improves the thermal and chemical stability. Additionally, it reduces gate leakage and increases the dielectric constant which benefits EOT scaling. [3]Thermal nitridation of Ge-oxide IL results in high nitrogen concentration at GeON/Ge interface that can increase interface state density (Dit) and degrade channel carrier mobility (µ).[4] Decoupled plasma nitridation (DPN) of Si-oxide IL has been shown to control the nitrogen profile in the IL [5] which improves SiON/Si interface properties.
In this work, we compare the impact of thermal nitridation versus Decoupled Plasma Nitridation (DPN) on the GeON/Ge interface properties such as nitrogen concentration ([N]), Dit and µ. Continuous Wave DPN (CW-DPN) nitridation versus thermal nitridation of Ge-Oxide IL for P and N Ge channel FETs shows that CW-DPN results in higher carrier mobilities and lower Dit at the Ge/GeON interface as compared to thermal nitridation. This is likely due to the lower nitrogen concentration at the Ge/GeON interface for the CW-DPN process as seen in Angle Resolved X-ray Photoelectron Spectroscopy (ARXPS) measurements. Thermal stability of the CW-DPN GeON IL is similar to that of the thermally nitrided GeON IL. [6] Further, impact of Pulsed Wave DPN (PW-DPN) nitridation on the GeON IL properties is explored. By reducing the kinetic energy of ions striking the wafer surface, PW-DPN has been shown to create less damage resulting in improved reliability and mobility performance of SiON IL as compared to CW-DPN SiON IL. [7] The PW N2 plasma is studied using a Langmuir probe to extract parameters such as normalized electron temperature and average ion density for key pulse parameters like duty cycle and power. Impact of PW-DPN process on Dit at GeON/Ge interface is studied through capacitor fabrication and electrical measurements, and correlated to the plasma parameters and the nitrogen profile in the IL as obtained from ARXPS spectra. Finally, a comparison of GeON performance for thermal vs. CW and PW DPN is presented.
References:
[1] K. C. Saraswat et al., Microelectronics engineering 80, 15 (2005). [2] K. Kutsuki et al., Appl. Phys. Lett.95, 022102 (2009). [3] T. Sugawara et al., J. Vac. Sci.Technol.B 24, 2442(2006). [4] Chi On Chui et al., IEEE Trans. Electron Dev.53, 1501(2006). [5] H. H. Tseng et al., IEEE Electron Device Lett.23,704(2002). [6] K. Chaudhuri et al., IEEE SISC (2012). [7] A. Veloso et al., ESSDERC (2003).

Recently, III-V MOSFETs with high drain currents (I_ds1mA/µm) and high transconductances (gm>1mS/µm) have been achieved at sub-micron channel lengths (L_ch), thanks to the better understanding and significant improvement in high-k/III-V interfaces. However, to realize a III-V FET at beyond 14nm technology node, one major challenge is how to effectively control the short channel effects (SCE). Due to the higher permittivity and lower bandgap of the channel materials, III-V MOSFETs are more susceptible to SCE than its Si counterpart. The scaling of planar devices stops at around 150nm L_ch. The dramatic increase in DIBL beyond 150nm indicates severe impact from 2D electrostatics. Therefore, the introduction of 3-dimensonal (3D) structures to the fabrication of sub-100nm III-V FETs is necessary. In this talk, we will review the materials and device aspects of III-V 3D transistors developed very recently [1-3]. We will also report some of new progress by demonstration of 20-80 nm channel length III-V gate-all-around nanowire MOSFETs with EOT=1.2nm and lowest SS=63 mV/dec [4]. The total drain current per pitch can be further enhanced by introducing 4D structures [5].
1. Y. Q. Wu et al. IEDM Tech. Dig. 331 (2009).
2. M. Radosavljevic et al., IEDM Tech. Dig. 126 (2010).
3. J. J. Gu et al. IEDM Tech Dig. 769 (2011).
4. J. J. Gu et al. IEDM Tech Dig. A (2012).
5. J. J. Gu et al. IEDM Tech Dig. B (2012).

Since the electron and hole mobilities in Ge are considerably greater than those of Si, MOSFETs fabricated on epitaxially grown Ge on Si are being considered as an alternate to conventional Si MOSFETs. For high-mobility Ge transistors integrated on Si substrates, managing dislocations and integrating a suitable gate dielectric have become an important engineering challenge. Herein, we focus on epitaxially grown n-type Ge-on-Si substrates to demonstrate the performance of p-MOSFETs. The defect density in Ge obtained from etch pit density measurements is consistently below 1×10⁶ cm^-2. In addition to the etch pit density, our x-ray diffraction and high-resolution transmission electron microscopy results support the crystalline quality of Ge epitaxially grown on Si. To avoid the ion-implantation damage, the epitaxial growth parameters are suitably chosen to auto-dope the Ge layer and turn it into n-type (phosphorus). The electron mobility of the Ge layers is obtained from Hall measurements, and it ranges from 800 to 1250 cm²/V-sec depending on epitaxial growth parameters. The Ge layer thickness is ~2 µm, and the gate length is 2.5 µm. p-MOS capacitors are fabricated to characterize the quality of the gate stack: Ti/HfO₂/germanium-oxynitride/n-Ge. The reverse leakage current density is below 10^-6 A/cm² at 300K. In this presentation, we will also report capacitance-voltage and interface trap density measurement results and compare them with 2D device simulations performed by TCAD software. In addition, we will report effective carrier mobility that exists in the inversion channel as a function of epitaxial Ge crystalline quality. Lastly, we will perform RF linearity analysis on our p-MOSFETs as a function of Ge layer thickness and crystalline quality. In summary, wafer-scale, epitaxial Ge on Si is used to fabricate high-hole-mobility p-MOSFETs, while suitable doping in the Ge layer is achieved by optimizing growth parameters, and as a result ion-implantation induced damage is avoided.

In the field of CMOS device fabrication the world is looking into new ways to reduce the leakage of today&’s capacitors and transistors. One theory on how to reduce leakage current is High K dielectrics. There are a number of High K dielectrics already known in this field. In our research, we aimed to optimize the growth of hafnium Oxide (HfO2) on III-V semiconductors. In these experiments we varied the growth temperature and thickness of the oxide layer. All of our growths were performed using the Atomic Layer Deposition (ALD) and water was used as our Oxygen source in depositing the oxide layers. We compare electrical results with the growth of Aluminum oxide and Zirconium oxide on the same semiconductor substrates. An important step in optimizing the growth of HfO2 for device use is the cleaning of the substrate. In our case, we use Gallium Arsenide (GaAs) and Indium Gallium Arsenide (InGaAs) substrates in order to see the differences, if any, in the growth kinetics of our High K dielectric. GaAs and InGaAs have high electron mobility carriers. We believe since both of them have high electron mobility carriers it will work better then Silicon, which is used in many high power and high frequency electronics today. GaAs also works in the terahertz region where as Silicon actually fails. But with GaAs and InGaAs being great uses for substrates, they contain a lot of interfacial issues. The major problem with both substrates is the different native oxides located on the surface. Since the substrates have these oxides present we have constructed a protocol to reduce the presence of the native oxides and grow high K material.

Research in the CMOS field is growing more and more over the years. The aim for this type of research is to produce capacitors and transistors with reduced leakage current and reduced interface trap density. While doing both of these things the device should also maintain acceptable capacitance. In our research, we study the effect of combining two high K dielectrics by using an Atomic Layer Deposition (ALD) system. In order to test the capabilities of the device, we preform electrical characterization and compare the results. In the electrical characterization we preformed capacitance vs. voltage (C-V), capacitance vs. frequency (C-F), and also current vs. voltage (I-V). We combined the oxide layers of Aluminum and Zirconium in order to produce Zirconium aluminate. In addition, we vary the concentrations of Zirconium to Aluminum to optimize what percentages work best for the composite. We compare the results of the composite to Zirconium oxide on the same substrates. In this research effort, we utilize GaAs as well as InGaAs because of their high mobility electron carrier properties. In using these two III-V semiconductors as substrates we encounter interfacial issues. GaAs contains seven separate interfacial oxides some of them including; GaO, AsO Ga2O3 etc. We have compiled a cleaning method including wet chemical cleaning and a self-cleaning by the ALD that we believe this is the best method in reducing the native oxides found on the surface of the substrates. We test their performance by X-ray Photoelectron Spectroscopy (XPS) studies. If these native oxides were not reduced, problems within the devices will be seen.

In the literature, it shows that cyclic D2O plasma treatments in the atomic layer deposition (ALD) high-k (HK) oxides can effectively improve electrical properties due to the purification and densification of HK layers. Besides, surface D2O plasma treatment on substrate can prevent growth retardation and create reactive sites for precursor adsorption at the initial ALD cycles. On the other hand, we know that the native oxide of Ge will cause the degradation of gate dielectrics. Therefore, suppression of GeOx and GeO2 became an important issue in Ge metal oxide semiconductor (MOS) devices. In this article, we fabricate cyclic D2O plasma treatments on HfO2 films and surface D2O plasma treatment on p- Ge (100) substrate by radical-assisted atomic layer deposition (RAALD).
The samples with cyclic and surface D2O plasma treatments show better electrical properties than the sample without treatment, because of high quality HfO2 films and better surface quality. It shows higher capacitance density, lower equivalent oxide thickness (EOT), and lower leakage current density, respectively. Furthermore we also investigate the physical properties of the films by X-ray photoelectron spectroscopy (XPS), X-ray diffraction (XRD), X-ray reflection (XRR) and transmission electron microscopy (TEM) to realize the mechanism of cyclic and surface D2O plasma treatments in Ge MOS devices.

Metal-insulator-metal (MIM) capacitors are used as memory capacitors in DRAM applications. The ITRS specifies increasing capacitance density (>7 fF/mu;m²), decreasing leakage current density (<10^-8 A/cm²), sub-nm effective oxide thickness (EOT), and low processing temperatures (<400 ⁰C) for MIM capacitors. Many high-k materials (Al₂O₃, HfO₂, ZrO₂, Ta₂O₅) have been used as dielectrics in MIM capacitors. These materials have medium dielectric constant values (k), thus limiting the maximum capacitance densities that can be achieved from these devices. Many higher-k dielectrics (TiO₂, SrTiO₃) have also been used. While the capacitance densities of these devices are higher, these lower bandgap materials are responsible for higher leakage current densities due to their low barrier offsets at the metal-dielectric interfaces. Therefore, a combination of medium-k and high-k dielectric stacks is suitable to achieve high capacitance density and low leakage current density.
In this work, we report the fabrication of MIM capacitors with dielectric stacks of TiO₂/ZrO₂/TiO₂, TiO₂/ZrO₂/Al₂O₃/ZrO₂/TiO₂, and TiO₂/ZrO₂/Al₂O₃/ZrO₂/Al₂O₃/ZrO₂/TiO₂ (TZT, TZAZT, and TZAZAZT) to improve the device performance and the stress reliability. The dielectric stacks were deposited on TiN-coated Si substrates by ALD at 250 ⁰C. Thickness of the dielectric stacks ranged from 7.5 nm to 9.6 nm. Top electrode stack of 10 nm-TiN/50 nm-W/10 nm-TiN was deposited by CVD, and patterned (area~10^-4 cm²). The fabricated devices were characterized by C-V and J-V measurements using Agilent LCR meter (4294A) and semiconductor device analyzer (B1500A), respectively. We discuss the device performance and suitability of these MIM capacitors for DRAM applications, and evaluate the conduction mechanisms in TZT, TZAZT, and TZAZAZT stacks at different electric field regimes. We also study the reliability characteristics of these devices.
High capacitance densities (~46 fF/mu;m²), and sub-nm EOT (<0.76 nm) were obtained for the fabricated devices. Low leakage current densities of about 4.9×10^-8 A/cm², 5.5×10^-9 A/cm², and 9.7×10^-9 A/cm² (at -1 V) have been obtained for TZT, TZAZT, and TZAZAZT dielectric stacks, respectively. Leakage current mechanisms at low and high electric fields were dominated by Schottky and Poole-Frenkel conduction, respectively. Temperature-dependent J-V characteristics were performed, and barrier/trap heights were extracted and correlated with the device characteristics of the fabricated capacitors. The effects of constant voltage and constant current stress (CVS and CCS) on the electrical characteristics of the fabricated capacitors were studied, and excellent device reliability was demonstrated. A ten-year operating voltage of about -1.5 V, and very low ΔC_stress/ C of about 1.1 % (at -3 V) were achieved. Device data obtained for the fabricated capacitors were found to be better than the reported data in recent literature, and exceed the ITRS specifications of 2018 and beyond.

In order to enable the world wide effort for continued scaling (Moore&’s law) of MOS structures in logic devices and MIM structures in memory devices, we have developed a promising inter-lanthanide oxide based high-k material LaGdO₃ (LGO) with higher linear permittivity (~22), larger band gap (5.6 eV), and sufficient electron (2.57 eV) and hole (1.91 eV) barrier heights with silicon. A series of thin films of LGO with various thicknesses were grown on HF treated Si (100) substrates by pulsed laser deposition to evaluate their performances for high-k applications. To achieve sub-nanometer equivalent oxide thickness (EOT), the interfacial layer (IL) thickness in LGO/Si hetero-structures were minimized by careful selection of the deposition parameters and conditions. Cross sectional HRTEM images of scaled gate stacks revealed a non-abrupt and structure-less IL of ~ 6 Å. The asymmetrical O1s XPS spectra were de-convoluted in to three components corresponding to three different chemical compositions viz. M (metal) -O-M (530.75 eV, FWHM 1.4 eV), M-O-Si (532.15 eV, FWHM 1.8 eV), and Si-O-Si (533 eV, FWHM 2.3 eV) and confirmed the formation of La-Gd silicates of moderate high-k at the interface due to inter-diffusion of La and Gd to SiOx and/or Si in to LGO. The forming gas passivated n-MOS device with the lowest EOT about 8.4 Å without quantum mechanical correction has an unsaturated (due to ultra thinness), close to ideal C-V curve with V_fb 37 mV, threshold voltage V_t 1.1V, a negligibly small hysteresis 2 mV (ΔV_fb between sweeps), and interface trap density D_it 6 X 10¹² cm^-2 eV^-1. Gate leakage current conduction mechanism of these devices was investigated by recording the temperature dependent J-E characteristics in the 300 - 450 K range. Gate injection current was dominated by Schottky emission below 1.2 MV/cm and quantum mechanical tunnelling above this field. The physical origin of substrate injection was found to be a combination of Schottky emission and trap assisted tunnelling. Leakage current densities of various LGO/Si ultra thin films with EOT le; 1.75 nm are at least four or more orders lower than the proposed ITRS requirements and SiO_x/Si heterostructures at -1V of applied gate voltage. These studies reveal that LGO could be one of the strong candidates for the future logic technology nodes.

The structural properties of a-HfO2/Ge(2x1)-(001) and a-ZrO2/Ge(2x1)-(001) interfaces were investigated with and without GeOx interface passivation using density-functional theory (DFT) molecular dynamics (MD) simulations. Realistic amorphous a-HfO2 and a-ZrO2 samples were generated using a hybrid classical-DFT MD “melt-and-quench” approach and tested against experimental properties demonstrating good reproducibility of major properties, such as coordination distribution, radial distribution function, average coordination numbers, and bandgap. For each high-K/Ge stack type, two systems with single and double interfaces were investigated. Every stack was annealed at 800K, cooled to 0K and relaxed to the ground state giving the system enough freedom to form realistic interface. Since standard DFT underestimates semiconductor bandgaps, the simulated stacks were recalculated with HSE06 hybrid-functional giving much more accurate electronic structure analysis and bandgap representation.
All stacks were free of midgap states but some had band-edge states. The band-edge states were mainly produced by deformation, intermixing, and bond-breaking creating improperly bonded semiconductor atoms. The comparison of bandgaps for a-HfO2/Ge and a-ZrO2/Ge systems against stacks with passivation (a-HfO2/O(2ML)/Ge and a-ZrO2/O(2ML)/Ge) indicated that inclusion of O(2ML) passivation interlayer generally decreases the stack bandgap roughly from ~0.7 eV to ~0.4-0.5 eV. Stacks with oxides directly bonded to Ge(100), (a-HfO2/Ge and a-ZrO2/Ge) showed no intermixing nor any significant Ge deformation. Conversely, the stacks with O(2ML) passivation interlayer demonstrated significant deformation and intermixing both at O(2ML)/Ge interface and interface between high-K oxide and O(2ML)/Ge substrate. These deformation and intermixing were mainly caused by thermal oxidation of Ge. These interface intermixing and deformation are mainly responsible for bandgap shrinkage relative to oxide/Ge stacks without O(2ML) passivation interlayer. The results with the direct bonding of high-k to Ge(100) were compared with similar DFT-MD simulation of the medium-k a-Al2O3/Ge(001); the a-HfO2/Ge(001) interface had the best electronic structure.

The DFT-MD simulations show that electronically passive interfaces can be formed directly between high-k dielectrics and Ge if the processing does not induce defects because on a short time scale the interface spontaneously forms electrically passive bonds as opposed to bonds with midgap states. The results show that if optimized processing is achieved neither a GeO2 passivation layer nor a a-Al2O3 passivation layer is required to form an unpinned interface.

InGaAs is being explored as an alternative channel material for n-type devices. It is desirable to be able to use ion implantation to dope the contacts to this channel material. In other materials (e.g. Si) amorphization and the subsequent dopant activation observed upon solid phase epitaxial growth is critical to maximize dopant activation. The effect amorphization has on the activation of Si+ implanted into In0.53Ga0.47As is studied as part of a program to better understand contacts to this alternative channel material. 600 nm of In0.53Ga0.47As was grown using MBE on lattice matched InP. Si+ was then implanted at 20 keV to a fluence of 6E14cm-2. Additional samples were implanted with two implants of Si at 20keV to a fluence of 6E14cm-2 followed by an As+ implant at 180 keV to a fluence of 3E14cm-2. As-implanted XTEM showed that the samples at room temperature were amorphized from the surface to slightly below the peak of the Si projected range. The subsequent As implant incorporated the entire Si layer into an amorphous layer. The samples were capped with 100 nm of PECVD SiO2 to prevent surface degradation caused by arsenic evaporation during annealing. Annealing consisted of 5 second rapid thermal annealing sequences (RTA) in 100°C increments from 350°C to 850°C to activate the implant. After annealing, the SiO2 cap layer was removed with BOE before electrical measurements were performed. The mobility, sheet number, and sheet resistance were measured with Hall effect using the van der Pauw method and TEM micrographs were used to investigate the underlying microstructure of the In0.53Ga0.47As upon implantation and after subsequent anneals to correlate the presence of defects with bulk electrical properties. TEM micrographs show that the amorphous layer is completely regrown after a 350°C RTA. The stacking fault density was around 7.2E10/cm2 and they originated at the amorphous/crystalline interface. Despite earlier reports of stacking fault instability, these stacking faults were observed to be very stable up to 850°C anneals. Electrical activation is observed at 550°C and maximizes at ~10% of the implanted dose after 850°C. This activation occurs well after SPEG is complete and thus SPEG is not seen to be responsible for the activation. An even greater delay in activation is observed with the fully amorphized sample further confirming that SPEG does not activate the dopant. In fact, the increased temperature necessary for activation suggests amorphization results in Si existing on sites that discourage dopant activation (possibly more stable clusters). It is concluded that to maximize dopant activation and minimize defect density, amorphization should be avoided when doping InGaAs.

Using first-principles density functional theory calculations, we have investigated the O vacancy formation and the relevant induced defect states in hafnium oxides and Hf-silicates (Hf1-xSixO2) over a wide range of chemical compositions (x=0~1). The PBE0 hybrid density functional was employed for the analysis of the electronic properties and the charge transition levels of the O vacancy in HfO2, hafnon (HfSiO4), and in amorphous Hf-silicates, respectively. Based on our generated structure models, eight typical kinds of O coordination structures were identified in amorphous Hf-silicates. Our calculated results showed that the positions of the induced defect energy levels in the band gap and the formation energies of O vacancy are largely determined by the local structures of the vacancy sites, which appear to be nearly independent of the chemical composition of amorphous Hf-silicates. Our calculations also showed that O vacancy can possess the negative-U behavior in crystalline HfSiO4 but not in amorphous Hf-silicates, where most of the O vacancies can simply exhibit the negative-U behavior as they were in the positive charge states. Given the measured band offset of 3.40 eV between Si and amorphous Hf-silicates, a considerable number of O vacancies were found to prefer staying in the charge neutral state as the Fermi level lies within the band gap region of Si. Furthermore, due to its relatively higher formation energy, the concentration of O vacancy in Hf-silicates can be much lower than that in m-HfO2 when the Fermi level lies within/below the mid-gap region of Si. Accordingly, a much reduced flat band voltage shift and less transient threshold voltage instability can be found in Hf-silicates as compared with m-HfO2, which indicates that a Hf-silicate layer formed at the interface between HfO2 and the Si substrate could be beneficial to the performance of the CMOS device. Furthermore, we will also discuss the effect of the La incorporation into these HfO2-based high-k gate dielectric materials, particularly on the electronic properties of the O vacancy induced defect states and the associated changes in their charge ionization levels.

Propagation of electrically active defects in high dielectric constant (k) oxide materials affects the reliability and performance degradation in many devices, including MOSFETs and DRAMs in today&’s and future technology nodes. Over the past decade, a good understanding of energetics and the diffusion mechanisms of existing isolated point defects has been achieved for many popular high-k materials. Much less understood are the mechanisms of new defect formation in strong electric fields. Defect formation is of particular importance for emerging non-volatile memory technologies that directly utilize the changes in defect concentration introduced by the near-breakdown values of the electric field. Here, we perform first-principles calculations to determine the energy profile for Frenkel defect formation (displacing a lattice atom to an interstitial position). Both local and Hubbard-corrected density functionals (LDA and GGA+U) are used in combination with the nudged-elastic-band method. We analyze how the diffusion barriers for both oxygen and cation Frenkel pair formation change upon the application of an external electric field, and how the field may affect the preference for interstitial vs. exchange diffusion mechanisms. For Ti Frenkel pair in rutile TiO₂ in the absence of an external field, the dynamically stable Ti interstitial position is the octahedrally bonded site (a/2,0,c) away from the Ti vacancy. Contrary to some earlier reports, we find that Frenkel pairs with Ti at the octahedrally bonded (a/2, 0, c/2) and the tetrahedrally bonded (a/2, 0, c/4) sites are dynamically unstable. The diffusion barriers in rutile TiO2 are strongly asymmetric, and the defect energies vary substantially (order of 1eV) with pair separation. We discuss the difference between Frenkel defect energy profiles between TiO₂ and other high-k materials, such as HfO₂. The obtained hierarchy of Frenkel pair energies is important for understanding the experimental data on annealing out the defects caused by an electric stress at different temperatures.

III-V compound semiconductor based quantum well field effect transistors are in general viewed as a promising transistor candidate for future high-speed low-power logic applications due to their excellent drive current performance at low voltage. In this presentation, I will review recent device developments of n-channel InGaAs transistors. To start, well-studied Schottky gate device architecture is adopted to demonstrate integration on Si substrate as well as to establish performance advantages over state-of-the-art Si NMOS at VCC=0.5V. To enable further LG scaling, high quality high-K dielectric is integrated and non-planar Tri-gate architecture is implemented. I will conclude by discussing InSb based p-channel device results, as well as InGaAs based tunnel FETs.

There are some recent atomic layer deposition(ALD) studies on III-V substrates which have demonstrated “self-cleaning” effect. It is the reduction of surface oxides occurred upon the exposure of precursor during the ALD process.^[1-3] And for Ge substrate, few reports has been investigated, however, they only demonstrated the structural effects of self-cleaning surface treatment.^[4] The self-cleaning surface treatment by TMA is a simple process of the exposure of TMA precursor to Ge substrate. In this study, to investigate the chemical and electrical effect of self-cleaning surface treatment on Ge substrate by trimethylaluminum(TMA), 9 nm HfO₂ were deposited on both of non-treated and TMA-treated Ge substrate by in-situ ALD. The Hf was carried out using TDMAHf as a Hf precursor through bubbler system with Ar and H₂O as a reactant. Then, the post deposition annealing with N₂ gas and 400°C made the defects lower. And the evaporated Al was used as a metal electrode. These MOS capacitors with varying ALD conditions have been examined mainly focusing on the chemical and electrical properties. In first part, for verifying the chemical effects of treatment, we compared the MOS capacitors with XPS analysis, which demonstrated the self-cleaning effect reduced thermally instable GeO₂. In second part, we measured C-V and I-V curves to investigate the electrical effects of treatment. With increasing time of self-cleaning process, the D_it value was reduced due to self-cleaning effect and the dielectric constant was also decreased by the formation of very thin Al₂O₃ layer.
[1] Young-Chul Byun et al., Journal of The Electrochemical Society, 159 (1) G1-G5 (2011)
[2] C. L. Hinkle et al., Appl. Phys. Lett. 92, 071901 (2008)
[3] M. L. Huang et al., Appl. Phys. Lett. 87, 252104 (2005)
[4] M. Milojevic et al., APPLIED PHYSICS LETTERS 95, 212902 (2009)

HfO₂ has been used for high k material on Si. However, HfO₂ alone is unsuitable on Ge substrate due to Ge diffusion into HfO₂.[1] Since La₂O₃ has high dielectric constant(about 25), large band gap(4.8~6.0eV) and good thermal stability, it has been proposed as high k on Si. Moreover, there is a recent report that solid solution LaGeO can interrupt indiffusion of thermally instable Ge.[2] Also doped HfO₂ have been introduced as a substitution of higher k material on Si. La doping case keeps HfLaO amorphous up to 900°C and, moreover, enhances dielectric constant.[3]
For fabrication of Ge MOS capacitors, high k films were deposited by thermal and plasma-enhanced atomic layer deposition(Th-&PE-ALD). TDMAH[tetrakis(dimethylaminoHafnium] and La(iPrCp)₃[tris(isopropyl-cyclopentadienyl)Lanthanum] were used as Hf and La precursor, respectively, which showed clean evaporation with no residue. For Th- and PE-ALD, H₂O and O₂ plasma were used as oxidizing reactants. The process exhibited ALD mode with good self-saturation behavior and linear growth without any nucleation delay on Ge as a function of growth cycles. After the formation of ALD HfO₂, La₂O₃, HfO₂/La₂O₃ and Hf_1-xLa_xO₂(x=0.11, 0.2, 0.33, and 0.5) on Ge, in order to investigate the effect of La incorporation, high-k layer/Ge samples were annealed by N₂ at various temperatures during 10 minutes. Also post deposition annealing(PDA) with a certain temperature resulted in partial crystallization of films and reduction in interface state density(D_it), hysteresis and leakage current density. Then a metal electrode was evaporated with Al on the top of ALD high k layer.
The chemical composition, binding structure, and carbon contamination of samples were analyzed by x-ray photoelectron spectroscopy(XPS). And the microstructures of films were analyzed by x-ray diffraction(XRD). The electrical properties were evaluated by capacitance-voltage(C-V) and current-voltage(I-V) measurements.
These comparative studies on high k with different compositions and structures on Ge showed that La incorporation with HfO₂ increased both thermal budget of Ge CMOS fabrication and dielectric constant by molar volume change through phase transformation, compared to HfO₂. Above 400°C which is the limitation of temperature for Ge since GeO₂ not only decomposes into GeO_(s) but also desorbs as GeO_(g) into oxide, La incorporated MOS capacitors had almost same properties below 400°C, but only HfO₂ MOS capacitor didn&’t. And especially, Hf_1-x La_xO MOS capacitor with x of 0.33 had highest k value among them(~21) with low leakage currents(5.6x10^-8A/cm²@V_fb=-1V). For thinner EOT and thermal stability, HfLaO can be an expected option as a future high k material on Ge substrate in semiconductor industry as coming the end of Si-based semiconductor.
Reference [1]Yoshiki Kamata et al., JJAP,44,4B,2323-2329(2005) [2]A. Dimoulas et al., Appl.Phys.Lett.96,012902(2010) [3]A. Toriumi et al., ECS Trans.(5)185-197(2006)

Gate dielectric deposition and post-dielectric thermal processing during III-V MOS device fabrication can result in undesirable chemical reactions at the dielectric/channel interface. We examine the oxidation of an In0.53Ga0.47As (100) surface through overlying ultrathin atomic layer deposited (ALD) Al2O3 layers. The Al2O3 layers (1 nm ~ 2.5 nm) were deposited at a substrate temperature of 270°C by atomic layer deposition and post-deposition anneals were performed under ultra-high purity oxygen ambient at atmospheric pressure. X-ray photoelectron spectroscopy (XPS) measurements using a monochromatic Al Kα were conducted to investigate whether the InGaAs surface is oxidized through the overlying ALD-Al2O3 during the O2 anneals.
Weak indium oxide (In2O3) and arsenic oxide (AsO, As2O3) features are detected in the XPS In 3d and As 3d spectra, and a strong gallium oxide (Ga2O3) feature is observed in the Ga 3p spectra after the 500°C O2 anneal for 20 min, whereas no oxidation of the substrate is detectable for any of the Al2O3 thicknesses investigated. The effect of ALD-Al2O3 layer thickness on 500°C InGaAs oxidation is also investigated. The ratio of the peak intensity of Ga-oxide component and the total peak intensity of Ga 3p core level near the InGaAs surface is reduced from 41% to 17% when the Al2O3 thickness increases from 1 nm to 1.7 nm. With 1.7 nm Al2O3, no detectable As-oxide and In-oxide are observed in the XPS spectra. When the oxide layer is 2.3 nm thick, no Ga-oxide is detected in XPS.
When 1 nm Al2O3/InGaAs is annealed under oxygen ambient at temperatures in the range from 300°C to 550°C, the XPS Ga 3p features shift to higher binding energy (possible interface defect formation) and the peak shapes evolve in a fashion consistent with increasing Ga-O bonding when this Al2O3/InGaAs sample is annealed in O2 at 500°C or higher. Band-edge photoluminescence peak intensity from 1.2 nm Al2O3/InGaAs is greatly reduced with increasing O2 anneal temperature, consistent with increasing oxidation at higher anneal temperature leading to interface trap formation.
We also investigate InGaAs surface oxidation through a 1.2 nm ALD-Al2O3 when H2O vapor is pulsed for 10 seconds at 300°C. Without extra water vapor pulse after the ALD-Al2O3, no detectable As-oxide and Ga-oxide features were found and very small amount of In2O3 was observable in XPS core level spectra. The ALD-Al2O3 with extra water vapor dose shows As-oxide and Ga-oxide features in the XPS As 2p and Ga 2p spectra and increased peak intensity of In-oxide compared to the Al2O3 without an additional water pulse.

Epitaxially grown Ge and III-V on Si have emerged as a promising candidate for the next generation of high-performance devices, including high-mobility FETs and read-only memory. In this study, we have investigated the device characteristic of p-MEFETs fabricated on Ge epitaxially grown on Si. We have focused on the effect of dislocation density (2×10⁷ - 2×10⁸ cm^-2) in Ge and the effect of dielectric layer (SiO₂, Al₂O₃, and HfO₂) inserted between metal contacts and Ge. The thin dielectric layers (5 - 30 nm) are intended to unpin the Fermi level. The hole mobility improves with decreasing dislocation density up to 1025 cm²/V-sec at an average carrier density of 10¹⁷ cm^-3. Among the three dielectric layers, a 30-nm-thick HfO₂ layer provides the best Schottky characteristics with a reverse leakage current on the order of 10^-10 A per mu;m², an on/off ratio of 3×10³, and an interfacial trap density of 6×10¹¹ cm^-2/eV. With HfO₂, we also observe the low-field peak effective hole mobility to be 310 cm²/V-sec. An external transconductance of 7 mS/mm is obtained from the our optimized MEFETs, where the transistor gate length is 2.5 mu;m, and the channel width is ~170 nm. The effective peak mobility obtained from our optimized MESFETs shows enhancement factors of 2.8 and 1.23, relative to bulk-Si universal mobility and recently reported mobility obtained with strained Ge, respectively.

EOT scaling is one of the most critical challenges for future Ge-MOSFET technology. It is difficult to achieve sub-1 nm EOT with a single dielectric material, due to the intrinsic trade-off between dielectric constants and band gaps. Recently, bilayer high-k materials, such as TiO2/Al2O3, HfO2/Al2O3, have been paid increasing attention. However, there are several challenges remaining for bilayer high-k stacks on Ge substrate: 1) an ultra-thin high-quality GeO2/GeOx layer is generally reported to be necessary for effective Ge surface passivation, but this is difficult to obtain by routine thermal oxidation. It has been reported that processes such as post-dielectric deposition plasma oxidation are beneficial for preparing such interface layers. 2) The interface between the two high-k materials in the bilayer must be abrupt and their thicknesses well-controlled, which is required for reducing gate leakage as the EOT is scaled. In this paper, we address these challenges by a simple, low-temperature process flow using thermal annealing. Using carefully-controlled atomic layer deposition (ALD) of the dielectric layers and a forming gas anneal (FGA), a TiO2/Al2O3/Ge gate stack is demonstrated with EOT = 0.63 nm that achieves low Dit and gate leakage current density in MOS capacitors. Pt gated Ge-pMOSFETs with TiO2/Al2O3 gate stacks are fabricated, and have a sub-1nm EOT, 75 mV/dec subthreshold swing, 10uA/um on state current and avoid gate metal/TiO2 reaction or interdiffusion.
The dipole between TiO2 and Al2O3 on a Ge(100) substrate is experimentally investigated. Using ALD without a vacuum break between oxide depositions, we are able to control the layer thickness and quality and deposit uniform thin films. Samples with multiple Al2O3 and TiO2 layers are fabricated to investigate formation and cancellation of a charge dipole at the TiO2/Al2O3 interfaces. Existence of an oxide/oxide dipole is consistent with trends in the flat band voltage and gate leakage current density observed for ALD-grown layered dielectric stacks with varying number, order and thickness of the two oxide layers. Comparisons to prior reports of dipole effects in MOS gate stacks, particularly at metal oxide/SiO2 interfaces, will be discussed.

Germanium with its higher carrier mobility than silicon, in conjunction with a ferroelectric material like barium titanate (BTO), is an excellent candidate for ferroelectric field effect transistors with applications in nonvolatile logic and memory devices. We report the epitaxial growth of BTO directly on a Ge(100) substrate. First, ½ monolayer of strontium metal is deposited on a clean Ge surface as a passivation layer at 600°C. Molecular oxygen to a pressure of 5x10^-6 torr is then introduced while barium and titanium are alternately deposited on the substrate at the same temperature. The BTO film is crystalline as-deposited and remains so throughout the growth as monitored by in situ reflection high energy electron diffraction. High resolution scanning transmission electron microscopy shows a well-defined interface between BTO and Ge with minimal interface oxidation. X-ray diffraction measurements of BTO films show only substrate peaks and (h00) peaks of BTO, indicating an in-plane ferroelectric polarization. This is expected due to the thermal expansion mismatch of BTO and Ge. We will report on efforts to induce out of plane polarization of BTO films grown on Ge. We have also measured the valence band offset between BTO and Ge using x-ray photoelectron spectroscopy (XPS) and found it to be 2.6 eV, resulting in a zero conduction band offset. We compare this value to density functional calculations of the band offset and remark on possible ways of increasing the conduction band offset.

To minimize the oxide-semiconductor interfacial defect density in Ge MOSFET, a proper passivation layer must be used before the oxide layer is deposited. The passivation layer must be very thin, ideally one monolayer, to allow for increased scaling of the equivalent oxide thickness (EOT). H2O provides a well-ordered chemisorption monolayer (ML) of HO-Ge and H-Ge sites at room temperature without disrupting surface Ge atoms if it is deposited on a clean oxide-free Ge(100). XPS data shows a Ge surface prepulsed with H2O(g) has double the aluminum coverage compared to a TMA only dose. However, since H2O chemisorption results in equal density of Ge-H and Ge-OH sites on the Ge(100), H2O can only provide a maximum of 0.5 monolayer of Ge-OH sites, limiting the TMA nucleation density. STM shows the saturation H2O dose resulted in 0.85 ML coverage of -OH and -H species chemisorbed on the surface. Unreacted portions on the surface are seen as bright STM features which are attributed to single or double dangling bond sites. STS measurements show dangling bond sites have energy states in the band gap consistent with the presence of dangling bonds. Conversely, STS measurements of the H2O sites show the conduction band edge dangling bond states are eliminated due to the passivating Ge-OH and Ge-H bonds. This room temperature dosed H2O/Ge surface can activate TMA chemisorption on the surface and forms an ordered structure when annealed. However, if the H2O/Ge surface is annealed prior to TMA dosing, it can be seen that the Ge-OH and Ge-H sites on the surface have limited thermal stability.
A saturation dose of HOOH(g) on Ge(100) results in a coverage of 0.95 ML of Ge-OH species chemisorbed on the surface, which is more than double that of the H2O surface. Only a few sites on the surface are unreacted dangling bond sites. Ge-OH sites on the HOOH dosed surface passivate the conduction band edge dangling bond states, while the few dangling bond sites show energy states in the band gap. In contrast to the H2O passivated surface, this HOOH passivated surface has increased thermal stability; annealing the surface to 100°C generated no additional dangling bonds while the oxygen coverage remains constant to within 10%. The improved coverage of Ge-OH sites allows for increased nucleation density of O-Al bonds and also minimizes the dangling bonds which are considered as the major source of interfacial trap states (Dit). The improved thermal stability allows for an increased thermal budget during ALD cycles. An STM image of the HOOH/Ge surface dosed with TMA and subsequently annealed shows the formation of an ordered layer on the surface while STS of the surface demonstrating it is unpinned and has no states in the band gap. This ordered TMA/HOOH/Ge surface can serve as an ideal template for further high-k oxide deposition.

We compare the value of HfO2, LaGeOx, HfGeOy, GeNx and Al2O3 as passivating gate dielectrics for Ge surfaces. We argue that a key role is as a barrier against O vacancy diffusion through the GeO2, inhibiting defect generation at the Ge-oxide interface. Al2O3 is preferred for this role, whereas nitrides have too low a band offset. HfGeOx can phase separate, leaving HfO2 through which O vacancies and Ge could diffuse. LaGeOx causes flat-band shifts of undesired polarity, whereas GeNx has a small valence band offset and band tail states.
Oxygen deficiency at Ge:GeO2 interface induces Ge-Ge bond which can re-arrange to form 3-fold bonded Ge site and 3-fold bonded O site. The Ge 3-fold site state lies at the Ge valence band edge, while O 3-fold site can give an anti-bonding state near the Ge conduction band edge. Thus both sites act as trap. While the oxygen vacancy at the interface of Ge:HfO2 will relax into a direct Hf-Ge bond which gives gap state pinning Fermi level at the upper gap.
Producing a well passivated Ge interface is to avoid these two defects. We consider introducing metal germinate layer. The epitaxial interface models of Ge:La2GeO5 and Ge:HfGeO4 are built. In both interfaces, Ge are fully tetravalent. The calculated valence band offset (VBO) for La2Ge2O7 is 3.0 eV, for La2GeO5 is 3.0 eV and for HfGeO4 is 3.0 eV. The calculated bulk band gap in sX of La2Ge2O7 is 5.0 eV, La2GeO5 is 5.0 eV, and HfGeO4 is 5.5 eV. Thus, by from their band gaps, the CBO of all these oxides is larger than 1.0 eV.
We have used the calculated energy of separating La2Ge2O7, La2GeO5 and HfGeO4 into their component binary oxides and the known lower melting temperature of GeO2 to produce phase diagrams of LaGeOx and HfGeOx systems by scaling from those of the silicates. This shows that HfGeOx will have the same spinodal decomposition into HfO2 and GeO2 phases, but at lower temperatures. However, LaGeOx will have no spinodal decomposition over the main part of its composition space because of the greater germanate-forming tendency of La. Spinodal depositions of HfGeO4 into HfO2 allows percolation path for O vacancy diffusion across the film.
La also has problems. La2O3 will lead to an n-type flat band voltage shift, so this solution is not useful for p-type FETs, and the reaction of La is too strong, removing the GeO2 completely. This makes an abrupt Ge:LaGeOx interface, placing remote phonon and Coulombic scattering centers against the channel, so reducing carrier mobility. Ge3N4 like Si3N4 has much lower diffusion rates and also resists O diffusion. But VBO of Ge:Ge3N4 is only 1.0 - 1.1 eV, which is too small. Note that Ge3N4 like Si3N4 will have a strong valence band tail, whose states will act as hole traps when the VBO is small. Al2O3 is left as remaining dielectrics. It is good oxygen diffusion barrier with large band offset. Ultrathin Al2O3 diffusion barrier combined with High K oxides like TiO2 and HfO2 will be viable dielectrics.

Current Status of NAND Memory
Recently, as NAND memories achieve small cell size, high-speed programming and low Power operation, NAND memories success to replace a part of market of Floppy Disk, DVD, HDD, and recently make many new business markets such as MP3 Player and mobile tablet, etc.
However, the scaling of NAND memories becomes to be difficult by interference phenomena. Moreover, process cost of smaller cell fabrication becomes very expensive and the number of endurance cycles decreases from 1000000 times to 1000 times. Therefore, it is very difficult to replace high volume HDD by current NAND memories, as scaling speed of NAND memories saturate. Moreover, as the scaling speed of NAND memories is faster than the developing speed of lithography, the scaling of NAND memories is limited with lithography trend at 1X nm generation.
3D NAND Technology
- Stacked Vertical NAND Memory -
From viewpoints of overcoming the above issues of conventional NAND memories, stacked vertical NAND memories [1-6] had been proposed. Its cell array structure is three-dimensional (3D) memory array architecture [1]-[3]. The proposed architecture can use all 3D space sufficiently without scaling technology. The structure of the proposed cell arranges bit line contact, first select gate, 2 Vertical type memory cells, second select gate and source line in series vertically in one silicon pillar. The Vertical type memory cell is structured that floating gate and control gate surround the silicon pillar. All devices for the proposed cell are vertically stacked in one silicon pillar, therefore, the stacked vertical structured cell does not need additional area such as bit line contact, 2 select gates and source line, while conventional NAND structured cell needs this additional area. As the number (N) of stacked memory cells in one silicon-pillar increases, the stacked vertical structured cell can reduce to cell area per bit in proportion to 1/N. As a result, the stacked vertical structured cell can realize a drastically smaller cell area per bit than the smallest reported NAND structured cell. The stacked vertical structured cell consisting of 2 stacked memory cells is fabricated. As recently, many type memory cell based on our stacked vertical structured cell technology has been proposed such as BiCS [7] and TCAT [8] with charge trap type cell. Moreover, for realizing high reliable stacked vertical cell, ESCG [9], DC-SF [10], S-SCG [11] and SCP [12] with floating gate type cell was proposed.
From all, 3D NAND memories with the stacked vertical structured cell technology become main technology in future nano-generation high density nonvolatile memory.
[1]T.Endoh, et al. IEICE Trans. Vol.E81-C, No.9, pp.1491, 1998.
[2]T.Endoh,et al. IEEE J. Solid-State Circuits,Vol.34,No.4, 1999.
[3]T.Endoh et al IEEE Trans. ED, Vol.48, No.8, pp.1599, 2001.
[4]T. Endoh, et al, IEDM, pp33-36, 2001
[5]T.Endoh, et al. IEEE Trans. ED, Vol.50, No.4, pp.945, 2003.
[6]T.Endoh, et al. 2006 IWDTF, pp. 115 - 116, Nov.8-9, 2006
[7] H. Tanaka, et al, VLSI Symp., pp14-15, 2007
[8] J.H. Jang, et al, VLSI Symp., pp192-193, 2009
[9] M.S. Seo and T.Endoh, IMW, pp146-149, 2010
[10] S.J. Whang, et al., IEDM, pp668-671, 2010
[11] M.S. Seo and T.Endoh, IMW, pp61-64, 2011
[12] M.S. Seo and T.Endoh, IMW, S2-5, 2012

AlGaN/GaN high electron mobility transistors (HEMTs) are of significant interest for high power, high frequency and high temperature devices due to large band gap, high mobility, and stability compared to other high mobility III-V materials. However, large leakage currents and frequency dependent current collapse degrades the performance of AlGaN/GaN HEMTs. The fabrication of metal-oxide-semiconductor HEMTs or hetero-field-effect-transistors (MOS-HEMTs or MOS-HFETs) by incorporating a high-k oxide layer between the semiconductor and the gate metal is one of the proposed methods to improve the performance of AlGaN/GaN HEMT devices. The oxide layer could play a role in reducing leakage current, potentially improving mobility by preventing degradation of the semiconductor surface. At the same time, the oxide layer could prevent current collapse by suppressing electron trapping at surface states, providing increased reliability of MOS-HEMT based devices. Hafnium dioxide, having a relatively large dielectric constant (k asymp; 20) as well as a large band gap with sufficient band offsets to ensure good device characteristics is a candidate oxide for this purpose and is already employed in the latest generations of silicon based semiconductor devices.
In this study we investigate the growth of HfO2 on Al0.25Ga0.75N surface by atomic layer deposition (ALD), electron beam evaporation (Ebeam) in oxygen and rf sputtering method using a HfO2 target. X-ray photoelectron spectroscopy (XPS) is used to determine interface states between the HfO2 and the Al0.25Ga0.75N surfaces. These deposition chambers and XPS chamber are connected by transfer tube, therefore the XPS is carried out in-situ by transferring the samples in UHV conditions (< 2 x 10-10 mbar) to prevent contamination due to atmospheric exposure.
This work is supported by the AOARD under AFOSR Grant No. FA2386-11-1-4077.

Gate dielectrics for nitride heterostructures have attracted interest due to recent efforts to reduce the leakage current in GaN-based high electron mobility transistors (HEMTs). High-k gate dielectrics enable the gate capacitance to be increased while reducing the leakage current. However, the preparation of device-quality high-k/nitride interfaces is still major obstacle for future GaN metal oxide semiconductor field effect transistors (MOSFETs) for power applications. Despite the importance of high-k/GaN interfaces, charges and interface passivation at the interfaces have not yet been extensively studied.
Here we first present the location and nature of fixed charge states in high-k/GaN metal-oxide-semiconductor capacitors (MOSCAPs) structures from flatband voltage shifts in high frequency capacitance-voltage measurements. We show that significant positive fixed charges present at Al₂O₃/GaN interfaces, but not at HfO₂/GaN interfaces. Moreover, we observe an abrupt shift in the flat band voltage in the bilayer dielectrics, which indicates that an interfacial dipole is created at HfO₂/Al₂O₃ interfaces in the bilayers. This result will be discussed in the context of energy band diagrams of MOSCAPs. We also present the effect of the plasma pretreatment for the interface passivation in high-k/GaN MOSCAPs from frequency-dependent capacitance-voltage measurements. We show that N₂ plasma treatment improves the frequency dispersion in depletion regime, which is closely related to midgap states in bandgap. We will discuss this result in terms of the role of the N₂ plasma and describe the influence of the chemical bonding in the high-k/GaN interfaces.

Lattice matched InAlN/GaN HEMTs have drawn attention due to their promising electronic and thermal properties. However, for high-voltage applications, the gate leakage current under reverse bias remains a serious challenge affecting the reliability of these heterostructures. In this work first we accurately identify the reverse leakage current flow mechanism in these heterostructures by taking polarization field into account. Subsequently to suppress this leakage a comprehensive characterization and interface analysis of InAlN/GaN HEMTs gate stacks with ALD Al₂O₃ of various thicknesses is presented.
The InAlN(7.5nm)/AlN(1nm)/GaN(2µm) HEMT structure was grown by metal-organic chemical vapor deposition (MOCVD) on SiC substrate at IQE RF LLC. Mesa isolation was performed followed by source/drain ohmic metallization using Ti/Al/Ni/Au (20/100/40/50 nm) stack deposition followed by rapid thermal annealing. Finally, Ni/Au (40/100 nm) gate metal stacks were deposited on this sample. The temperature dependent reverse bias J-V measurement on Schottky diode with radius 20 µm over a temperature range of 200K-350K was performed. Gate leakage Mechanism in InAlN/GaN HEMTs: From the measured data we find that the trap assisted tunneling (TAT) is the dominant mechanism at lower reverse biases (0 to -1V). However, unlike non-polar semiconductors (Si, Ge), the presence of built-in polarization field in the barrier of the III-Nitrides demands the modification of Frenkel-Poole-Emission (FPE) expression to accurately explain the experimental data. Using this modified FPE the relative high frequency dielectric constant ε_s and trap barrier height Phi;_t are extracted to be 6.2 and 0.48eV respectively. However, at higher bias voltages (-2.2V and beyond) the effective barrier for electron tunneling becomes triangular and it is seen that Fowler-Nordheim (FN) tunneling dominates over TAT. From FN plot, the surface barrier height and electron tunneling effective mass are extracted to be 1.5eV and 0.2m₀ respectively.
ALD/InAlN interface: To suppress the gate leakage current in these heterostructures, atomic layer deposited (ALD) Al₂O₃ is used as gate dielectric. Before gate metallization, different Al₂O₃ thicknesses (t_ox=0nm, 3nm, 6nm) were deposited on InAlN surface of three different samples by using TMA and H₂O as precursors. The gate leakage current decreased with increasing t_ox, the property that will enable high breakdown voltages in GaN HEMTs. However, the pinch-off voltage V_p increased with t_ox from -3.6 V for t_ox=0nm to -7.2V for t_ox=6nm. The increase in V_pwith t_ox over the 3 samples can be quantitatively explained by the existence of a fixed positive sheet charge Q_int~5x10¹³ cm^-2 at the (Al₂O₃/InAlN) interface. This charge can be attributed to the ALD oxygen atoms attaching to Al/In by substituting the nitrogen site thus by electron counting rules acting as a donor dopant.
These findings are expected to accelerate the choice of optimal gate stacks for nitride HEMTs.

High-κ on GaN based devices are a strong candidate for high temperature/high power and high frequency transistor applications because of the wide bandgap (3.4eV) and the large breakdown voltage of the semiconductor. The high-κ/GaN interface is central to the performance of the device - be it in the conventional metal oxide semiconductor field effect transistor structure, or the GaN/AlGaN/GaN high electron mobility transistor structure, where the top thin GaN cap protects the AlGaN surface. The characterization of the GaN/high-κ interface quality is therefore the focus of this work. In this case, we have focused on atomic layer deposited Al2O3 as the gate dielectric due to its good thermal stability, favorable band offset with GaN, and a dielectric constant of ~8 [1-3].
Capacitance voltage analysis is routinely used to characterize metal oxide semiconductor (MOS) structures [4]. However, the application of this technique to GaN with its aforementioned wide bandgap is not trivial. In this presentation, we will discuss the use of temperature dependant capacitance voltage measurements in order to characterise the Pd/Al2O3/GaN MOS structures. Using low temperature measurements (77 K), we will demonstrate that no border trap response exists for the Al2O3-GaN interface, unlike other Al2O3-III-V systems [5]. Using higher temperature measurements (500 K), we will discuss the use of the conductance and Terman methods for extraction of the interface state density at the Al2O3-GaN interface. We will present the limitations of the conductance method when working with a wide bandgap semiconductor, and discuss why the Terman method is more preferable in this case. We will also discuss the role of the pyroelectric charge in the piezoelectric material GaN and how this should be understood in electrical characterization of GaN-based metal oxide semiconductor structures [6].
[1] J. Robertson, “PHYSICAL J OURNAL, vol. 291, pp. 265-291, 2004.
[2] N. V. Nguyen et al., Applied Physics Letters, vol. 93, no. 8, p. 082105, 2008.
[3] R. D. Long and P. C. McIntyre, Materials, vol. 5, no. 7, pp. 1297-1335, Jul. 2012.
[4] E. H. Nicollian and J. R. Brews, MOS Physics and Technology. Wiley Classics Library, 2003.
[5] E. J. Kim et al., Applied Physics Letters, vol. 96, no. 1, p. 012906, 2010.
[6] Submitted to Applied Physics Letters, ‘Temperature-Dependent Capacitance-Voltage Analysis of Defects in Al2O3 Gate Dielectric Stacks on GaN&’, R. D. Long, A. Hazeghi, M. Gunji, Y. Nishi and P. C. McIntyre

Unlike conventional MOSFETs, the Tunnel FET (TFET) architecture employs a gate modulated Zener tunnel junction at the source which controls the transistor ON and OFF states. This scheme fundamentally eliminates the high-energy tail present in the Fermi-Dirac distribution of the valence band electrons in the p+ source region and allows sub-kT/q steep slope device operation near the OFF state. This allows Tunnel FETs to achieve a much higher IONminus;IOFF ratio over a small gate voltage swing. A major challenge in the demonstration of high performance Tunnel FET is the limited rate of tunneling across the Zener junction which results in low drive current. Fig. 4 illustrates the vertical Nanopillar Tunnel FET architecture used in the fabrication of the TFETs. Nanopillar Tunnel FET provides several features not accessible in conventional lateral device geometry. It allows incorporation of an asymmetric source drain configuration within the transistor structure where the source region composition can be markedly different from those of the channel and drain regions. This is vital for high performance Tunnel FET which requires a heterojunction source, abruptly doped source and channel tunnel junction, precise alignment of the gate edge with the source-channel tunnel junction, ultra-thin body and double gate or surround gate configuration, but requires suppression of gate induced channel to drain tunneling. Recently, we have experimentally demonstrated III-V Nanopillar Tunnel FETs using both homojunction and heterojunction tunnel source regions. The results show, for the first time, that the on-current bottleneck in Tunnel FETs can be overcome by careful bandgap engineering.
Acknowledgement: This work was supported by Intel and NRI/SRC through the Notre Dame MIND Center

High Electron Mobility Transistors (HEMTs) formed from AlGaN/GaN heterostructures are poised to become the technology of choice for a large cross-section of microwave circuit applications. There is a need to understand and model the failure mechanisms of these devices if they are to be widely accepted. This study corelates some of the defects observed by SEM and TEM with the electrical properties of stressed devices. In this study, AlGaN/GaN HEMTs were formed by Metal-Organic Chemical Vapor Deposition of 2.5 µm of Fe-doped GaN on 6H:SiC substrates followed by a 3nm AlN nucleation layer. Next 15nm of Al0.28Ga0.72N and n-GaN capping layer were grown by by Molecular Beam Epitaxy resulted in the formation of the Two Dimensional Electron Gas (2DEG) of the HEMT device. Ohmic contacts to the 2DEG were formed by the deposition of a Ti/Al/Ni/Au metal stack which was annealed at 850C for 30s in order to reduce contact resistance. The gate contact of each device was formed by the successive deposition of Ni and Au with variable gate geometries. The challenge of studying device degradation is the stochastic nature of the defects that form under the gate. In order to better understand changes that occur under the gate metal during stressing, an etching scheme has been developed which removes the passivation and gate metal and contact layers without etching the AlGaN or forming etch pits along the threading dislocations. After the initial degradation in gate leakage is observed, deprocessed devices exhibited a previously unreported defect which appears in SEM as a band of contrast under the entire gate length and width. AFM measurements indicate a 2 nm expansion of the AlGaN under the banded gate. This banding defect has also been observed after thermal stressing of the devices from 500C to 600C. High resolution TEM compositional analysis of the degraded region will also be presented. There appears to be a strong correlation between degradation in gate leakage and the formation of these banding defects.

The structural and electronic properties of amorphous a-Al2O3/GaN(0001) interfaces were investigated by density-functional theory (DFT) molecular dynamics (MD) simulations for various GaN surface terminations (Ga- or N-polar), with or without Ga adlayer and O passivation. Realistic amorphous a-Al2O3 samples were generated using a hybrid classical-DFT MD “melt-and-quench” approach and tested against experimental properties demonstrating good reproducibility of major properties, such as coordination distribution, radial distribution function, average coordination numbers, bandgap. Every stack was annealed at 800K, cooled to 0K and relaxed to the ground state giving the system enough freedom to form realistic interface. Since standard DFT underestimates semiconductor bandgaps, the simulated stacks were in addition recalculated with HSE06 hybrid-functional giving much more accurate electronic structure analysis and bandgap representation.
The GaN surface was simulated both with GaN(0001)(Ga-Polar) and GaN(000-1)(N-Polar) surface reconstructions. The DFT-MD simulations of a-Al2O3/GaN(0001) (Ga-Polar) interface revealed predominantly Ga-O bonding with no intermixin; however, this system had multiple band-gap states. Similar simulations of a-Al2O3/GaN(000-1) (N-Polar) interface demonstrated N-O and N-Al bonding pattern with a bandgap free of midgap states. Since nearly all GaN surfaces are prepared with a Ga adlayer, the previous systems were simulated with Ga-adlayer and DFT-relaxed prior to the oxide stacking. The inclusion of Ga-adlayer resulted in an oxide/semiconductor bonding formed both by O-Ga and Al-Ga bonds and multiple midgap states mainly from metal-metal (Al-Ga) bonds and semiconductor undercoordinated atoms. To eliminate metal-metal bonding the Ga-adlayer/GaN(0001)(Ga-polar) and Ga-adlayer/GaN(000-1)(N-polar) surface was passivated by reaction with O to simulate typical oxidation processing. Afterwards, the new oxidize surface was stacked to a-Al2O3 sample and DFT-MD annealed at 800K, cooled and relaxed. The obtained interface eliminated practically all metal-metal bonds and demonstrated better band-gap than a-Al2O3/Ga-adlayer/GaN(0001)(Ga-polar) and a-Al2O3/Ga-adlayer/GaN(000-1)(N-polar), but these were still inferior to the a-Al2O3/GaN(000-1) (N-Polar) interface. This interface is superior because nitrogen atoms readily forms strong covalent bonds to both metal atoms (Al) and oxygen atoms thereby providing the most favorable interface to amorphous oxides.

GaN-based power transistors have superior material properties, which result in a higher power density and efficiency; however, these devices are also plagued by a large concentration of defects at the interface between the gate and GaN, resulting in a large leakage current and current collapse, which degrade device performance. This research investigates the role of these defects at the oxygen-terminated GaN surface and Al2O3/GaN interface. Since GaN has a large spontaneous polarization, there is a negative and positive bound sheet charge at the Ga- and N-face, respectively, ~2.1x10^13 charges/cm2. Left uncompensated by external defects at the surface, this would correspond to ~3.4 eV upward band bending at the Ga-face and small downward band bending at the N-face.
Experimental results, on the other hand, showed that there must be heavy external charge compensation; the n-type Ga- and N-face GaN had 0.3-0.8 eV and 0.3-0.4 eV upward band bending, as determined by in-situ x-ray and ultraviolet photoemission spectroscopy (XPS and UPS). Such band bending corresponds to ~2x10^13 charges/cm2 at the surface. This was after the samples were cleaned with an initial ex-situ wet chemical clean and in-situ 650°C H2/N2 plasma annealing to remove carbon. These samples did retain ~2 ML of oxygen. The surface defects, which could, therefore, include structural defects, surface contamination or additional charges, heavily compensated the polarization-induced charge, causing a decrease in the depletion layer at the Ga-face and hole accumulation at the N-face.
The band alignment was also investigated at the Al2O3/GaN interface with XPS and UPS. The VBOs were 1.8 eV and 1.6 eV for Al2O3/Ga- and N-face GaN, which are consistent with calculated values based on charge neutrality level model about amorphous Al2O3. The band bending after deposition was ~0.8 eV on Ga- and N-face. The increase in band bending was likely a result of the oxygen plasma used in the deposition process. After deposition the samples were annealed, the band bending decreased to ~0.3 eV. Subsequent exposure to oxygen plasma and annealing confirmed that this process was reversible. This would suggest that the oxygen plasma process changed the GaN surface band bending by inducing ~4x10^11 charges/cm2 acceptor-like defects, most likely at the Al2O3/GaN interface.
In other words, Al2O3 provided sufficient band offsets on Ga- and N-face GaN as gate insulator; these band offsets were not significantly affected by direction of the polarization induced charge or the oxygen plasma treatments, suggesting that neither of these factors significantly affect the interface bonding at the Al2O3/GaN interface.
This research was supported by the ONR through the DEFINE MURI program, N00014-10-1-0937.

Introduction: Ternary oxides offer special opportunities as gate oxides for group III nitride transistors. Their high permittivity κ allows an increase in the normalized capacitance without any increase in leakage current. In the past several investigations of such gate stacks were already presented such as monoclinic Gd₂ O₃ on GaN [1] or AlGaN/GaN MISHEMT&’s (metal insulator semiconductor high electron mobility transistors) with amorphous LaLuO₃ as gate dielectric [2].
In this work first characteristics of GdScO₃ grown epitaxially on GaN are presented with respect to their structural and their electrical properties.
Experiment: A 3 µm thick n-doped GaN (0001) was grown epitaxially on α-Al₂O₃ (0001) by MOVPE (metalorganic vapor phase epitaxy). Subsequently thin layers of GdScO₃ were deposited epitaxially by pulsed laser deposition. The structural properties were investigated by Rutherford backscattering spectrometry (RBS) and x-ray diffraction (XRD). Al-contacts were deposited via shadow masks to characterize the stack electrically by CV- (capacitance voltage) measurements.
Results and Discussion: RBS in random and channeling mode yielded the stoichiometry and the thickness of the layer to be Gd:Sc as 1:1 and 20 nm, respectively. A minimum yield of about 50% proved a good crystallinity. XRD provided some information about the crystal structure. Apart from typical GaN and sapphire peaks the omega;-2theta;-scan revealed reflections at 30.5° and 63.6° which can only be related to the GdScO₃. A rocking curve scan around 30.5° showed a FWHM of 0.10°. Comparing this value to the 0.09° FWHM of the rocking curve of the GaN (0002) peak shows that GdScO₃ and GaN have the same crystal quality. The angle of 30.5° corresponds to a lattice parameter of 5.85 Å which fits quite well to the 5.75 Å of the b-axis of bulk orthorhombic GdScO₃ [3]. Further measurements will be shown and will clarify whether the other lattice constants fit the a- and c- axis (5.48 Å and 7.93 Å) of bulk GdScO₃ [3].
CV-measurements of an Al/GdScO3/n-GaN stack demonstrate MOS-like behavior with a maximum normalized capacitance of 1.08µF/cm². Assuming 16 nm of GdScO₃ from RBS, the κ-value is around 19.5 which fits the κ of the b-axis of GdScO₃ quite well [3].
Conclusion: First GdScO₃ layers grown on GaN exhibit high crystallinity and render themselves suitable as high-κ oxides on III-V semiconductors.
References:
[1] W. H. Chang et al., Journal of Crystal Growth 311 (7), 2183 (2009).
[2] Yang Shu et al., Electron Device Letters, IEEE 33 (7), 979 (2012).
[3] Sinisa Coh et al., Physical Review B 82 (6), 064101 (2010).

To integrate cross-point (4F^2) ReRAM device array, we need to develop bi-directional selector device to suppress the sneak current path through the unselected devices. Although various candidates with selector properties were recently reported, several problems such as insufficient current density at set/reset operations for nano-scale devices, low selectivity, and poor endurance have been raised.
In this paper, we report two types of selection devices, called the varistor-type bidirectional switch (VBS) and NbOx based threshold switching device with excellent thermal stability.
A highly non-linear VBS showed superior performances including high current density (>3x107A/cm^2) and high selectivity (~10^4). Ultrathin NbO2 exhibits excellent TS characteristics such as high temperature stability (~160C), good switching uniformity, and extreme scalability.

Since the gate pitch size of NAND flash memory has been shrunk into sub-20 nm technologies, a high quality tunnel oxide (Tox) is required to improve endurance characteristics. Generally, Tox has been grown by post-oxidation processed with thermal/radical oxidation and post-annealing in NAND flash memory area. In the previously reported papers, two-step oxidation was introduced to improve the roughness of a Tox/Si interface and electrical properties of Tox [1,2]. The two-step oxidation process is performed with first-half oxidation, intermediate-annealing, and second-half oxidation in consecutive order. In this study, the two-step oxidation process on a Si (100) surface is employed to obtain a high quality Tox and Tox/Si interface with low roughness mean square. Firstly, the Tox growth on the Si surface is calculated using technology computer aided design (TCAD) simulation, thermodynamically. After the two-step oxidation process, the grown Tox is more tensile stressed than that progressed by post-oxidation due to the intermediate-annealing process, while the Si surface is stressed more compressive. To confirm the interfacial state, the samples are analyzed by high resolution transmission electron microscopy (HRTEM), resulting that the Tox/Si interface processed with the two-step oxidation process shows low RMS. Since some defects, such as native vacancy/interstitial, hydrogen, and others, located in Tox (half thickness) and Tox/Si interface after the first-half oxidation process are easily moved to the Tox surface, the number of trap sites in Tox can be diminished. In conclusion, we fabricate a high quality Tox using the two-step oxidation process for NAND flash memory devices and this method shows possibilities for enhancing endurance characteristics.
[1] A. Bhattacharyya, C. Vorst, and A. H. Carim, Solid-State Sci. Tech., 132, 1900 (1985).
[2] J. Kim and S. T. Ahn, IEEE Electron Dev. Lett., 18, 385 (1997).

Since the gate pitch size of NAND flash memory has been shrunk into sub-20 nm technology the Si process condition and time should be controled and managed delicately. Especially, the reliability characteristics such as available program/erase cycles and retention are severely influenced by manufacturing processes. The effects of dopant elimination on reliability are investigated with the delay time during the manufacturing process. Since water (H2O) molecules are adsorbed on the surface when the surface of silicon oxide (SiO2) is exposed in the air, the threshold voltage of the cells is decreased due to the boron dopant elimination as increasing the delay time after capping SiO2 in NAND process. The adsorbed H2O molecules are dissociated to hydroxyl (OH-) and hydrogen ion (H+) on the surface, and then H+ bonds to a neighboring oxygen ion (O-2) to generate another OH- without any activation energy at room temperature [1]. Since a surface of Si active area is oxidized with the diffusion of the generated hydroxyls from the SiO2 surface, boron dopants located at the surface of Si active area are migrated to the SiO2 generated with oxidation enhanced diffusion mechanism [2]. Furthermore, the diffusion of boron dopants to the SiO2 is accelated by H+ of OH-. In summary, the reliability properties of NAND chips can be degraded due to the boron dopant elimination, which is originated from the oxidation of the Si active area with long delay time during the manufacturing process.
[1] M.-H. Du, A. Kolchin, and H.-P. Cheng, J. Chem. Phys., 119, 6418 (2003).
[2] K. Taniguchi, K. Kurosawa, and M. Kashiwagi, J. Electrochem. Soc., 127, 2243 (1980).

Defect generation and soft breakdown are critical reliability issues in high-k gate dielectrics for CMOS application. The same phenomena, on the other hand, are key enablers for resistive switching memory (RRAM) operation, where the resistance of a conductive filament (CF) is modulated by applying voltage pulses [1]. The CF is first generated by the forming operation, namely a controlled, low-current dielectric breakdown. The CF is then activated/deactivated through set/reset processes consisting of voltage-driven ion migration [2]. Both unipolar and bipolar switching operations have been observed, with bipolar switching generally displaying the highest reliability and capability of low-current operation. The details of the switching mechanism, such as the size of the CF and the ion-migration kinetics, dictate not only the RRAM operation, but also the memory reliability and the scaling limits of this technology. Therefore, an accurate physical picture of resistive switching is essential.
This talk will cover the basic concepts of bipolar switching in high-k oxides. First, the main material requirements for high-k oxides in RRAM, as opposed to high-reliability gate dielectric, will be summarized. Then, the switching processes will be illustrated through characterization results of HfOx and simulation results of ion drift/diffusion activated by the applied field and by the local Joule heating at the CF [3]. The universal switching, namely the independence of the characteristic set/reset voltages among most high-k oxides, will be evidenced through data from the literature and modelling results [4]. Complementary switching and the capability to control both the size and the direction of the CF in the set operation will be shown. Finally, the potential scaling issues will be summarized in terms of reliability issues and switching variability [5].
[1] H.-S. P. Wong, et al., Proc. IEEE 100, 1951 (2012).
[2] H. Y. Lee, et al., IEDM Tech. Dig. 297 (2008).
[3] S. Larentis, et al., IEEE Trans. Electron Devices 59, 2468 (2012).
[4] D. Ielmini, et al., IEEE Trans. Electron Devices 58, 3246 (2011).
[5] D. Ielmini, et al., Phase Transition 84, 570 (2011).

The use of the nanocrystals embedded high-k dielectric structure in nonvolatile memory devices has the advantages of low leakage current and high reliability [1]. Replacing SiO2 gate dielectric in the nano-size MOSFET with the ZrHfO high-k material can improve bulk and interface properties, such as lowering the EOT, increasing the crystallization temperature, lowering the interface state density, and increasing the effective k value [2]. Light exposure can affect the performance of the nanocrystals embedded high-k dielectric structure, which is critical to applications in commercial products. However, there are few studies on this topic until recently [2,3]. In this paper, the nc-MoOx embedded ZrHfO MOS capacitors were prepared on the p-type Si wafer using the one pump down process followed by the 800omicron;C post deposition annealing process. The ITO material was used as gate electrode because of its relative high band gap, high electric conductivity and high transparency in the visible region of the spectrum [3]. The nonvolatile memory characteristics were investigated using the C-V and J-V hysteresis curves. The fresh C-V curve of nc-MoOx embedded sample changed under light conditions while that of control sample, i.e., ZrHfO without the embedded MoOx, showed negligible change. When the gate voltage was swept from -7 V to +7 V to -7 V, a large flat band voltage of 0.607 V was obtained while a small value of 0.083 V was obtained in the control sample. The flat band voltage slightly increased under the light condition, and the C-V curves shifted to the positive gate voltage direction. The capacitor under green LED light exposure trapped slightly less holes than that under the red light exposure. The J-V curve showed significantly increase under the light exposure condition compared to that in the dark in the positive voltage range. A peak was observed in the J-V curve of the nc-MoOx embedded sample in dark due to the Coulomb blockade effect [4]. The sample under light exposure conditions did not show this phenomenon. The control sample did not show Coulomb blockade either. The leakage current under the green light exposure was lower than that under the red light exposure. A detailed study on the charge storage characteristics under the influence of exposure light wavelength will be included in this paper.
1. S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Cabbe and K. Chan, Appl. Phys. Lett., 68, 1377 (1996).
2. Y. Kuo, X. Liu, C. H. Yang, and C. C. Lin, Mater. Res. Soc. Symp. Proc. 1430, E01 (2012).
3. B. Q. Luo, C. C. Lin, and Y. Kuo, ECS Trans., 41, 93 (2011).
4. X. Liu, C. H. Yang, Y. Kuo, and T. Yuan, Electrochem. Solid-State Lett., 15, H1 (2012).

The demand for high density, low power and high speed performance has been increasing. For the demand, a dynamic random-access memory (DRAM), which consists of one transistor and one capacitor, requires a high stack capacitor or a deep-trench capacitor to satisfy a storage capacitance (around 25fF/cell) in smaller cells. In a 30-nm DRAM, it is difficult to discriminate between the ‘0&’ and ‘1&’ logic states due to severe charge leakage of the capacitor caused by the high inner electric field. Moreover, if the height of the capacitors is too high, they can lean each other. If a capacitor can be replaced to a resistor or eliminated from the DRAM cell structure, scaling down issue can be overcome easily. The capacitor-less using the floating body effect on a silicon-on-insulator (SOI) wafer consists of one transistor structure operated with a charge storage in the silicon body without a storage capacitor. In capacitor-less memory, two states of ‘0&’ and &’1&’ are discriminated using the threshold voltage (VT) difference induced by the kink effect on the SOI. We investigated the effect of the SiGe layer and mobility enhancement on the memory margin of a capacitor-less memory cell. The hole confinement well can be used to insert the SiGe layer. Moreover, mobility is increased by strain in the Si channel. The memory margin of a strained Si SGOI capacitor-less memory cell was 138.6 µA, or 3.3 times greater, at a Ge concentration of 32 at%. Two key phenomena contributing to a higher memory margin were studied. One is the effect of hole confinement, which is well achieved by inserting the SiGe layer. The other is increased mobility resulting from strain in the channel. These two effects enhance the memory margin by factors of 1.85 and 1.74, respectively, compared to that of the SOI cell at a 32 at% Ge concentration. Two factors were split into strain and hole barrier effect through the simulation work with a device simulator ATLAS from Silvaco International Corporation. These simulation results show that the two factors of the strained Si SGOI capacitor-less memory cell improve the memory margin with Ge concentration. We demonstrate the possibility of an extremely long retention time which results from the innovative structure of a capacitor-less memory cell as the strained Si grown on SiGe-on-insulator (SGOI). * This work was financially supported by the grant from the “Next-generation substrate technology for high performance semiconductor devices (No. KI002083)“ of the Ministry of Knowledge Economy (MKE) of Korea and the Brain Korea 21 Project in 2012.

Research on the electronic properties of disordered materials dates back to the original work of Ovshinsky in the 1950s. From 1958 to 1961, he investigated the chemical and the electrical properties of amorphous semiconductors, discovering the existence of reversible switching effects. The first one is related to the reversible switching mechanism between an electrical low conductive state and a high conductive one, without any change in the microscopic structure of the material. Since this mechanism requires a threshold voltage and is usually associated with an SNDCs, it has been named threshold switching (also called Ovonic threshold switching OTS). A second mechanism was also discovered in some chalcogenide compounds, this one related to a thermally activated phase transition of the chalcogenide alloy that can be switched between a high conductive polycrystalline state and a low conductive amorphous one, through proper electrical pulses that cause a Joule heating of the material. Since both the crystalline and the amorphous state are stable, the two phases could be used to store binary information in a nonvolatile memory device, the bit “1” corresponding to the conductive state and the bit “0” to the insulating one. This electrically induced structural change has been thus named Ovonic memory switching (OMS). It is worth noting that the OTS effect is required to get the OMS mechanism but not vice versa. In fact, an amorphous chalcogenide has to be driven in a highly conductive electrical state through OTS to get the transition temperatures without enormous electrical fields. Despite this fundamental role of the OTS effect and the theoretical efforts spent in the past 50 years to explain this crucial phenomenon, the nature of the physical principle responsible for the conductance switching is still controversial.
In this tutorial the main ingredients of the chalcogenide physics are reviewed and analyzed through simplified analytical models, providing a deeper insight on the origin of the threshold switching mechanism in chalcogenide glasses. The electrical properties of phase-change materials, including low-field conductivity, transient behaviors, and resistance drift, will be reviewed and the various models so far proposed will be compared, highlighting their strengths and weaknesses. Finally, some experimental evidences will be reviewed as a possible path to discriminate among the several threshold switching theories.

Next generation CMOS requires high activation and hyper-abrupt junction formation for low sheet resistance. The primary method of doping, ion implantation, provides excellent spatial control of dose, however a high temperature anneal (>1000 C) is required to remove defects introduced from ion implantation and to electrically activate the implanted specie. A “diffusionless anneal” by which dopant is activated without significantly diffusing, would be ideal for ultra-shallow junction (USJ) formation. This work investigates one such technique, laser annealing, which uses a scanning laser to locally heat the wafer surface. We investigate the laser system via simulation to determine the peak temperature achieved in the active area during processing. We employed the Sentaurus TCAD software by Synopsys to perform a 2D simulation of a laser scanning across the active area of the device, solving the heat equation in both time and space. An absorber layer is deposited on the wafer surface to encourage the absorption of optical power and consequent heating of the wafer surface. An effective absorption coefficient of α=8000cm-1 was calculated for the absorber layer, calibrated with the experimental laser intensity. This absorption coefficient correctly predicts the silicon temperature as a function of power with any arbitrarily defined scan speed. To investigate the role of dopant activation, an SOI wafer was implanted at 25 keV, dose 3e15 /1.5e15 cm-2 and laser annealed in stripes of target temperatures ranging from 1100-1300 C. The sheet resistance was measured on wafer showing Rs improvement with increasing laser temperature. The extracted temperature cycle from the 2D heat simulation was used as an equivalent millisecond RTA in a full 3D finFET process simulation to study dopant distribution and activation using Sentaurus Process Kinetic Monte Carlo (KMC), considering the effect of dopant clusters and point defects. The results of this simulation, show that there is no further activation of arsenic with increasing laser temperature (~ 25%) which suggests healing of the implant crystal damage may be reducing sheet resistance.

Metal gates are replacing polycrystalline silicon gates in CMOS applications to enable integration with high-k dielectrics and further scaling of devices. However, work function (WF) variation due to grain orientation has become a significant problem as the gate dimensions scale and become comparable to the grain size. Amorphous metal gates have the potential to eliminate WF variability due to their lack of grains, and have drawn attention in the past few years. For future MOSFETs, the following properties are required for the metal gate: thermal stability, suitable WF, low resistance, compatibility with high-k dielectrics, and conformal deposition.
In this study, we investigated binary amorphous metal gate systems since the simple structures make them promising candidates for conformal deposition systems such as ALD. Metals and metal alloys tend to crystallize due to their simple crystal structures. However, certain binary metal systems can form a metastable amorphous structure, although most do not meet all the requirements listed above. In our study TaNi was selected as the candidate because of it provides a potential tunable work function range from 4.3eV (WF of Ta) to 5.1eV (WF of Ni). Crystal structure, thermal stability, and electrical properties of various compositions (Ta, Ta25Ni75, Ta50Ni50, Ta75Ni25, and Ni) were investigated. All the metal gates were deposited by DC sputtering onto SiO2 substrates for film characterization and onto SiO2/HfO2 substrates for WF extraction using C-V. As determined by grazing XRD, all alloys are amorphous as-deposited and are stable after annealing at at least 400°C for 30 mins, which makes them suitable for gate-last application. In addition, Ta/Ni multi layers with thickness of 1.2nm were sputtered and are amorphous as-deposited due to mixing during deposition, lending them to ALD processes. The resistivity of all the amorphous films are around 200mu;Omega;*cm.
While one might expect the WF to vary linearly with composition to first order, for the TaNi alloys in this study the WF is pinned at the Ta WF value until pure Ni. XPS depth profiles reveal that the Ta atoms seem to segregate to the metal/HfO2 interface to some degree, perhaps due to the higher Ta-O bond enthalpy compared to Ni-O, thus resulting in the WF/composition behavior. These properties enable us to have a thermally stable amorphous metal with the WF of one component (Ta), which provides flexibility in fabrication and the ability to optimize other properties (stability of amorphous phase, resistivity, etc.) while maintaining the WF. In addition, due to the absence of grain boundaries, amorphous TaNi can act as a good diffusion barrier for other metals, which makes it more attractive for use in gate stacks since this reduces the need for an additional diffusion barrier layers for the metal fill. Based on the above characteristics, amorphous TaNi has great potential for use in advanced CMOS gate structures.

High dielectric constant (k) oxides are important elements of devices such as MOSFETs, DRAMs, and non-volatile memories and will continue to be used for new technology nodes. Electrical measurements on metal-insulator-metal (MIM) capacitors with different types of high k oxides were used to develop a model for defect generation that explains the electrical leakage as well as reliability of a wide range of high k oxides. The breakdown fields (Ebd) of thin films (5-10nm) of different binary and ternary oxides decreased with increasing k over a wide range of k values (9-80). The values were accurately described by the function Ebd=A*k-0.5 similar to that predicted from Macpherson&’s Thermochemical model [1].
The dependence of the breakdown field on temperature was also determined. The increase in leakage currents as a function of time for different combinations of constant-voltage-stress/temperature were measured on a few samples with different k. By modeling the I-V curves at different points of the stress cycle, it was shown that the increased leakage current was caused by creation of additional oxygen Frenkel defects by the electrical stress. The rate of defect formation for a given applied field increased with k, indicating that high “local” fields at the lattice position (which are enhanced at high k) were responsible for lowering the energy barrier for defect creation. The model of electrical field induced defect generation explains the breakdown of high k dielectrics and in particular the dependence on k. Films under different stress conditions (voltage, temperature, time) were annealed at different temperatures and times.
The reduction of leakage current as a function of time for different annealing temperatures was measured and in all cases followed a fractional power law with respect to time. This allowed the determination of the spatial separation of Oxygen Interstitials and Vacancies after electrical stress and an estimation of the diffusion rate of the defects. Defects created by electrical stress at room temperature recombined within a few seconds for anneal temperatures around 90C. This indicates that electric fields at low temperatures create defects within a lattice distance. In contrast, if the samples were stressed at temperatures >90C but annealed at temperatures lower than the stress temperature, a large fraction of the defects remained active even after several hours. This could be explained by the larger separation of field-induced Interstitials and Vacancies due to diffusion of these defects at higher temperatures.
1. J. McPherson, J. Kim, A. Shanware, H. Mogul and J. Rodriguez, IEEE Transactions on Electron Devices, 50 (8), pp 1771 - 1778 (2003).

We present here experimental results and analysis of the interface states and defect density for AlGaN / GaN heterostructures with AlN, Al2O3 and SiN insulators. The conventional AlGaN / GaN Schottky-gate high electron mobility transistor suffers from problems such as high gate leakage and current collapse. Transistor structures with insulated gates have been developed to suppress gate leakage and passivate surface states. Insulator materials such as SiO2, Si3N4, Al2O3, HfO2 and AlN have been reported as the gate dielectric and passivation layers. The ideal candidate material should have high bandgap (Eg > 5eV), high dielectric constant comparable to AlGaN (k ~ 9.5), high breakdown field (E > 10 MV / cm) and high thermal conductivity. The dielectric material also has to form a good interface with AlGaN since good gate control of the transistor depends on the dielectric / AlGaN interfacial properties. We have studied and characterized the dielectric / AlGaN interface to better understand the relative importance of these issues.
In this work we characterized the interface of three dielectric materials deposited on AlGaN/GaN heterostructures: Al2O3, AlN, and SiN. The Al2O3 and AlN layers were deposited by atomic layer deposition (ALD). Trimethylaluminum (TMA) and water vapor were used as the Al and O sources for the Al2O3 films. TMA and NH3 were used as Al and N sources for AlN. SiN deposition was performed by plasma-enhanced chemical vapor deposition (PECVD) using the SiH4 and NH3 reaction. Metal / dielectric / AlGaN / GaN MIS diodes were fabricated. Ti / Al / Ni / Au (20 / 50 / 20 / 100 nm) stacks were evaporated and annealed at 800 °C for 20 s to form ohmic contacts. Ni / Au was used as gate contact on the dielectric layer. AlGaN / GaN Schottky diodes were also fabricated for comparison. Electrical characterization, including current-voltage (I-V) measurements, shows that the MIS structure has superior suppression of gate leakage current. Capacitance-voltage characterization of the dielectric / AlGaN and AlGaN / GaN interfaces are also reported with three stages of the voltage sweeping range. The 2DEG is first depleted below the threshold voltage, and then forms at the AlGaN / GaN interface above the threshold voltage. At a high positive gate voltage, electrons at AlGaN / GaN interface partially transfer to dielectric / AlGaN interface. Multiple frequency C-V was used to investigate interface states at both the dielectric / AlGaN and AlGaN / GaN interfaces. Our conclusion is that ALD-grown Al2O3 / AlN forms superior interfaces with AlGaN compared to PECVD SiN / AlGaN interfaces.