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Fall 2008 Logo2008 MRS Fall Meeting & Exhibit

December 1-5, 2008 | Boston
Meeting Chairs:
 S. Ashok, Shenda M. Baker, Michael R. Fitzsimmons, Young-Chang Joo

Symposium E : Materials and Technologies for 3-D Integration

2008-12-01   Show All Abstracts

Symposium Organizers

Fred Roozeboom NXP Semiconductors Research
Christopher Bower Semprius, Inc.
Phil Garrou Microelectronic Consultants of NC
Mitsumasa Koyanagi Tohoku University
Peter Ramm Fraunhofer Institute IZM Munich
E1: Intro and Applications
Session Chairs
Fred Roozeboom
Monday PM, December 01, 2008
Room 205 (Hynes)

9:15 AM - **E1.1
3D Process Integration – Requirements and Challenges.

Jurgen Wolf 1 , A. Klumpp 1 , Kai Zoschke 1 , R. Wieland 1 , L. Nebrich 1 , M. Klein 1 , H. Oppermann 1 , P. Ramm 1 , H. Reichl 1
1 , Fraunhofer IZM Institute, Berlin Germany

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9:45 AM - **E1.2
Three-Dimensional Integrated Circuit Fabrication Technology*.

Craig Keast 1 , Chenson Chen 1 , Jeff Knecht 1 , Vyshi Suntharalingam 1 , Brian Tyrrell 1 , Bruce Wheeler 1 , Donna Yost 1
1 , MIT Lincoln Laboratory, Lexington , Massachusetts, United States

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10:15 AM - **E1.3
Current and Future 3D-LSI Technology for the Image Sensor Devices.

Makoto Motoyoshi 1 , Hirofumi Nakamura 1 , Manabu Bonkohara 1 , Mitsumasa Koyanagi 2 1
1 , Zycube, Yokohama Japan, 2 , Tohoku University, Sendai Japan

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10:45 AM - E1 Intro amp; Apps
BREAK

11:15 AM - **E1.4
Scalability and Low Cost of Ownership Advantages of Direct Bond Interconnect (DBI®) as Drivers for Volume Commercialization of 3-D Integration Architectures and Applications.

Paul Enquist 1
1 , Ziptronix, Inc., Morrisville, North Carolina, United States

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11:45 AM - **E1.5
3D Wafer Level Packaging: Processes and Materials for Trough Silicon Vias & Thin Die Embedding.

Philippe Soussan 1 , Bart Swinnen 1 , Bivragh Majeed 1 , Deniz Sabuncuoglu Tezan 1 , Wouter Ruythooren 1 , François Iker 1 , Eric Beyne 1
1 , IMEC, Leuven Belgium

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12:15 PM - **E1.6
Wafer and Die Bonding Technologies for 3D Integration.

Shari Farrens 1
1 , SUSS MicroTec, Waterbury Center, Vermont, United States

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E2: 3D Bonding
Session Chairs
Philip Garrou
Monday PM, December 01, 2008
Room 205 (Hynes)

2:30 PM - **E2.1
3D Integration Using Adhesive, Metal, and Metal/Adhesive as Bonding Interfaces.

Jian-Qiang Lu 1 , J. McMahon 1 , Ronald Gutmann 1
1 Electrical, Computer, and Systems Engineering, Rensselaer Polytechnic Institute, Troy, New York, United States

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3:00 PM - **E2.2
Copper Direct Bonding for 3D Integration, a Room Temperature, Atmospheric Pressure and Ambient Air Process.

Lea DiCioccio 1 , Pierric Gueguen 1 , Maurice Rivoire 2 , Daniel Scevola 2 , P. Gergaud 1 , Anne Marie Charvet 1 , Dominique Lafond 1 , Laurent Clavelier 1
1 DRT/DIHS/LTFC, CEA-Grenoble, Gredoble cedex France, 2 , STMicroelectronics, Crolles Cedex France

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3:30 PM - E2.3
Ambient Copper-Copper Bonding using Self Assembled Monolayers.

Xiaofang Ang 1 , Jun Wei 2 , Zhong Chen 1 , Chee Cheong Wong 1
1 , Nanyang Technological University, Singapore Singapore, 2 , Singapore Institute of Manufacturing Technology, Singapore Singapore

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3:45 PM - E2.4
Effect of Temperature and Bonding Duration on the Mechanical Strength of Metal to Metal Thermocompression Bonds.

I Made Riko 1 3 , Chee Lip Gan 1 3 , Liling Yan 2
1 School of Materials Science and Engineering, Nanyang Technological University, Singapore Singapore, 3 Advanced Materials for Micro- and Nano-systems, Singapore-MIT Alliance, Singapore Singapore, 2 , Institute of Microelectronics, Singapore Singapore

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4:00 PM - E2 Bonding
BREAK

4:30 PM - **E2.5
Fabrication and Characterization of Metal-to-Metal Interconnect Structures for 3-D Integration.

Alan Huffman 1 , John Lannon 1 , Matthew Lueck 1 , Christopher Gregory 1 , Dorota Temple 1
1 , RTI International, Research Triangle Park, North Carolina, United States

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5:00 PM - **E2.6
Thin Wafer Processing for TSV and 3D Integration.

Thorsten Matthias 1 , C. Brubaker 1 , B. Kim 1 , S. Pargfrieder 2 , M. Privett 3 , R. Puligadda 3 , X. Shao 3
1 , EVG North America, Tempe, Arizona, United States, 2 , EVG Group , Florian Austria, 3 , Brewer Science Inc., Rolla, Missouri, United States

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5:30 PM - **E2.7
Three-Dimensional Integration Technology Based on Self-Assembled Chip-to-Wafer Stacking.

T. Fukushima 1 , T. Tanaka 1 , M. Koyanagi 1
1 , Tohoku University, Sendai Japan

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2008-12-02   Show All Abstracts

Symposium Organizers

Fred Roozeboom NXP Semiconductors Research
Christopher Bower Semprius, Inc.
Phil Garrou Microelectronic Consultants of NC
Mitsumasa Koyanagi Tohoku University
Peter Ramm Fraunhofer Institute IZM Munich
E3: TSV and Thinning
Session Chairs
Peter Ramm
Tuesday AM, December 02, 2008
Room 205 (Hynes)

9:15 AM - **E3.1
Bosch Process – DRIE Success Story, New Applications and Products.

Andrea Urban 1 , Franz Laermer 1
1 EPT, Robert Bosch GmbH, Reutlingen Germany

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9:45 AM - **E3.2
Front End Through Silicon Via (TSV) Fabrication.

Subhash Shinde 1 , Todd Bauer 1 , Jordan Massad 1 , Dale Hetherington 1
1 , Sandia National Labs, Albuquerque, New Mexico, United States

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10:15 AM - E3.3
The Effect of Process Parameters on Electrical Properties of High Density Through-Si Via.

Patrick Leduc 1 , Myriam Assous 1 , David Bouchu 1 , Virginie Loup 1 , Antonio Roman 1 , Barbara Charlet 1 , Léa Di Cioccio 1 , Emmanuel Deronzier 1 , Anne Roule 1 , Lucile Mage 1 , Nicolas Sillon 1
1 , CEA-Leti, Grenoble France

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10:30 AM - E3.4
Edge Protection of Wafers during Through-Silicon via Fabrication using Anisotropic Wet Etching of Silicon.

Ramachandran Trichur 1 , Gary Brand 1
1 , Brewer Science, Inc., Rolla, Missouri, United States

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10:45 AM - E3 TSV amp; thin
break

11:00 AM - **E3.5
Copper Plating for 3D Interconnect Applications.

Tom Ritzdorf 1
1 , Semitool, Inc., Kalispell, Montana, United States

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11:30 AM - **E3.6
Cu Plating of Through-Si Vias for 3D-Stacked Integrated Circuits.

Aleksandar Radisic 1 , Ole Luhn 1 2 , Bart Swinnen 1 , Wouter Ruythooren 1 , Philippe Vereecken 1
1 , IMEC, Leuven Belgium, 2 MTM, Katholieke Universiteit Leuven, Leuven Belgium

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12:00 PM - E3.7
A Method for Die Thickness Reduction to sub-35 µm.

Jeffrey Thompson 1 , Gary Tepolt 1 , Livia Racz 1 , Chris Rogers 2 , Vincent Manno 2 , Robert White 2
1 Advanced Hardware, C.S. Draper Laboratory, Cambridge, Massachusetts, United States, 2 Mechanical Engineering, Tufts University, Medford, Massachusetts, United States

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12:30 PM - E3.9
Statistical Analysis of the Influence of Thinning Processes on the Strength of Silicon.

Yu Yang 1 2 , Ricardo Teixeira 1 , Philippe Roussel 1 , Bart Swinnen 1 , Bert Verlinden 2 , Ingrid De Wolf 1 2
1 IPSI, IMEC, Leuven Belgium, 2 MTM, KUL, Leuven Belgium

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12:45 PM - E3.10
Oxidized ALD-deposited Titanium Nitride Films as a Low-temperature Alternative for Enhancing the Wettability of Through-Silicon Vias (TSVs).

Mohamed Saadaoui 1 , Henk Van Zeijl 1 , Hoa Pham 1 , Harm Knoops 2 , Erwin Kessels 2 , Yann Lamy 3 , Wim Besling 3 , Fred Roozeboom 3 2 , Lina Sarro 1
1 DIMES ECTM, TU-DELFT, Delft Netherlands, 2 Department of Applied Physics, Eindhoven University of Technology, Eindhoven Netherlands, 3 , NXP-TSMC Research Center, Eindhoven Netherlands

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E4: 3d Packaging and Epi 3D
Session Chairs
Christopher Bower
Tuesday PM, December 02, 2008
Room 205 (Hynes)

2:30 PM - **E4.1
The Promise of 3D ICs With Through Silicon Vias.

Sitaram Arkalgud 1
1 , Sematech, Albany , New York, United States

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3:00 PM - **E4.2
Recent Technology and Material Developments in 3D Packaging and Assembly.

Marc de Samber 1 , Eric van Grunsven 1 , Gerard Kums 1 , Anton van der Lugt 1 , Hans de Vries 1
1 , Philips Applied Technologies, Eindhoven Netherlands

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3:30 PM - **E4.3
Die-to-Wafer 3D Integration Technology for High Yield and Throughput.

Katsuyuki Sakuma 1 , Paul Andry 2 , Cornelia Tsang 2 , Yukifumi Oyama 3 , Kuniaki Sueoka 1 , Steven Wright 2 , Raymond Horton 2 , Bing Dang 2 , Chirag Patel 2 , Robert Polastre 2 , Edmund Sprogis 4 , John Knickerbocker 1
1 Tokyo Research Laboratory, IBM, Yamato, Kanagawa, Japan, 2 T.J. Watson Research Center, IBM, Yorktown Heights, New York, United States, 3 Systems and Technology, IBM, Shimogyo-ku, Kyoto, Japan, 4 Systems and Technology, IBM, Essex Junction, Vermont, United States

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4:00 PM - E4
BREAK

4:15 PM - **E4.4
3D MEMS and IC Integration.

Maaike Taklo 1 , Nicolas Lietaer 1 , Hannah Tofteberg 1 , Timo Seppanen 2 , J. Prainsack 3 , Josef Weber 4 , Peter Ramm 4
1 Microsystems and Nanotechnology, SINTEF ICT, Oslo Norway, 2 , Infineon Technologies SensoNor AS, Horten Norway, 3 , Infineon Technologies , Graz Austria, 4 , Fraunhofer-IZM, Munich Germany

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4:45 PM - E4.5
Laser Crystallization of Si Films for Fabricating 3-D Integrated Circuits.

Gabriel Ganot 1 , Monica Deep 1 , P. van der Wilt 1 , U. Chung 1 , A. Chitu 1 , A. Limanov 1 , James Im 1
1 Program in Materials Science and Engineering, Columbia University, New York, New York, United States

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5:00 PM - E4.6
Pulsed Current Annealing of Lithographically Defined Si Wires on Insulating Substrates for Single Crystal Si Ribbon Formation for 3D Integration.

Ali Gokirmak 1 , Gokhan Bakan 1 , Cicek Boztug 1 , Adam Cywar 1 , Nathan Henry 1 , Mustafa Akbulut 1 , Helena Silva 1
1 Electrical and Computer Engineering , University of Connecticut, Storrs, Connecticut, United States

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5:15 PM - E4.7
Seeded Crystallization of Amorphous Semiconductors by Vertical Epitaxial Ge Nanowires: A Possible Approach to Dense 3-D Integrated Circuits.

Shu Hu 1 , Paul Leu 1 , Paul McIntyre 1 2
1 Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 , the Geballe Laboratory for Advanced Materials, Stanford, California, United States

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5:30 PM - E4.8
Oxide-based Electronic Switching Devices for 3D Stack Oxide Memory.

Bo Soo Kang 1 , Ki Hwan Kim 1 , Myoung-Jae Lee 1 , Seung Eon Ahn 1 , Chang Bum Lee 1 , Genrikh Stefanovich 1 , Chang Jung Kim 1 , Youngsoo Park 1
1 Semiconductor Lab., Samsung Advanced Institute of Technology, Yongin-si, Gyeonggi-do, Korea (the Republic of)

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5:45 PM - E4.9
Fabrication and Reliability of Wafer-level MEMS Packaging.

Yoon-Chul Sohn 1 , Suk-Jin Ham 1 , Ji-Hyuk Lim 1 , Byung-Gil Jeong 1 , Jong-Oh Kwon 1 , Woon-Bae Kim 1 , Chang-Youl Moon 1
1 Materials & Devices Research Lab, Samsung Advanced Institute of Technology, Yongin, Gyeonggi-do, Korea (the Republic of)

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E5: Poster Session
Session Chairs
Wednesday AM, December 03, 2008
Exhibition Hall D (Hynes)

9:00 PM - E5.1
Characterization of Texture and Microstructure of Electrodeposited Ni Layer.

Homuro Noda 1 , Akinobu Shibata 2 , Masato Sone 2 , Chiemi Ishiyama 2 , Yakichi Higo 2
1 Department of Materials Science and Engineering, Tokyo institute of technology, Yokohama Japan, 2 Precision and Intelligence Laboratory, Tokyo institute of technology, Yokohama Japan

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9:00 PM - E5.2
A Generic Heterogeneous 3D Integration Platform Based on Post-Processing.

Fengda Sun 1 , Yusuf Leblebici 1
1 Microelectronic Systems Laboratory, Ecole Polytechnique Fédérale de Lausanne, Lausanne, Vaud, Switzerland

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9:00 PM - E5.3
Low Temperature Growth of Silicon Structures for 3-D Flash Memory Devices.

Thomas Mih 1 , Richard Cross 1 , Shashi Paul 1
1 Emerging Technologies Research Centre, De Montfort University, Leicester United Kingdom

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9:00 PM - E5.5
Effect of Nanotwin on Abnormal and Normal Grain Growth in Pulse Electrodeposited Copper.

Di Xu 1 , Luhua Xu 1 , Vinay Sriram 1 , Jenn-Ming Yang 1 , King-Ning Tu 1
1 Materials Science and Engineering, University of California, Los Angeles, Los Angeles, California, United States

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2008-12-03   Show All Abstracts

Symposium Organizers

Fred Roozeboom NXP Semiconductors Research
Christopher Bower Semprius, Inc.
Phil Garrou Microelectronic Consultants of NC
Mitsumasa Koyanagi Tohoku University
Peter Ramm Fraunhofer Institute IZM Munich
E6: Materials and Modeling
Session Chairs
Mitsumasa Koyanagi
Wednesday AM, December 03, 2008
Room 205 (Hynes)

9:30 AM - **E6.1
Fabrication Method using Wet Etching Technology for Multi-layer Stacked Devices.

Miyakawa Nobuaki 1 , Hashimoto Eiri 1 , Maebashi Takanori 1 , Nakamura Natsuo 1 , Sacho Yutaka 1 , Nakayama Shigeto 1 , Toyoda Shinjiro 1
1 , Honda Research Institute Japan Co., Ltd., Wako, Saitama, Japan

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10:00 AM - **E6.2
Hotspot-Optimized Interlayer Cooling in Vertically Integrated Packages.

Thomas Brunschwiler 1 , Bruno Michel 1 , Hugo Rothuizen 1 , Urs Kloter 1 , Bernhard Wunderle 3 , Hermann Oppermann 3 , Herbert Reichl 2 3
1 , IBM Research, Rüschlikon Switzerland, 3 , Fraunhofer Institute for Reliability and Microintegration, Berlin Germany, 2 , Technische Universität Berlin, Berlin Germany

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10:30 AM - **E6.3
Thermo-Mechanical Reliability Investigation of Through-Silicon-Vias and Inter-connects for 3D Systems Integration.

Bernhard Wunderle 1 , J. Weber 2 , R. Mrossko 1 , E. Kaulfersch 1 , P. Ramm 2 , B. Michel 1 , H. Reichl 3
1 , Fraunhofer Institute Reliability and Microintegration, Berlin Germany, 2 , Fraunhofer IZM, Munich Division, Munich Germany, 3 , Technische Universitat Berlin, Berlin Germany

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11:00 AM - *
break

11:30 AM - **E6.4
Design Support for 3D System Integration by Multi Physics Simulation.

Peter Schneider 1 , Sven Reitz 1 , Jorn Stolle 1 , Roland Martin 1 , Andreas Wilde 1 , Peter Ramm 2 , Josef Weber 2
1 , Fraunhofer IIS/EAS, Dresden Germany, 2 , Fraunhofer IZM , Munich Germany

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12:00 PM - **E6.5
Through Silicon via Metallization: a Novel Approach for Insulation/Barrier/Copper Seed Layer Deposition-based on Wet Electrografting and Chemical Grafting Technologies.

D. Suhr 1 , J. Gonzales 1 , I. Bispo 1 , Frederic Raynal 1 , C. Truzzi 1 , Steve Lerner 1 , Vincent Mevellec 1
1 , Alchimer S.A., Massy France

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12:30 PM - E6.6
Self Assembly of Die to Wafer using Direct Bonding Methods and Capillary Forces.

Francois Grossi 1 , Léa Di Cioccio 1 , Francois Rieutord 1 , Olivier Renault 1 , Jean Berthier 1 , Jean-Charles Barbé 1 , Francois De Crécy 1 , Laurent Clavelier 1
1 , CEA-LETI-MINATEC, Grenoble France

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12:45 PM - E6.7
Grain Boundary Engineering in Copper Through-via Silicon Interconnects.

S. Ratanaphan 1 2 , D. Xu 2 , L. Xu 2 , Dierk Raabe 1 , K. Tu 2
1 , Max-Planck-Institut fuer Eisenforschung, Duesseldorf Germany, 2 Department of Materials Science and Engineering, University of California, Los Angeles, California, United States

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