Symposium Organizers
Fred Roozeboom NXP Semiconductors Research
Christopher Bower Semprius, Inc.
Phil Garrou Microelectronic Consultants of NC
Mitsumasa Koyanagi Tohoku University
Peter Ramm Fraunhofer Institute IZM Munich
E1: Intro and Applications
Session Chairs
Monday PM, December 01, 2008
Room 205 (Hynes)
9:15 AM - **E1.1
3D Process Integration – Requirements and Challenges.
Jurgen Wolf 1 , A. Klumpp 1 , Kai Zoschke 1 , R. Wieland 1 , L. Nebrich 1 , M. Klein 1 , H. Oppermann 1 , P. Ramm 1 , H. Reichl 1
1 , Fraunhofer IZM Institute, Berlin Germany
Show Abstract9:45 AM - **E1.2
Three-Dimensional Integrated Circuit Fabrication Technology*.
Craig Keast 1 , Chenson Chen 1 , Jeff Knecht 1 , Vyshi Suntharalingam 1 , Brian Tyrrell 1 , Bruce Wheeler 1 , Donna Yost 1
1 , MIT Lincoln Laboratory, Lexington , Massachusetts, United States
Show AbstractOver the last several years MIT Lincoln Laboratory (MIT-LL) has developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This talk will provide a brief overview of MIT-LL’s 3D-integration process and a discussion of some of the application areas and circuit ideas being explored with the technology. *This work was sponsored by the United States Army under U.S. Air Force contract FA8721-05-C-0002. “Opinions, interpretations, conclusions, and recommendations are those of the authors and are not necessarily endorsed by the United States Government.”
10:15 AM - **E1.3
Current and Future 3D-LSI Technology for the Image Sensor Devices.
Makoto Motoyoshi 1 , Hirofumi Nakamura 1 , Manabu Bonkohara 1 , Mitsumasa Koyanagi 2 1
1 , Zycube, Yokohama Japan, 2 , Tohoku University, Sendai Japan
Show AbstractRecently the development of three-dimensional large-scale integration (3D-LSI) has been accelerated and its stage has changed from the research level or limited production level to the investigation level with a view to mass production. This paper describes the current and future 3D-LSI technologies with TSV focused on image sensor. Semiconductor integration technology has been widely spread in two dimensional over the past three decades. The reason for this rapid progress is due largely to good scalability of MOS device in device level and easy prediction of next generation LSIs based on Moore’s law. But in recent years, the actual device has become to deviate from the ideal scaling theory. The main cause is difficulty of operation voltage scaling. The value of kT/q does not scale down and thus lowering threshold voltage (Vth) of MOS transistor is difficult without increasing subthreshold leakage. Without Vth scaling, power and performance became a trade-off. Under this circumstance, in order to bring out high performance from LSI chips while restricting their power, there are two approaches. One is reconsidering circuits and system architecture from view point of power consumption. Another is concerning LSI structure. In recent devices, the signal propagation delay is mainly determined by wiring length and pin capacitance. The 3D-LSI is the one solution to improve performance without increase of power consumption. One of the key issues to realize 3D-LSI is the method of the information transfer and the supply of electric power among stacked chips. There are many methods to connect inter-chip, such as wire-bonding, edge connect, capacitive or inductive coupling method, and direct contact using TSV. The 3D-LSI using TSV has simplest structure and it is expected to realize high-performance, high-functionality and high density LSI cube. In an ideal image sensor, pin outs are preferably located on the opposite side of the sensor array. This CSP does not have a real 3-D LSI structure itself, but it is simplest and applies the same technology, such as TSV, wafer thinning and bump formation. Therefore it is suitable vehicle to develop the 3D-LSI process module and easy to expand the real 3D-stacked structure, to include a sensor with DSP, or a sensor with memory and DSP etc. In this paper, the process and structure of the CSP for CMOS image sensor is presented. Among many potential application of 3D-LSI technology with fine pitch TSV are high performance focal plane array image sensors. This technology will allow high-speed signal processing and 100 % optical fill factor.
10:45 AM - E1 Intro amp; Apps
BREAK
11:15 AM - **E1.4
Scalability and Low Cost of Ownership Advantages of Direct Bond Interconnect (DBI®) as Drivers for Volume Commercialization of 3-D Integration Architectures and Applications.
Paul Enquist 1
1 , Ziptronix, Inc., Morrisville, North Carolina, United States
Show AbstractThe high volume commercialization of 3-D integration will require process technologies that are scaleable and have a low cost of ownership (CoO). Direct Bond Interconnect (DBI®) is a planar direct oxide bond technology that simply requires alignment and placement of constituent 3-D layers after suitable surface activation and termination to initiate a very reliable bond capable of scaleable 3-D interconnects. For example, this technology has previously been shown to be capable of 8 micron pitch interconnects with greater than 99.999% yield and reliability that significantly exceeds JEDEC requirements. This work reports an extension of this capability to 1.5 micron pitch and predicts submicron pitch capability with the availability of increased accuracy alignment and placement tools. The ability of this technology to obtain very high bond energies with simple alignment and placement allows these scaleable pitches to be achieved with a low CoO in a wafer-to-wafer or die-to-wafer format by eliminating the need for expensive bond tools and long cycle times.
11:45 AM - **E1.5
3D Wafer Level Packaging: Processes and Materials for Trough Silicon Vias & Thin Die Embedding.
Philippe Soussan 1 , Bart Swinnen 1 , Bivragh Majeed 1 , Deniz Sabuncuoglu Tezan 1 , Wouter Ruythooren 1 , François Iker 1 , Eric Beyne 1
1 , IMEC, Leuven Belgium
Show Abstract12:15 PM - **E1.6
Wafer and Die Bonding Technologies for 3D Integration.
Shari Farrens 1
1 , SUSS MicroTec, Waterbury Center, Vermont, United States
Show AbstractE2: 3D Bonding
Session Chairs
Monday PM, December 01, 2008
Room 205 (Hynes)
2:30 PM - **E2.1
3D Integration Using Adhesive, Metal, and Metal/Adhesive as Bonding Interfaces.
Jian-Qiang Lu 1 , J. McMahon 1 , Ronald Gutmann 1
1 Electrical, Computer, and Systems Engineering, Rensselaer Polytechnic Institute, Troy, New York, United States
Show AbstractThis paper reviews the materials and technologies for three wafer bonding approaches to 3D integration using adhesive, metal, and metal/adhesive as the wafer bonding interfaces. Differences in architectural advantages, technology challenges and potential applications are presented. Recent research advances and potential reliability issues are discussed.
3:00 PM - **E2.2
Copper Direct Bonding for 3D Integration, a Room Temperature, Atmospheric Pressure and Ambient Air Process.
Lea DiCioccio 1 , Pierric Gueguen 1 , Maurice Rivoire 2 , Daniel Scevola 2 , P. Gergaud 1 , Anne Marie Charvet 1 , Dominique Lafond 1 , Laurent Clavelier 1
1 DRT/DIHS/LTFC, CEA-Grenoble, Gredoble cedex France, 2 , STMicroelectronics, Crolles Cedex France
Show Abstract3D technology will be the next step for the development of microelectronic devices. Vertical interconnection is one of the challenging issues. Metal bonding might be one of the possible techniques to address it. In this work, direct Cu/Cu bonding at room temperature, atmospheric pressure and ambient air is investigated. At room temperature, a 2.8 J/m2 bonding toughness is achieved. EELS spectrum pointed out the absence of copper oxide at the interface. Morphological evolutions versus post bonding annealing are presented with TEM and XRD analyses. The ohmic behavior of the bonding is highlighted.
3:30 PM - E2.3
Ambient Copper-Copper Bonding using Self Assembled Monolayers.
Xiaofang Ang 1 , Jun Wei 2 , Zhong Chen 1 , Chee Cheong Wong 1
1 , Nanyang Technological University, Singapore Singapore, 2 , Singapore Institute of Manufacturing Technology, Singapore Singapore
Show AbstractA typical copper-copper thermocompression bonding process is carried out in an ultrahigh vacuum (UHV) or inert environment at a bonding temperature >300°C. The ultraclean environment serves a single purpose – to maintain oxide-free copper surfaces, allowing intimate physical contact between copper atoms. Yet often, a time lag between sample preparation and bonding leads to an inevitable formation of surface oxide which necessitates more stressful bonding conditions for successful bonding. This study has demonstrated successful bonding between two copper surfaces under ambient condition at a bonding temperature below 140°C, yielding typical joint shear strength of 70MPa. This is made possible by coating the copper surface with 1-undecanethiol prior to bonding. The densely packed monolayer serves to passivate the copper surface against oxidation under ambient conditions. The ultrathin organic monolayer structure, as compared to a bulk oxide layer, could be easily displaced during the mechanical deformation at the bonding interface which accompanies thermocompression. This method could be an effective simple bonding solution for three-dimensional integrated chips.
3:45 PM - E2.4
Effect of Temperature and Bonding Duration on the Mechanical Strength of Metal to Metal Thermocompression Bonds.
I Made Riko 1 3 , Chee Lip Gan 1 3 , Liling Yan 2
1 School of Materials Science and Engineering, Nanyang Technological University, Singapore Singapore, 3 Advanced Materials for Micro- and Nano-systems, Singapore-MIT Alliance, Singapore Singapore, 2 , Institute of Microelectronics, Singapore Singapore
Show Abstract4:00 PM - E2 Bonding
BREAK
4:30 PM - **E2.5
Fabrication and Characterization of Metal-to-Metal Interconnect Structures for 3-D Integration.
Alan Huffman 1 , John Lannon 1 , Matthew Lueck 1 , Christopher Gregory 1 , Dorota Temple 1
1 , RTI International, Research Triangle Park, North Carolina, United States
Show Abstract5:00 PM - **E2.6
Thin Wafer Processing for TSV and 3D Integration.
Thorsten Matthias 1 , C. Brubaker 1 , B. Kim 1 , S. Pargfrieder 2 , M. Privett 3 , R. Puligadda 3 , X. Shao 3
1 , EVG North America, Tempe, Arizona, United States, 2 , EVG Group , Florian Austria, 3 , Brewer Science Inc., Rolla, Missouri, United States
Show AbstractMany 3D manufacturing schemes for wafer-to-wafer (W2W) or chip-to-wafer (C2W) integration are based on a face-to-back stacking, where the device side of one wafer is bonded to the backside of another die or wafer. As the feasible aspect ratio for vias is limited, the only way to reduce the real estate consumption for the vias is to reduce the wafer thickness. Therefore thin wafer processing is a necessity for many integration schemes.For C2W it is advantageous to do all the front- and backside processing on wafer level prior to singulation. Face-to-back integration has the advantage that it allows to use the same integration techniques for two-layer devices as for multi-layer devices. Temporary bonding of the device wafer to a carrier wafer is a safe and reliable way for backside processing of thin wafers. After completion of the backside processing the device wafer is either permanently bonded to another device wafer or it gets debonded from the carrier wafer and transferred to a film frame for singulation. In this paper the progress of the thin wafer processing solution developed by EVG and Brewer Science will be presented. The protection of the thin wafer edge will be described in detail. An embedded wafer edge has been achieved with carriers with standard diameter, which enables compatibility with downstream equipment and processes. Furthermore, it will be described how this technology has been adapted for challenging topographies like protruding vias or bumps. A high emphasis will be on the process for bonding and debonding as well as on the material-process interaction.
5:30 PM - **E2.7
Three-Dimensional Integration Technology Based on Self-Assembled Chip-to-Wafer Stacking.
T. Fukushima 1 , T. Tanaka 1 , M. Koyanagi 1
1 , Tohoku University, Sendai Japan
Show AbstractThree-dimensional (3D) integration has attracted much attention since vertically stacked chips with a number of Through-Silicon Vias (TSVs) can increase packing density and improve LSI performance. In the recent 10 years, we have developed TSV with polycrystalline silicon (Poly-Si) or Poly-Si/Tungsten as conductive materials and fabricated prototype 3D LSI chips such as an image sensor chip, a shared memory, an artificial retina chip, and a microprocessor chip by using a wafer-to-wafer bonding method. The wafer-to-wafer 3D integration is a promising candidate for high-throughput stacking of memories such as Dynamic Random Access Memory (DRAM). However, a major problem in the wafer-to-wafer 3D integration is that production yield exponentially decreases with the increase in the number of stacked wafers because defective dies cannot to be removed from LSI wafers to be stacked. On the other hand, chip-to-wafer 3D integration can provide high production yield due to the use of Known Good Dies (KGDs). However, it takes much time to precisely align and tightly bond many KGDs onto an LSI wafer by robotic pick-and-place stacking methods used in the chip-to-wafer 3D integration. In 2005, we proposed 3D integration technology based on a new self-assembled chip-to-wafer bonding technique to solve the big throughput problem in the chip-to-wafer 3D integration using the pick-and-place chip stacking methods. We have demonstrated for the first time that a multi-chip self-assembly technique with surface tension of liquid can be applied to 3D integration of LSI chips. By using the fluidic self-assembly technique, a large number of chips can be simultaneously aligned onto a substrate within 0.1 seconds, and the chip alignment accuracy of several hundred nanometers is obtained. We can stack various kinds of chips with different chip sizes, different materials and different devices in our new 3D integration technology using the self-assembled chip-to-wafer bonding method. In the paper, the fundamental studies and potential application of the self-assembly-based 3D integration are presented. In addition, key technologies including chip thinning, underfilling, and Tungsten TSV and metal microbump formations are described. 3D LSI fabrication using our self-assembly technique is also introduced.
Symposium Organizers
Fred Roozeboom NXP Semiconductors Research
Christopher Bower Semprius, Inc.
Phil Garrou Microelectronic Consultants of NC
Mitsumasa Koyanagi Tohoku University
Peter Ramm Fraunhofer Institute IZM Munich
E3: TSV and Thinning
Session Chairs
Tuesday AM, December 02, 2008
Room 205 (Hynes)
9:15 AM - **E3.1
Bosch Process – DRIE Success Story, New Applications and Products.
Andrea Urban 1 , Franz Laermer 1
1 EPT, Robert Bosch GmbH, Reutlingen Germany
Show AbstractSilicon Deep Reactive Ion Etching (DRIE), as originally developed at Bosch, is a pioneering fabrication process for microsystems technology (MEMS), which revolutionized the manufacturing of MEMS devices and which opened the way to new generations of MEMS applications and products.The technology, today widely known as the “Bosch process”, is a plasma etching procedure dedicated to the structuring of silicon which is free from the design restrictions known from classical silicon wet etching in potassium hydroxide solution. Using the “Bosch process”, arbitrarily shaped structures can be etched deep into silicon substrates with vertical sidewalls, at high etching speed and an extreme level of precision.The basic development dates back to 1992. Since then the process has been constantly improved throughout the years.Nowadays a broad base of DRIE equipment suppliers have been established on the market. They support any costumer needs all over the world. Technology push from the early days has moved towards market pull from the product side, requesting enhanced key process features like high etching speed, improved uniformity and profile control, high selectivity and increasing aspect ratios. The requirements also cover a wide range of silicon exposure, from extremely low to extremely high percentage of open silicon area on the wafer, depending on the particular application.As a result of DRIE technology, cost-effective mass-production of sensors is nowadays possible. Since many years, a large number of Bosch sensor product families which rely on DRIE performance have penetrated the market, and new sensor generations are rising up the product pipeline. High volume acceleration sensors for airbag applications and gyroscopes for the ESP systems significantly contribute to the safety of millions of people worldwide.At the Bosch plant in Reutlingen (Germany) more than 150 million MEMS sensors are produced every year, and this number is further increasing, since new MEMS devices will be used in upcoming application fields outside of the automotive sector, e.g. in consumer products. Consumer MEMS markets are mobile phones, PDA’s, laptops and game consoles, and many more. Bosch founded a subsidiary to supply sensors especially to this field of consumer applications.The paper leads through the history from the early development stages of basic DRIE technology to the first steps into the MEMS field, and shows the path towards mass-production.Sensor applications like the inertial sensors for acceleration and yaw rate will be discussed, with special emphasis on their DRIE requirements. Further trends for future devices for new DRIE application fields on the market will be given, like micro mirrors, microphones, ink jet printing heads and micro spray nozzles.
9:45 AM - **E3.2
Front End Through Silicon Via (TSV) Fabrication.
Subhash Shinde 1 , Todd Bauer 1 , Jordan Massad 1 , Dale Hetherington 1
1 , Sandia National Labs, Albuquerque, New Mexico, United States
Show AbstractTuesday 12/2New Abstract *E3.2 @ 8:45 AMFront End Through Silicon Via (TSV) Fabrication.Subhash L. Shinde, Todd M. Bauer, Jordan E. Massad, and Dale Hetherington; Sandia National Laboratories, Albuquerque, New Mexico.3D integration provides an important solution for electronics systems miniaturization, with wide ranging applications (viz. computing, imaging, communications, and energy). 3D integration enables merging of diverse architectures and also offers considerable technical advantage by combining analog, digital, and other technology functions in a low-volume solution utilizing vertical die or wafer stacking. Some solutions for die and wafer stacking employ layer to layer vertical interconnects created after complete wafer fabrication. This vias-last approach requires via formation, isolation, and filling processes to be carried out at temperatures that are below 450C to be compatible with typical integrated circuit (IC) metal layers. Also, since the vias are formed last they take up space through all the metal layers in the chip impacting the efficient use of semiconductor ‘real estate’.This presentation will describe the approach we have developed to address these issues, viz. a complete process module for creating front end of line (FEOL) through silicon vias (TSVs). We rely on using thermally deposited silicon as a sacrificial material for via fill. After full FEOL processing, the silicon is removed by dry processing. Dry processing may include a plasma etch process, a chemical downstream etch process, and/or other dry processes such as XeF2 etching. Vias can be formed as early as the initial steps of FEOL processing. We employ Bosch etching to form high aspect ratio vias. After patterning and etch, dielectric isolation of the resulting via is achieved by thermal oxidation of silicon. After dielectric isolation, we use low pressure chemical vapor deposition (LPCVD) to deposit a conformal silicon fill of the etched and lined via. The silicon overburden is removed by CMP. To protect the thermal oxide via liner from wet etches that are common to FEOL processing and to protect the silicon in thevia from silicide formation, a silicon nitride barrier is defined to protect the sacrificial silicon and the oxide. After FEOL processing, the FEOL structures are covered by inter-layer dielectric (IMD) films. To expose the silicon that has filled the TSV, contacts are formed using photolithography and plasma etch process.. Once the silicon is exposed, dry processing is used to etch the silicon in the via leaving an unfilled via that is re-filled using tungsten CVD. CMP is used to remove the tungsten overburden. The resulting via is defined by initial patterning and etch processes, the dielectric isolation, and the metallization using tungsten.Concurrently we have also developed a high fidelity modeling approach to understand the stress distribution in 3D integrated structures. This is very important from device performance as well as TSV layout points of view. We employed a high-fidelity, 3D finite element modeling framework to examine the thermo-mechanical response of 3D IC interconnects. The modeling process involved three primary steps. In the first, we generated a parameterized geometrical representation of the structure. To accommodate all design features, we used the fabrication layout files and process definitions as the basis of the 3D virtual geometry. The parameterization allowed for the quantification of geometric uncertainties encountered due to processing inaccuracies and variations. In the second step, we developed a mesh generation program to enable high-fidelity finite element analysis. In the third step, we simulated the physical behavior of the body using a nonlinear, 3D finite element model with temperature-dependent material plasticity.
10:15 AM - E3.3
The Effect of Process Parameters on Electrical Properties of High Density Through-Si Via.
Patrick Leduc 1 , Myriam Assous 1 , David Bouchu 1 , Virginie Loup 1 , Antonio Roman 1 , Barbara Charlet 1 , Léa Di Cioccio 1 , Emmanuel Deronzier 1 , Anne Roule 1 , Lucile Mage 1 , Nicolas Sillon 1
1 , CEA-Leti, Grenoble France
Show AbstractThe purpose of the paper is to discuss the influence of through silicon via (TSV) process on its electrical properties. 15µm-deep TSVs with a diameter between 3µm and 5µm are considered in this study to address high density 3D integration. To characterize electrically the TSVs, daisy chains structures are performed by stacking face down a wafer with copper interconnect wires on a silicon carrier. The stacking is done using SiO2/SiO2 molecular bonding. After a substrate thinning, TSV are etched in silicon to connect the metal layer of the bonded wafer, using Bosch-like process. They are isolated with a silicon oxide liner and then filled with copper. The effect of copper filling property as voids and isolation quality of dielectric materials was evaluated with static electrical characterization. The results point the leading impact of TSV bottom quality on static resistance and yield. The impact of voids in copper metallization on resistance dispersion was also observed. A specific test structure was used to evaluate the isolation quality. The results show that leakage current can be observed between TSVs due to defects at the interface between the oxide liner and the TiN barrier layer. More than 90% yield was obtained on chains with 3200 TSVs. The resistance of 4µm large TSV was measured at 80mOhm with less than 30mOhm of resistance dispersion.
10:30 AM - E3.4
Edge Protection of Wafers during Through-Silicon via Fabrication using Anisotropic Wet Etching of Silicon.
Ramachandran Trichur 1 , Gary Brand 1
1 , Brewer Science, Inc., Rolla, Missouri, United States
Show AbstractThrough-silicon via (TSV) formation is an integral element for the realization of the three-dimensional (3D) interconnects for advanced integrated circuits. Here we present a method for edge protection of wafers during TSV fabrication by wet silicon etching using a photosensitive etch mask. TSVs are currently fabricated using deep reactive-ion etching (DRIE), laser drilling, or wet etching technologies. DRIE is the current technology of choice for high-density and high-aspect-ratio via holes. But deep silicon vias present several hurdles due to non-uniform seed layer deposition and void formation during the copper electroplating process. Moreover, the total cost of the process is a significant hurdle to implement the 3D interconnect technology for mass production.To mitigate the costs of drilling vias and simplify the metallization process, wet etching of silicon has been considered as an alternative process for fabricating TSVs. Here, silicon is etched using alkaline etch chemistries such as potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH). It has been previously demonstrated that a spin-applied organic photosensitive material can be used as a mask for deep silicon etching using KOH or TMAH for TSV fabrication. Previous results show that the photosensitive etch protective material demonstrated similar etch protection performance compared to silicon nitride etch masks in TMAH etch solutions, and it exhibited a larger but controlled undercut in KOH etch solutions. During wet etching of silicon using any etch mask, etch damage occurs at the wafer edge. The alkaline etch solution attacks the edges of the wafer through gaps in the organic coating or the CVD mask, which causes formation of a knife-edge or defects along the edge of the wafer. The knife-edge poses a severe threat to the integrity of the wafer during subsequent handling of the wafer and serves as a point of origin for cracks that tend to propagate and break the wafers.Here we present a method for edge protection by applying the photosensitive etch protective coating on the top, edge, and the backside rim of the wafer simultaneously to seamlessly encapsulate the wafer and its edges. The other side of the wafer is also coated to protect etch-sensitive features already present in the wafer. This edge wrapping is accomplished with the help of a specially designed coating baffle that collects the excess material during spin coating and coats the material along the edge of the wafer to obtain a seamless, continuous coating at the edge of the wafer. After the coating process, the wafer undergoes downstream processing, including lithography and wet silicon etching, to create TSVs. We have demonstrated good edge protection and TSV formation on wafer thicknesses down to 200 µm. We plan to perform additional tests to characterize the process for various wafer thicknesses or TSV dimensions and present alternate processes for formation of TSVs using wet silicon etching.
10:45 AM - E3 TSV amp; thin
break
11:00 AM - **E3.5
Copper Plating for 3D Interconnect Applications.
Tom Ritzdorf 1
1 , Semitool, Inc., Kalispell, Montana, United States
Show AbstractThere is an enormous amount of research going on today regarding various configurations of 3D interconnects for semiconductor applications. From through-wafer interconnects on CMOS image sensors to multiple transistor levels on a wafer to stacking chips during assembly and packaging, almost every imaginable combination of 3D integration is currently being considered. This activity includes about two orders of magnitude in feature dimensions just for through silicon via (TSV) applications.This paper will discuss the factors driving feature sizes and processes for electrochemical deposition (ECD) of copper as an electrical conductor for TSV filling and lining. The effect of feature sizes and shapes on the copper deposition process will be discussed, along with the driving factors for deciding whether to use complete copper fill, or lining only. The process parameters available in the copper ECD process, and their impact on the ability of the copper ECD process to fill high aspect ratio structures will also be presented. These parameters are typically manipulated to minimize the copper deposition time in order to provide a cost-effective TSV fill process.
11:30 AM - **E3.6
Cu Plating of Through-Si Vias for 3D-Stacked Integrated Circuits.
Aleksandar Radisic 1 , Ole Luhn 1 2 , Bart Swinnen 1 , Wouter Ruythooren 1 , Philippe Vereecken 1
1 , IMEC, Leuven Belgium, 2 MTM, Katholieke Universiteit Leuven, Leuven Belgium
Show Abstract12:00 PM - E3.7
A Method for Die Thickness Reduction to sub-35 µm.
Jeffrey Thompson 1 , Gary Tepolt 1 , Livia Racz 1 , Chris Rogers 2 , Vincent Manno 2 , Robert White 2
1 Advanced Hardware, C.S. Draper Laboratory, Cambridge, Massachusetts, United States, 2 Mechanical Engineering, Tufts University, Medford, Massachusetts, United States
Show AbstractSignificant system performance improvements can be realized by stacking die layers. This approach, known as 3-D integration, can reduce RC delay as well as the system form factor. Die are typically thinned in wafer form prior to integration into the modules allowing even greater functional density. However, certain applications require the thinning of individual die. A detailed technique including die lamination, lapping, chemical mechanical planarization (CMP), and release has been developed to thin die to sub-35 µm. During lamination, the die are temporarily adhered with their active side down to a glass substrate using an adhesive. Mechanical lapping is performed to remove the majority of silicon from the back side. The final thickness of approximately 35 µm is achieved using CMP. The CMP step is critical for the removal of sub-surface damage and prevention of device failure. After thinning, the adhesive is dissolved and the die are handled using porous end effectors. The process can effectively produce die thinned to sub-35 µm with ± 1.5 µm total thickness variation (TTV).
12:30 PM - E3.9
Statistical Analysis of the Influence of Thinning Processes on the Strength of Silicon.
Yu Yang 1 2 , Ricardo Teixeira 1 , Philippe Roussel 1 , Bart Swinnen 1 , Bert Verlinden 2 , Ingrid De Wolf 1 2
1 IPSI, IMEC, Leuven Belgium, 2 MTM, KUL, Leuven Belgium
Show AbstractWafer thinning, one of the key enabling techniques for 3D integration, is widely studied due to its impact on Si breakage strength. However, most studies only focused on the average strength, without checking the failure mechanisms. This may result in misleading conclusions and the mechanism of breakage is still ambiguous.In this paper, the mechanical strength of wafers that were thinned using different methods [rough grinding(RG), fine grinding(FE), plasma etching(PE), chemical mechanical polishing(CMP)] was evaluated statistically and through failure analysis. The results provide the industry guidance on their wafer thinning strategy.Si wafers were thinned down to 300μm by different thinning techniques: only RG; RG+FG; RG+FG+10μm CMP and RG+FG+10μm PE. Next the samples were diced into strips and the strength was tested using a 4-point bending test.The breakage strength of the dies was plotted in Weibull graphs and on wafer maps. Both RG and PE samples showed a strong bimodal distribution. On the other hand, both FG and CMP wafers showed a monomodal behaviour. This observation was unexpected and until now never reported in literature. The RG wafer has large surface grooves and is the weakest one, as expected. The bimodal distribution of the strength of RG-dies could be related to the direction of the grinding marks on the surface (along width or length of the Si strips). There is a direct correlation with the position of the dies on the wafer and the bimodal distribution. Samples with lines perpendicular to the tensile stress (along the width of the strips) are more vulnerable than the rest. The fracture on these samples propagates vertically from the ground surface, along the {110} plane. The others are stronger and break along the {111} plane. FG improves both the surface roughness and the strength compared to RG. The Weibull curve, with a monomodal behavior, shifts to a higher breakage strength, indicating that the effect of the grooves on the breakage strength is removed by FG. After CMP, the strength raises 17% compared to FG-Si due to the removal of surface roughness. Similarly, PE increases the average strength by 15% from FG. However, the Weibull plot shows that after PE, there is again a bimodal failure distribution. The weaker one falls on top of the FG distribution and the stronger one mixes up with the CMP. This indicates that although a large fraction of these samples have a similar strength as CMP, but some parts still have defects, probably local roughness related, that serve as easy initiation of fracture. This study shows that the orientation of the grinding marks plays an important role in determining the fracture plane and thus the strength. FG can efficiently remove this effect. We also showed for the first time that even after PE there is a bimodal strength distribution. Part of the dies has the same strength as the ones after CMP, but part of the population still has a lower strength.
12:45 PM - E3.10
Oxidized ALD-deposited Titanium Nitride Films as a Low-temperature Alternative for Enhancing the Wettability of Through-Silicon Vias (TSVs).
Mohamed Saadaoui 1 , Henk Van Zeijl 1 , Hoa Pham 1 , Harm Knoops 2 , Erwin Kessels 2 , Yann Lamy 3 , Wim Besling 3 , Fred Roozeboom 3 2 , Lina Sarro 1
1 DIMES ECTM, TU-DELFT, Delft Netherlands, 2 Department of Applied Physics, Eindhoven University of Technology, Eindhoven Netherlands, 3 , NXP-TSMC Research Center, Eindhoven Netherlands
Show AbstractThrough-silicon vias (TSVs) are vital for enabling 3D interconnects. The enhanced electrical performance together with the low cost and the high density of integration are the major benefits. For high aspect ratio vias (HAR > 10), copper bottom-up electroplating techniques are often used in order to overcome the limited metal coverage that sputter deposition techniques exhibit. During the electroplating process in deep vias, both diffusion and natural convection are manifested. In order to maintain proper mass transfer regime and guarantee spontaneous flow of the electrolyte inside the vias, the wettability of the layer covering the vias sidewalls should be to be enhanced. The results are voids free interconnect with high electrical performances and low electromigration failure. In this paper we report on the deposition of an oxidized titanium nitride (TiNxOy) layer by plasma enhanced atomic layer deposition (PE-ALD) and processed further within the TSVs to serve as both a barrier against copper diffusion and a wetting layer during the electroplating process. The low temperature of the PE-ALD process and the high conformality of the layer make it an extremely suitable layer for the realization of IC compatible through silicon interconnects. The vias are 300 µm deep and 20 µm wide (HAR of 15) and are formed by deep reactive ions etching (DRIE) of silicon. The TiNxOy film exhibits super-hydrophilic properties after UV exposure with a linear decrease of the contact angle for water from 50° (as deposited) to 5° or less with increasing UV exposure time. X-ray Photoelectron Spectroscopy (XPS) analysis is performed on planar wafers with 30nm thick TiNxOy to clarify the oxidation process and determine the uniformity of the layer in the via. The bottom-up copper electroplating process employed to metalize the TSVs covered with this super-hydrophilic TiNxOy shows a very stable electroplating potential which is indicative for a well-controlled process. The morphology of the plated copper as well as the wetting/barrier layer boundary is determined by TEM image analysis. The Cu filled TSVs lined with the TiNxOy layer are then further processed into cross-Kelvin structures realized on both sides of the wafer and electrically characterized using an automatic procedure under HP 4156B microprobes station to scan the entire wafer. These TSVs exhibit a very low average resistance (around 50 mΩ) with a 25% uniformity across the wafer. This corresponds to an equivalent resistivity of 4.76 μΩ.cm for the specific aspect ratio investigated in this study.
E4: 3d Packaging and Epi 3D
Session Chairs
Tuesday PM, December 02, 2008
Room 205 (Hynes)
2:30 PM - **E4.1
The Promise of 3D ICs With Through Silicon Vias.
Sitaram Arkalgud 1
1 , Sematech, Albany , New York, United States
Show Abstract3:00 PM - **E4.2
Recent Technology and Material Developments in 3D Packaging and Assembly.
Marc de Samber 1 , Eric van Grunsven 1 , Gerard Kums 1 , Anton van der Lugt 1 , Hans de Vries 1
1 , Philips Applied Technologies, Eindhoven Netherlands
Show AbstractAbstract The trend towards further integration and miniaturization has driven the electronics R&D community to using the 3rd dimension in packaging and assembly. This is a main challenge in terms of adapting or renewing, e.g., assembly technologies, materials, electrical design tools and modeling. 3D assembly and packaging has been introduced already more than 10 years ago with the use of MCMs (multi-chip modules) that typically combine in a single package various ICs (from different origin) and that are built on ceramic substrate carriers or silicon carriers with integrated passives. Recent developments go much further, and stacks of multiple memory dies are now commonly used. However lots of challenges remain to be solved, such as stacking of non-identical dies, low cost vertical interconnections, multi-physics modeling for mixed-functionality in fluidic, medical imaging and optical applications, etc. The paper will give an overview of the most recent developments in our R&D institute for various industrially relevant applications and using various technical approaches. Focus is always on finding industrial solutions. An approach that is always preferred in this respect is to use or modify ‘packaging platforms’ and to re-using technologies that are known from other application fields. This is to allow faster technology and product introduction. For the various applications different approaches and technical solutions will be discussed. When implementing die stacks inside electronic packages one focus is on finding and exploring the optimal vertical interconnections using so-called Through Silicon Vias (TSV) and on determining technologies and materials that still allow using the standardized packaging without jeopardizing the quality and reliability. Recently new materials for via filling have been studied.However next to using TSVs in 3D assemblies other methods are studied. One is based on integrating (embedding) active dies into a ‘smart’ printed board assembly. Methods and material for that will be elaborated on.In MEMS packaging for physical sensors there is a trend to realizing (semi) hermetic sealing of the MEMS functionality using some kind of 3D assembly (Si cap assembled onto MEMS wafer). The focus here is on finding the proper sealing material between cap and MEMS die, with the target to be able to next overmold the MEMS device in a standard plastic package.New challenges arise when packaging and using the 3rd dimension for non-electrical functionalities, such as optical devices, magnetic devices and biomedical devices. Various examples from the field of LED based illumination, high complex optical systems and medical X-ray imaging will be given. For these examples the main challenges and achievements will be analyzed and discussed.
3:30 PM - **E4.3
Die-to-Wafer 3D Integration Technology for High Yield and Throughput.
Katsuyuki Sakuma 1 , Paul Andry 2 , Cornelia Tsang 2 , Yukifumi Oyama 3 , Kuniaki Sueoka 1 , Steven Wright 2 , Raymond Horton 2 , Bing Dang 2 , Chirag Patel 2 , Robert Polastre 2 , Edmund Sprogis 4 , John Knickerbocker 1
1 Tokyo Research Laboratory, IBM, Yamato, Kanagawa, Japan, 2 T.J. Watson Research Center, IBM, Yorktown Heights, New York, United States, 3 Systems and Technology, IBM, Shimogyo-ku, Kyoto, Japan, 4 Systems and Technology, IBM, Essex Junction, Vermont, United States
Show AbstractTuesday, 12/2New Presenter *E4.3 @ 2:30 PMDie-to-Wafer 3D Integration Technology for High Yield and Throughput. John U. Knickerbocker
4:15 PM - **E4.4
3D MEMS and IC Integration.
Maaike Taklo 1 , Nicolas Lietaer 1 , Hannah Tofteberg 1 , Timo Seppanen 2 , J. Prainsack 3 , Josef Weber 4 , Peter Ramm 4
1 Microsystems and Nanotechnology, SINTEF ICT, Oslo Norway, 2 , Infineon Technologies SensoNor AS, Horten Norway, 3 , Infineon Technologies , Graz Austria, 4 , Fraunhofer-IZM, Munich Germany
Show Abstract4:45 PM - E4.5
Laser Crystallization of Si Films for Fabricating 3-D Integrated Circuits.
Gabriel Ganot 1 , Monica Deep 1 , P. van der Wilt 1 , U. Chung 1 , A. Chitu 1 , A. Limanov 1 , James Im 1
1 Program in Materials Science and Engineering, Columbia University, New York, New York, United States
Show AbstractLaser-induced melt-mediated crystallization of amorphous or polycrystalline Si films corresponds to a long investigated and still compelling approach for directly generating crystalline Si films that can permit multiple-level fabrication of transistors for realizing 3-D integrated circuits. Here, it can be noted that directional solidification of the films using cw-lasers (often additionally involving epitaxial seeding through an underlying oxide layer to the single-crystal Si substrate) represents the primary technical method pursued in the past; unfortunately, the directional solidification process is prone to introducing various microstructural defects (such as sub-grain boundaries and twins) in a spatially heterogeneous manner, and the seeding procedure unavoidably introduces additional process- and design-related complications and constraints.In this paper, we present alternative laser crystallization techniques that may enable, among other things, realization of highly functional 3-D integration by effectively and efficiently providing SOI-quality {100}-surface-oriented single-crystal regions in an initially amorphous layer. Much of our present work leverages and builds on the advances that were made in the course of developing pulsed-laser-based crystallization techniques for making high-performance polycrystalline Si-based TFTs on glass substrates. The approaches we present in this paper involve modifications and optimization to the pulsed-laser-induced controlled-lateral-solidification techniques referred to as sequential lateral solidification (SLS) and controlled-super-lateral growth (C-SLG) [Sposili and Im, APL 69 p2864, 1996; Im et al., Phys. Stat. Sol. (a) 166 p603, 1998]. One specific and critical component of the present work entails the use of (100) surface textured precursor polycrystalline Si films (which, for this work, was obtained via a crystallization method referred to as mixed-phase solidification (MPS), performed using a frequency-doubled Nd:YVO4 cw-laser (532 nm) [Van der Wilt, et al., Proc. SPIE 61060B-1, 2006]).It is shown that SLS or C-SLG of (100) textured 100-nm-thick polycrystalline Si films implemented using excimer laser irradiation (308 nm, 30~300 nsec) can yield, albeit to a limited spatial extent (~a few μm), location-controlled single-crystal regions that are apparently and essentially free of planar and other detectable intra-grain defects, whilst preserving the (100) texture of the grains. In the case of other surface orientations, defects were found to be systematically and typically promptly generated to varying degrees. The experimental details extracted using TEM, SEM, and EBSD techniques that substantiate this correlation will be presented. We will also discuss how the process may be implemented in a practical manner in semiconductor manufacturing environments.
5:00 PM - E4.6
Pulsed Current Annealing of Lithographically Defined Si Wires on Insulating Substrates for Single Crystal Si Ribbon Formation for 3D Integration.
Ali Gokirmak 1 , Gokhan Bakan 1 , Cicek Boztug 1 , Adam Cywar 1 , Nathan Henry 1 , Mustafa Akbulut 1 , Helena Silva 1
1 Electrical and Computer Engineering , University of Connecticut, Storrs, Connecticut, United States
Show Abstract5:15 PM - E4.7
Seeded Crystallization of Amorphous Semiconductors by Vertical Epitaxial Ge Nanowires: A Possible Approach to Dense 3-D Integrated Circuits.
Shu Hu 1 , Paul Leu 1 , Paul McIntyre 1 2
1 Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 , the Geballe Laboratory for Advanced Materials, Stanford, California, United States
Show AbstractCrystallization of amorphous semiconductors is one way to achieve 3-D integration by adding a second active device layer over a pre-existing layer of silicon circuitry. This approach has the potential to increase circuit performance by stacking multiple functional layers (e.g. dense memory arrays, on-chip optoelectronics, sensors) on Si metal-oxide-semiconductor device layers, and by enabling heterogeneous integration of misfitting semiconductor materials (e.g. Si and Ge). Single crystalline, vertical nanowires (NWs) of Si and Ge hold promise for transferring the orientation and perfection of the underlying Si single crystal substrate to overlying device layers by seeded crystallization. For example, thin film germanium can be crystallized from an amorphous state by seeded nucleation at the tips of vertical germanium nanowires (Ge NWs) with which it is in contact. In principle, this technique could be repeated to build multiple device layers for monolithic 3-D integration. A key requirement is to achieve a device quality semiconductor layer on a typically amorphous interlayer dielectric (e.g. deposited SiO2) which separates neighboring device layers. Here, we demonstrate that seeded crystallization can produce micron-scale, thin Ge crystals using vertically aligned <111> Ge NWs that are grown heteroepitaxially on Si (111) substrates, and then encapsulated in micron-thick deposited SiO2. Chemical mechanical polishing (CMP) was applied to planarize and expose the Ge NWs in cross-section, which produced seeds for crystallization of an overlying 50 nm thick amorphous-Ge film. Liquid phase epitaxy was used to crystallize a-Ge layer during post-deposition rapid thermal anneals at temperatures above its melting point. A detailed study of the crystalline quality of the crystallized a-Ge layers using transmission electron microscopy, selected area electron diffraction, electron back-scattered diffraction patterns, and x-ray diffraction will be reported.
5:30 PM - E4.8
Oxide-based Electronic Switching Devices for 3D Stack Oxide Memory.
Bo Soo Kang 1 , Ki Hwan Kim 1 , Myoung-Jae Lee 1 , Seung Eon Ahn 1 , Chang Bum Lee 1 , Genrikh Stefanovich 1 , Chang Jung Kim 1 , Youngsoo Park 1
1 Semiconductor Lab., Samsung Advanced Institute of Technology, Yongin-si, Gyeonggi-do, Korea (the Republic of)
Show AbstractAs the limitation of memory density based on two dimensional scaling is expected in both physical and technological aspects in near future, development of 3-dimensionally stackable structure is greatly desired. Since high temperature processes of the current silicon technology is prone to induce degradation of the underlying layers, fabrication of electronic devices using low temperature process of non-Si semiconductors is necessary. We have integrated an oxide-based memory array composed of memory elements (resistance switching NiO), switch elements (CuO/InxZn1-xOy thin film diode), and selection elements (ZnO-based transistor). In order to embody the resistance switching memory array, there are many requirements of the switching devices. High current density is required to supply enough current needed to switch the NiO layer. High on/off current ratio is required to prevent crosstalk and guarantee the array operation. Other issues include compatibility with metal electrodes and low temperature process. Considering bandgap diagram, CuO and InxZn1-xOy were employed as p-type and n-type materials for a heterojunction thin film diode, respectively. The maximum current density was 3.5×104 A/cm2 and the on/off current ratio was 106 at ±2 V. The issues regarding thermal stability of the oxide diode and transistor are discussed.
5:45 PM - E4.9
Fabrication and Reliability of Wafer-level MEMS Packaging.
Yoon-Chul Sohn 1 , Suk-Jin Ham 1 , Ji-Hyuk Lim 1 , Byung-Gil Jeong 1 , Jong-Oh Kwon 1 , Woon-Bae Kim 1 , Chang-Youl Moon 1
1 Materials & Devices Research Lab, Samsung Advanced Institute of Technology, Yongin, Gyeonggi-do, Korea (the Republic of)
Show AbstractE5: Poster Session
Session Chairs
Wednesday AM, December 03, 2008
Exhibition Hall D (Hynes)
9:00 PM - E5.1
Characterization of Texture and Microstructure of Electrodeposited Ni Layer.
Homuro Noda 1 , Akinobu Shibata 2 , Masato Sone 2 , Chiemi Ishiyama 2 , Yakichi Higo 2
1 Department of Materials Science and Engineering, Tokyo institute of technology, Yokohama Japan, 2 Precision and Intelligence Laboratory, Tokyo institute of technology, Yokohama Japan
Show AbstractIn recent years, MEMS (Micro Electro Mechanical System) devices have been studied intensively. MEMS consists of three dimensional structure of micro mechanical system and electronic circuit formed by stacking the thin films. The electrodeposition is a major method to make thin films for MEMS devices. Generally, electrodeposited layer has a complex texture or microstructure depending on the plating condition (current density, plating temperature, etc.). Because these texture and microstructure can have an influence on the mechanical properties of thin film itself as well as the adhesion strength between thin film and substrate, it is important to understand the their formation mechanism. In the present study, the texture and microstructure in electrodeposited Ni layers formed from an additive-free Watt’s bath were investigated in detail. In the present study, two kinds of substrates were used; annealed Cu (fcc) and Ni-P (amorphous). Ni-P amorphous substrate was formed by electroless deposition on Cu. Ni layer was electrodeposited onto such kinds of substrates from an additive-free Watt’s bath with a current density of 150A/m2 at 323K. Microstructures of electrodeposited Ni layers were observed by means of scanning electron microscopy (SEM) and transmission electron microscopy (TEM). Texture analysis was performed by pole figures and inverse pole figures obtained by of X ray diffraction (XRD). Electron back scattered diffraction pattern (EBSD) was also used to analyze the texture of Ni layer.The microstructure of the Ni electrodeposited layer consists of fine columnar grains extending in the growth direction. The major texture components of Ni electrodeposited layer onto Ni-P substrate were (112) or (110) fiber. Because Ni-P substrate has an amorphous structure, texture formation is unbiased by substrate. Consequently, this texture is the one that is determined only by the deposition condition of the present study. In contrast to the case of Ni-P substrate, Ni electrodeposited layer onto Cu substrate has a strong (110) fiber texture. This texture is presumably developed by the preferential growth of the grains which have the epitaxial relationship with respect to the (110) oriented grains of Cu substrate.This results demonstrate that the thin film with specific texture can be fabricated for the MEMS device.
9:00 PM - E5.2
A Generic Heterogeneous 3D Integration Platform Based on Post-Processing.
Fengda Sun 1 , Yusuf Leblebici 1
1 Microelectronic Systems Laboratory, Ecole Polytechnique Fédérale de Lausanne, Lausanne, Vaud, Switzerland
Show Abstract9:00 PM - E5.3
Low Temperature Growth of Silicon Structures for 3-D Flash Memory Devices.
Thomas Mih 1 , Richard Cross 1 , Shashi Paul 1
1 Emerging Technologies Research Centre, De Montfort University, Leicester United Kingdom
Show AbstractMemory devices play a vital role in consumer electronic applications. Flash memory, a type of non-volatile memory ideal for portable applications such as mobile phones, digital cameras, laptop computers, has evolved over the years since its invention. Despite the enormous commercial success over the years, current flash memory technology has some limitations for which a number of solutions are sought[1-4]. One such solution is 3-D integrated logic [4] in which a number of memory layers are stacked on the top of a silicon wafer using conventional CMOS technology.
The flash memory industry widely employs chemical vapour deposition techniques to grow polycrystalline silicon which is used as the information storage element. The growth temperatures of this technique are typically greater than 600oC. These high temperatures not only result in high thermal budgets in the fabrication of flash memory, but could also adversely affect device performance of next generation 3-D flash memory devices where the need for high memory density and performance requires thinning down the substrates supporting the memory layers. Therefore, the development of low temperature processes is of fundamental importance to this future 3-D integration.
In this paper, we report for the first time the growth of low temperature poly-Si at temperatures < 400oC using radio frequency plasma enhanced CVD from silane plasmas using organometallic material. The optical bandgaps of the poly-Si films grown have been obtained using ultraviolet-visible (UV-VIS) absorption spectroscopy and the dark conductivity and photoconductivity properties of the films were investigated in a light-tight box under illumination of 100 mW/cm2 using an Oriel a solar simulator. In addition, results will also be presented of the I-V and C-V characteristics of MIS structures incorporating the low temperature poly-Si films, and discussions given of the feasibility of the inclusion of these films in 3-D memory devices.
References
1.S. Paul, IEEE Transactions on Nanotechnology 6, 2, (2007) 191-195
2. S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe and K. Chan; J. Appl. Phys. Lett., 68(10), (1996), 1377
3. S. Koliopoulou, P. Dimitrakis, P. Normand, S. Paul, et. al., J. Appl. Phys. 94(8), (2003), 5234
4. S. Koliopoulou, P. Dimitrakis, D. Goustouridis et. al., Microelectronic Engineering, 83, (2006), 1563.
9:00 PM - E5.5
Effect of Nanotwin on Abnormal and Normal Grain Growth in Pulse Electrodeposited Copper.
Di Xu 1 , Luhua Xu 1 , Vinay Sriram 1 , Jenn-Ming Yang 1 , King-Ning Tu 1
1 Materials Science and Engineering, University of California, Los Angeles, Los Angeles, California, United States
Show AbstractAbnormal and normal grain growth have been studied extensively for Cu thin films and Cu interconnect lines because they happen at room temperature. Uncontrollable abnormal and normal grain growth can lead to inhomogeneous distribution of microstructure, which is undesirable. Direct current (DC) electroplated Cu films without nanotwins and pulse electroplated Cu films with high density of nanotwins were investigated for abnormal grain growth at room temperature and normal grain growth under 200 degree C for 1 hour. Electron Backscatter Diffraction (EBSD) was performed for grain orientation and grain size characterization. We found that with a high density of twins (either growth twin from pulse plated Cu or annealing twins from annealed DC plated Cu), Cu films showed little abnormal grain growth after 1 year at room temperature and weak normal grain growth under 200 degree C for 1 hour. In contrast, those Cu films with few nanotwins underwent prominent abnormal and normal grain growth. These results suggested that nanotwins have a strong effect on abnormal and normal grain growth upon annealing.
Symposium Organizers
Fred Roozeboom NXP Semiconductors Research
Christopher Bower Semprius, Inc.
Phil Garrou Microelectronic Consultants of NC
Mitsumasa Koyanagi Tohoku University
Peter Ramm Fraunhofer Institute IZM Munich
E6: Materials and Modeling
Session Chairs
Wednesday AM, December 03, 2008
Room 205 (Hynes)
9:30 AM - **E6.1
Fabrication Method using Wet Etching Technology for Multi-layer Stacked Devices.
Miyakawa Nobuaki 1 , Hashimoto Eiri 1 , Maebashi Takanori 1 , Nakamura Natsuo 1 , Sacho Yutaka 1 , Nakayama Shigeto 1 , Toyoda Shinjiro 1
1 , Honda Research Institute Japan Co., Ltd., Wako, Saitama, Japan
Show AbstractIntroductionMany research organizations have been developing the stacking technology using TSV; and there are many trials for the stacking process method, for example, chip-to-chip, chip-to-wafer, wafer-to-wafer, etc [1],[2]. The chip-to-wafer technology using a known good die is connected to a good chip on another wafer, such that the overall yield can be improved, at the expense of extra testing cost for KGDs. The wafer-to-wafer stacking method is one of the fabrication methods for mass production, though the failed chips areincluded in the wafer. This method is good for high-throughput manufacturing, with the disadvantage of lower yield compared to a chip-to-wafer stacking method. For the practical use of the stacking device we must investigate the reduction of a number of the stacking process steps, the improvement of the electrical connectivity between each layer, and the test method of the stacked device after the stacking process etc.We introduce a new 3-dimensional stacking technology using a wafer-to-wafer stacked method.Proposed ProcessAlmost all previous cases had to have back-side metal of the upper layer for the stacking between the upper layer and lower layer, therefore the process needed an isolation layer to avoid an electrical short circuit between the substrate and the back-side metal. As a result, the total process is lengthened due to adding the two processes.We have developed a wafer-to-wafer stacking method which applies a direct connection between metal TSV and bump, and a wafer thinning method using wet etching technology to reduce total process steps.Experimental ResultsWe have tried the prototype of 3-layerstacked devices using our technology, in which each wafer is structured by a microprocessor, custom circuits, and 64Mbit SDRAM, respectively.Test wafers have been fabricated using 0.18μm CMOS technology, where each wafer for the stacking is fabricated based on 8-inch wafers. Electrical conductivity between each layer is almost 100% and contact resistance between TSV of upper wafer and a surface bump of lower wafer is less than 0.7Ω. The frequency distribution by 6 stacking wafers of the connection portion between 3 layers was very sharp.The prototype devices showed sophisticated functionality by testing, and the yields gotten from the results comprising all functional tests are over 60%..Issue of the Future Application The 3D stacking technology is very promising as a future technology due to many benefits, such as high performance, low power, smaller footprint, and the enabling of heterogeneous technology integration.Large electrical systems such as computer systems need the larger band width of the bus and reduce signal delay distortion among bus signals. For high performance, TSV must be made of metal to decrease the resistance value. Reference[1] ISSCC 2007 Forum on the “ Design of 3D-Chipstacks” Feb.11[2] RTI “ 3D Architectures for SemiconductorIntegration and Packaging” 2004 -2007
10:00 AM - **E6.2
Hotspot-Optimized Interlayer Cooling in Vertically Integrated Packages.
Thomas Brunschwiler 1 , Bruno Michel 1 , Hugo Rothuizen 1 , Urs Kloter 1 , Bernhard Wunderle 3 , Hermann Oppermann 3 , Herbert Reichl 2 3
1 , IBM Research, Rüschlikon Switzerland, 3 , Fraunhofer Institute for Reliability and Microintegration, Berlin Germany, 2 , Technische Universität Berlin, Berlin Germany
Show AbstractTraditional back-side cooling approaches are limited to vertically integrated chip stacks with one single high-performance logic layer and multiple memory layers. To exploit the full potential of 3D integration, scalable heat-removal concepts are necessary. In forced convective interlayer cooling, the coolant is pumped between the active layers and scales with the number of strata in the stack. With uniform heat removal geometries, 180 W/cm2 per layer at 100-um interconnect pitch can be removed. From an electrical perspective. pitches of 10 to 50 um are desirable. Unfortunately the acceptable heat flux drops drastically at 50 um to below 100W/cm2, which is not sufficient for high-performance chip stacks with local heat dissipation of more than 150 W/cm2. In this publication, we present concepts to extend interlayer cooling to interconnect pitches down to 50 um. On a typical processor, only 20 to 40% of the area is covered with cores. They dissipate four to six times the heat flux of the cache area, and are called thermal hot spots. At these core locations, the interconnect density is typically twice that of the cache areas. Uniform heat transfer structures are not optimal for such non-uniform conditions. Here we therefore demonstrate hot-spot-optimized heat-transfer concepts.We modulate the heat-transfer structure according to the local heat flux and fluid temperature. At locations having low heat flux, large hydraulic diameters with high convective resistance but low pressure needs are acceptable as a means to stay below the junction temperature limit. Numerical algorithms are presented to define the optimal local channel width for micro-channels. Another approach is to use all four sides (four-port) of the package for fluid in- and outlets. For a quadratic chip, the maximum channel length in the center is equal to the length of all straight channels in the two-port configuration, but the effective flow length is reduced for channels located towards the corners and accordingly, the channel flow rate towards the chip corners is increased. Using computational fluid dynamics (CFD) modeling, we demonstrate that four-port configurations are most beneficial if the hot spots are in corner areas. The third building block presented is fluid focusing. Guiding structures channel the fluid towards hot-spot locations. The structure needs to be balanced such that areas with low heat flux still receive sufficient cooling to stay below the maximum junction temperature. The problem is solved numerically using the porous-media approach with input parameters from experiments. By combining the hot-spot cooling methods described above, the optimal heat transfer structure with the lowest pumping-power need can be achieved. This structure has to be defined using the chip power map and the local electrical interconnect density as input. As a result, we were able to extend interlayer cooling from a minimal pitch of 100 um down to below 50 um.
10:30 AM - **E6.3
Thermo-Mechanical Reliability Investigation of Through-Silicon-Vias and Inter-connects for 3D Systems Integration.
Bernhard Wunderle 1 , J. Weber 2 , R. Mrossko 1 , E. Kaulfersch 1 , P. Ramm 2 , B. Michel 1 , H. Reichl 3
1 , Fraunhofer Institute Reliability and Microintegration, Berlin Germany, 2 , Fraunhofer IZM, Munich Division, Munich Germany, 3 , Technische Universitat Berlin, Berlin Germany
Show Abstract11:30 AM - **E6.4
Design Support for 3D System Integration by Multi Physics Simulation.
Peter Schneider 1 , Sven Reitz 1 , Jorn Stolle 1 , Roland Martin 1 , Andreas Wilde 1 , Peter Ramm 2 , Josef Weber 2
1 , Fraunhofer IIS/EAS, Dresden Germany, 2 , Fraunhofer IZM , Munich Germany
Show AbstractEmerging technologies for three-dimensional integration of sensors, electronics for signal processing and communication enable a wide range of new applications. Due to interconnect structures in the third dimension new functional concepts, but also opportunities for improved thermal management or electromagnetic shielding become possible. However, designers are faced with new challenges coming from 3D integration, e.g.:- electrical characteristics of inter-chip via (ICV) structures especially for high frequencies,-different mounting conditions of dies within the stack, inducing changes with respect to heat transfer and mechanical stability,-additional pad and shape constraints due to 3D interconnect technology,-electrical interconnects crossing the dies, implying the risk of substrate coupling to active regions and-altered device characteristics after thinning of wafers, especially for ultrathin silicon.Thus, the application of 3D integration technologies is associated with a couple of uncertainties. To proceed towards real 3D design it is necessary to have information about the influence of the interconnect structures on the system behavior. Therefore, investigations by measurements of test structures and by multi-physics simulations are needed, to achieve this information and provide it as design rules or guidelines.In the paper a methodology and its application is presented, which deals with different physical effects, integration variants and design tools. It comprises -a modular modeling approach, which consists of a tool-independent structural representation as a basis for semi-automatic generation of models for PDE solvers,-detailed simulations with PDE solvers with subsequent derivation of device characteristics and design rules,-computer-aided model generation for system level simulation, supported by various methods like optimization and model order reduction,-integration of data into the design flow using SPICE macro models or behavioral models as well as dedicated data formats for parasitics like SPEF.The application of this modeling approach is focused on thermal analysis of 3D systems and investigations of the electrical behavior of interconnect structures especially at high frequencies above 1 GHz. But, also the analysis of thermo-mechanical effects, especially for MEMS integration is carried out. The suitability of this approach is currently proven for several technologies, like Au stud bumps or micro solder balls. Extensively, a post Backend-of-Line “via first” 3-D integration technology developed by Fraunhofer IZM was investigated. It is called ICV-SLID and is based on vias through the device substrates and metal bonding using solid-liquid-interdiffusion (SLID) soldering. The SLID metal system provides mechanical and electrical connections, both in one single step. In the paper results from multi physics simulation for different integration technologies are presented.
12:00 PM - **E6.5
Through Silicon via Metallization: a Novel Approach for Insulation/Barrier/Copper Seed Layer Deposition-based on Wet Electrografting and Chemical Grafting Technologies.
D. Suhr 1 , J. Gonzales 1 , I. Bispo 1 , Frederic Raynal 1 , C. Truzzi 1 , Steve Lerner 1 , Vincent Mevellec 1
1 , Alchimer S.A., Massy France
Show AbstractWednesday, 12/3New Abstract Title/Authors *E6.5 @ 11:00 AMInsulation/Barrier/Copper Seed Layer Deposition-based on Wet Electrografting and Chemical Grafting Technologies.D. Suhr1, J. Gonzales1, I. Bispo1, Frederic Raynal1, C. Truzzi1, Steve Lerner1, Vincent Mevellec1 1. Alchimer S.A., Massy, France.
12:30 PM - E6.6
Self Assembly of Die to Wafer using Direct Bonding Methods and Capillary Forces.
Francois Grossi 1 , Léa Di Cioccio 1 , Francois Rieutord 1 , Olivier Renault 1 , Jean Berthier 1 , Jean-Charles Barbé 1 , Francois De Crécy 1 , Laurent Clavelier 1
1 , CEA-LETI-MINATEC, Grenoble France
Show AbstractNowadays 3D integration technology enables to bring together processed wafers, layers, dies and devices in one chip. It aims to create and develop innovative systems on a chip. Die-to-wafer assembly is preferred to the wafer-to-wafer approach since it allows better yield. To provide a growing demand on precision and speed, self assembly becomes promising thanks to its parallel aspect, especially regarding the tools used currently in robotics.In literature, self-assembly is mainly achieved by shape recognition surface and/or surface functionalization with self assembled monolayers (SAM). We have developed an original self-assembly method, using surface preparation methods inherited from wafer bonding: thanks to selective exposure to a surface treatment we are able to create a substrate with heterogeneous surface state, especially with silicon. We are building a hydrophilic zone surrounded by hydrophobic zones. We are also able to create a locally wettable and bondable substrate with protrusions standing for bonding zones on it.We are using chemical treatments inherited from direct bonding for the force which provides attachment of the die. This force is high enough to withstand post-processing such as thinning down or via etching for interconnects. The aim here is to create 3D aligned microelectronic devices with vertical connection.This effect of selective surface wetting generates a capillary force which allows moving the die to the good bonding alignment if they were originally misaligned. Higher wettability contrast improves the restoring force of the die. It is induced by the surface treatments or thanks to the use of different substrate materials.We observed that the water drop volume needed to be controlled to maximize the self alignment efficiency. We will present modellization studies provided by the “Surface Evolver” software regarding the free movement capability induced by the wettability contrast. This helps to determine optimal parameters such as initial misalignment or the steady state of the initial drop once the alignment has happened.Moreover, self alignment may happen also on a fully treated surface with topology such as protrusion. We were able to adapt our method with a surface patterned: we created a surface with a grid-like structure on it to separate the bonding zones. This type of structure may receive a homogeneous surface treatment and still be able to perform self assembly. On the other hand, thanks to the bonding of double-sided polished dies we could stack several silicon dies with this method. These die-to-die or die-to-wafer bonded structures have similar characteristics at the interface to wafer-to-wafer bonded structures.We are now able to characterize within the micrometer accuracy how close our chips are aligned to the bonding zone: results of alignment thanks to infrared control on alignment patterns will be presented and discussed.
12:45 PM - E6.7
Grain Boundary Engineering in Copper Through-via Silicon Interconnects.
S. Ratanaphan 1 2 , D. Xu 2 , L. Xu 2 , Dierk Raabe 1 , K. Tu 2
1 , Max-Planck-Institut fuer Eisenforschung, Duesseldorf Germany, 2 Department of Materials Science and Engineering, University of California, Los Angeles, California, United States
Show AbstractWe introduce the concept of Grain Boundary Engineering (GBE) into the fabrication and design of copper through-via silicon interconnects which is the key technology for 3D wafer stacking integration. By controlling the current density during electroplating, highly dense twin boundary and void free structures were obtain in copper interconnects (100um in diameter and 300um in height). The microstructure evolution along the deposition length of copper interconnects was characterized by high resolution Electron Backscatter Diffraction (EBSD).The microstructure of the copper columns was found to have a fiber texture with strongly preferred orientations in (110) crystallographic direction parallel to Growth Direction (GD). The Sigma 3 twin boundary is a primary grain boundary (38% of all grain boundaries). The average grain size in longitudinal sections was approximately 5.27um^2 and 111.06um^2 in longitudinal direction including twin and excluded twin boundaries, respectively. This observation underlines the role of the twin boundary distribution in the material. The EBSD investigation in the cross section of the freshly deposited surface showed that the twin boundaries are originated from the adjoining edge of newly formed grains. The thermal stability and thermal strain induced microstructure evolution are performed in an isothermal annealing at 300 degrees centigrade for 2 hours for three kinds of set-ups: copper through-via silicon; copper through-via silicon with a deposited cap on top, and free standing copper.