Symposium Organizers
Andrew Kummel, University of California, San Diego
Alexander Demkov, University of Texas, Austin
John Robertson, Cambridge Univ
Shinichi Takagi, University of Tokyo
ED7.1: Memory I
Session Chairs
Andrew Kummel
Dirk Wouters
Tuesday PM, April 18, 2017
PCC North, 100 Level, Room 131 A
11:30 AM - *ED7.1.01
Computing with Coupled Dynamical Systems
Suman Datta 1 , Nikhil Shukla 1 , A. Parihar 2 , V. Narayanan 3 , A. Raychowdhury 2
1 , University of Notre Dame, Notre Dame, Indiana, United States, 2 , Georgia Institute of Technology, Atlanta, Georgia, United States, 3 , The Pennsylvania State University, State College, Pennsylvania, United States
Show AbstractWhile Boolean logic is the backbone of information processing, there are computationally hard problems like optimization and associative computing where this method is inadequate. This motivates us to look for new pathways to a solution. Here we introduce an experimental testbed of compact coupled relaxation oscillator based on the insulator-metal transition in the correlated oxide, vanadium dioxide (VO2), to efficiently solve the approximate match between stored and input patterns.
VO2 exhibits a metal-insulator transition (IMT) with a large, abrupt change in resistivity. Connecting a resistive load like a MOSFET in series with the VO2 induces a negative differential resistance across the phase transition which can enable relaxation-type oscillations. Low-power oscillators can be realized through dimensional scaling making VO2 oscillators an attractive candidate for oscillator-based computing.
We use the phase synchronization dynamics of pairwise, capacitively coupled VO2 relaxation oscillators to calculate a distance norm which is required for finding a ‘degree of match’ relevant to associative computing applications; the time domain waveforms of the synchronized oscillators. To understand the phase synchronization dynamics, we explore the phase space behavior of the coupled oscillators.
This work is supported by the National Science Foundation Expeditions in Computing Award-1317560.
12:00 PM - ED7.1.02
Growth of NbO2 by Molecular-Beam Epitaxy and Characterization of its Metal-Insulator Transition
Lindsey Noskin 1 , Darrell Schlom 1 2
1 Materials Science and Engineering, Cornell University, Ithaca, New York, United States, 2 , Kavli Institute at Cornell for Nanoscale Science, Ithaca, New York, United States
Show AbstractMaterials with temperature-dependent metal-to-insulator transitions (MIT) have gained attention for use in conjunction with metal-oxide-semiconductor field-effect transistors (MOSFET) to reduce the sub threshold slope of MOSFETs to beat the 60 mV/decade Boltzmann limit [1]. Recent advancements show that MITs can be harnessed to produce reversible switching when the MIT material in connected in series with the transistor’s source. To achieve practical MOSFET operation temperatures, however, MIT materials with transition temperatures below 400 K are unsuitable. This necessity rules out most MIT materials, including VO2. Previous research on NbO2 shows an MIT at 1060 K, with a change in electrical resistivity of three orders of magnitude between 400 K and 1100 K [2]. Using oxide molecular-beam epitaxy (MBE) we have synthesized thin films of NbO2 on MgF2 substrates, which like NbO2 have the rutile structure. Two growth parameters have been systematically varied in order to discover optimal growth conditions: growth temperature and the partial pressure of O2 during film growth. X-ray diffraction theta-2theta measurements identify two dominant phases in this system: rutile NbO2 is favored in lower oxygen environments, while Nb2O5 grows in high oxygen partial pressure. The dependence of resistivity vs. temperature and electrically induced MIT switching on the growth conditions of the NbO2 films will be presented.
[1] N. Shukla, A.V. Thathachary, A. Agrawal, H. Paik, A. Aziz, D.G. Schlom, S.K. Gupta, R. Engel-Herbert, S. Datta, “A steep-slopetransistor based on abrupt electronic phase transition,” Nat. Comms., 6 (7812) [2015] 1-5.
[2] G. Belanger, J. Destry and G. Perluzzo, “Electron-Transport in Single-Crystals of Niobium Dioxide,” Can. J. Phys., 52 (22) [1974] 2272.
12:15 PM - ED7.1.03
Infrared Near-Field Spectroscopy of Free Charge Carriers at Grain Boundaries in Sr1-xLaxTiO3 Ceramics on the nm-Scale
Martin Lewin 1 2 , Fabian Gaussmann 2 , Jochen Wueppen 2 , Sebastian Nyga 2 , Bernd Jungbluth 2 , Rainer Waser 3 4 , Thomas Taubner 1 2
1 Institute of Physics (IA), RWTH Aachen University, Aachen Germany, 2 , Fraunhofer Institute for Laser Technology (ILT), Aachen Germany, 3 Institute of Electronic Materials (IWE 2), RWTH Aachen University, Aachen Germany, 4 , Juelich Aachen Research Alliance - Fundamentals of Future Information Technology (JARA-FIT), Aachen Germany
Show AbstractTransition metal oxides, like SrTiO3, are candidates for future non-volatile memory devices due to their resistively switching nature. The switching in SrTiO3 is described as Valence Change Mechanism (VCM), but up to now the fundamental microscopic process is still under debate.[1] Integral electronic transport measurements and local conductivity atomic force microscopy studies point to a strong connection of the resistive switching phenomenon and local defects. In case of Sr1-xLaxTiO3 ceramics modeling of impedance spectroscopy data implies that the switching process is governed by grain boundary effects.[2, 3] Spatially resolved analysis is still missing.
Infrared spectroscopic measurements can be used to address the phonons to gain information about the crystal structure and to analyze the contributions from free charge carriers. However, the spatial resolution of conventional far-field measurements is usually limited to approximately half of the applied wavelength. In combination with scattering-type Scanning Near-field Optical Microscopy (s-SNOM) infrared spectroscopic analyses of the electrical and structural properties of the ceramics on the nm-scale become feasible.[4] Like in atomic force microscopy, a metal coated tip is scanned over the sample. At the sharp apex of the tip evanescent near-fields are excited by infrared laser irradiation. Due to the local near-field interaction, subwavelength spatial resolution in the order of the tip radius (approximately 25 nm) can be achieved.
Using s-SNOM in combination with a specially developed broad-band laser system [5] we observed significant local inhomogeneities (circular spots, mosaic shaped boundaries) in the infrared near-field response of Sr1-xLaxTiO3 ceramics. These inhomogeneities can be ascribed to differences in the local charge carrier density and damping by a combined Drude-phonon analysis. A comparison of local near-field spectra to integral far-field infrared spectra of low, average and highly doped Sr1-xLaxTiO3 ceramics supports this assignment.
1 R. Waser et al., Adv. Mater. 21, 2632 (2009).
2 R. Moos, K.-H. Härdtl, J. Appl. Phys. 80, 393 (1996).
3 S. Hirose et al., J. Appl. Phys. 104, 053712 (2008).
4 F. Keilmann and R. Hillenbrand, Philos. Trans. R. Soc. A 362, 787 (2004).
5 S. Bensmann et al., Opt. Express 22, 22369 (2014).
12:30 PM - ED7.1.04
Molecular Beam Epitaxy Grown NbO2 Thin Films for Selector Devices
Alexander Demkov 1 , Tobias Hadamek 1 , Agham Posadas 1 , Hyunsang Hwang 2 , JaeHyuk Park 2
1 , University of Texas, Austin, Texas, United States, 2 , Pohang University of Science and Technology, Pohang Korea (the Republic of)
Show AbstractIn this study, niobium oxide films of varying stoichiometry were first grown by molecular beam epitaxy (MBE) on (111) oriented perovskite substrates (La,Sr)2(Al,Ta)2O6 (LSAT) and SrTiO3 (STO) to determine the optimal growth conditions for the growth of stoichiometric and highly crystalline NbO2. The growth of stoichiometric NbO2 was epitaxial with the c-axis of NbO2 oriented in plane (along the perovskite <110> directions) and with (110) out-of-plane orientation, which led to the formation of three rotational domains on the 6-fold symmetric perovskite (111) substrates. The MBE process that was found to yield the optimal NbO2 films in terms of their stoichiometry and crystallinity for growth on the perovskite substrate as described above was further used to deposit crystalline and stoichiometric 20 nm films of NbO2 on a TiN bottom electrode. The so-grown selector device was subjected to electrical I-V measurements with a parameter analyzer to analyze its selector device characteristics with switching fields of ~ 1 MV/cm. It was found that the E-IMT in these films follow an electroforming (soft breakdown)-free characteristic and are hence superior to NbO2 films grown by sputtering techniques which require an electroforming step in order to observe the typical selector characteristics of NbO2. In comparison with the sputter-deposited NbOx film, the electroforming process was almost eliminated in the MBE-deposited NbO2 film. This is likely due to the fact that electroforming causes local crystallization of the film in sputtered films, whereas the MBE-grown film was already in a polycrystalline state as grown.
12:45 PM - ED7.1.05
A Novel Forming-Free Bipolar Resistive Memory Based On ITO/V2O5/ITO Structure
Zhenni Wan 1 , Robert Darling 1 , M.P. Anantram 1
1 , University of Washington, Seattle, Washington, United States
Show AbstractElectroforming process in resistive random access memory (RRAM) usually requires a large voltage that is a few times higher than the switching voltage and thus exposes severe electrical and mechanical stresses to the MIM memory element. Reducing or even eliminating the forming step is valuable for practical applications. Forming-free bipolar resistive switching behavior in a ITO (150nm)/V2O5 (900nm)/ITO (150nm) structure is observed for the first time. While the bottom ITO layer functions as a common ground electrode, the top ITO layer is an active element and used as an oxygen reservoir with an additional metal electrode patterned on its top for making contact. Our device exhibits a low resistance state (LRS) in its virgin state, and is switched to a high resistance state (HRS) when a forward bias of ~+2.5V is applied. The device can be reset to its original state at a reverse bias of ~–1.5V. Transient response of the device to applied voltage pulses with widths of 200ns in a full programming and erasing cycle is also tested, confirming that no forming process is required and the device has the potential to work in high speed circuit.
Top metal contacts (20nm Cr/260nm Al/20nm Cr) with different diameters ranging from 30µm to 100µm are patterned by shadow mask during e-beam evaporation. Interestingly, a noticeable decrease of switching voltage with reduced top contact area is observed. The lowest switching voltage (+2.5V) is observed when a probe tip with 2µm diameter is directly in contact with the top ITO layer, and the highest switching voltage (+6.8V) is with contact diameter of 100µm. Our results indicate a strong electric field enhanced effect associated with the switching as the electric field beneath the top metal contact increases when decreasing the contact area, and the switching is likely to occur at the interface instead of conductive filaments. We explain the switching behavior by the migration of oxygen ions at top ITO/V2O5 interface. When oxygen ions are extracted to the ITO side during the forward sweep, an interfacial layer with reduced oxidation states is formed and acts as a thin tunneling barrier that suppresses the current through the whole device. When a reverse bias is applied, oxygen ions are attracted back to V2O5 lattice, fill in the vacancies and lower the tunneling barrier, resulting a low resistance state. Although the ITO/V2O5/ITO structure seems to be symmetrical, asymmetry in electrical properties is observed when a reverse sweep is applied first. No resistive switching occurs up to -4V and the I-V characteristics of the device remain resistor-like. Bipolar switching appears only when a forward bias is applied to the top electrode. This observation implies that oxygen ions do not migrate at the bottom V2O5/ITO interface and the two interfaces are asymmetric, which can be explained by the asymmetric fabrication processes. The results suggest future application in low power, high speed and highly integrated circuit.
ED7.2: Memory II
Session Chairs
Alexander Demkov
John Robertson
Tuesday PM, April 18, 2017
PCC North, 100 Level, Room 131 A
2:30 PM - *ED7.2.01
ReRAM Devices—From New Memory to Beyond von Neumann Computing Applications
Dirk Wouters 1
1 , RWTH Aachen University, Aachen Germany
Show AbstractReRAM are resistive switching devices operating by nanoscale movement of atomic defects. They are ultimately scaling emerging memories enabling devices smaller than 5x5nm2. Their properties (programming speed, endurance, and operation voltage) are superior to established Flash memories, making ReRAM technology ideally suited for a new type of Storage Class Memory that will improve system performance by bridging the huge latency gap between DRAM working memory and NAND-Flash storage. However promising, a number of important challenges remain as intrinsic variability and limited memory window. Further understanding of the material related physical mechanisms is hereby required to bring this technology to the market.
Besides their application as non-volatile memory, the memristive properties of ReRAM enable new logic-in-memory computation schemes (e.g. using implication logic), which would solve the speed and energy bottleneck related to the data transfer between processor and memory. Also, ReRAM devices have been proposed as synthetic synapses for dense neuromorphic circuits, showing both short and long time pulse time dependent plasticity effects. These developments are seen as important possibilities for surpassing the von Neumann bottlenecks to computation.
3:00 PM - ED7.2.02
Oxygen Stoichiometry Controlled Resistive Switching Modes in HfOx and TaOx Based RRAM Devices
Sankaramangalam Sharath 1 , Stefan Vogel 1 , Erwin Hildebrandt 1 3 , Jose Kurian 1 , Philipp Komissinskiy 1 , Thomas Schroeder 2 3 , Lambert Alff 1
1 Institute of Materials Science, TU Darmstadt, Darmstadt Germany, 3 , Brandenburgische Technische Universität, Cottbus, Cottbus Germany, 2 , IHP, Frankfurt Germany
Show AbstractResistive Random Access Memory (RRAM) devices based on resistive switching in hafnium oxide (HfO2) and tantalum oxide (TaOx) are being investigated extensively as emerging embedded nonvolatile memories. In such filamentary based RRAM devices, it is important to control the structure and understand the nature of the filament which depends strongly on the electroforming process. In turn, a lowered forming voltage as realized by oxygen stoichiometry engineering [1] is being investigated towards realization of reproducible high yield RRAM technology. Oxygen engineering in HfOx and TaOx thin films has been achieved via strongly oxygen deficient growth parameters using rf plasma assisted molecular beam epitaxy (MBE) which can stabilize oxygen vacancy concentrations far beyond the thermodynamical equilibrium [2]. We show that the density of polycrystalline HfOx as well as amorphous TaOx thin films grown at CMOS compatible temperatures (< 440 oC) can be controlled in a wide range between metallic (Ta, Hf) and bulk density of the oxides (Ta2O5, HfO2). At 320 oC, sub-stoichiometric HfOx crystallizes in an oxygen vacancy stabilized higher symmetry tetragonal-like phase (t-HfO1.5) as compared to monoclinic symmetry (m-HfO2) at higher oxidation conditions. A large sub-stoichiometry led to a defect band at the Fermi-level as observed by X-ray photoelectron spectroscopy (XPS) indicating the conducting nature of these sub-stoichiometric films. The forming voltages in a Pt/MOx/TiN based device configuration can be controlled to close to operating set voltages using these highly oxygen deficient TaOx and HfOx thin films. Further electrical switching measurements in such Pt/MOx/TiN based devices show that, while a bipolar switching occurs in all the devices irrespective of oxygen stoichiometry, switching modes like unipolar and threshold switching is favored only at higher oxygen stoichiometry [3]. This is attributed to higher heat dissipation and lowered concentration gradient of oxygen vacancies in sub-stoichiometric TaOx and HfOx devices. In Pt/HfO1.5/TiN based devices, the occurrence of switching at both interfaces leading to a complementary switching is attributed to nature of the filament. In addition, the observation of intermediate quantized conductance states in set/reset switching could be due to the interplay between oxygen sub-stoichiometry induced modulation of Joule heating and electric field effects. This knowledge about the dependence of different switching modes (bipolar, complementary, unipolar, threshold) on oxide stoichiometry is crucial for design of RRAM devices with appropriate functionality.
[1] S. U. Sharath et al., Appl. Phys. Lett. 105, 073505 (2014).
[2] E. Hildebrandt et al., J. Appl. Phys. 112, 114112 (2012).
[3] S. U. Sharath et al., Appl. Phys. Lett. 109 (17), accepted (2016).
3:15 PM - ED7.2.03
The Effect of Oxygen Exchange Layer on the Performance of Tantalum Oxide-Based RRAM
Zahiruddin Alamgir 1 , Joshua Holt 1 , Nathaniel Cady 1
1 , State University of New York Polytechnic Institute, Albany, New York, United States
Show AbstractResistive random access memory (RRAM) has emerged as a forerunner for replacing existing non-volatile memory because of its CMOS compatibility, simple structure, excellent scalability, fast speed and high endurance. Different oxide materials have been proposed and demonstrated as switching materials, including TiOx, HfOx, TaOx, and SiOx. Among these materials, TaOx has been shown to have excellent switching endurance and speed. For many transition metal oxide based RRAM devices, an oxygen exchange layer (OEL) is placed between the top electrode and the oxide to scavenge oxygen and thereby modify the stoichiometry of the oxide. This layer is believed to play an important role in device switching uniformity, forming voltage, endurance, and retention. In this work we report the effect of varying the OEL on memory performance of TaOx based RRAM devices. Titanium, Hf, Ta, and Zr were deposited between the TaOx switching layer and the W top electrode, and the resulting device switching performance was compared. These materials have varying degrees of oxygen scavenging ability and thus should result in different oxygen vacancy profiles within the switching (oxide) layer. Analysis of oxygen profiles within these layers is ongoing, and will be compared to the resultant switching behavior of the RRAM devices. Ultimately this approach provides a means to optimize device performance, and can shed light on physical switching mechanisms of metal oxide based RRAM.
3:30 PM - *ED7.2.04
In Case of Emergency Break the Z-Glass Ceiling—Thin Film Processes for Advanced Integration and Devices
R. Clark 1 , T. Hakamata 1 , K. Tapily 1 , K.-H. Yu 1 , S. Consiglio 1 , D. O'Meara 1 , J. Smith 1 , D. Newman 1 , C. Wajda 1 , G. Leusink 1
1 , TEL Technology Center, America LLC, Albany, New York, United States
Show AbstractThe latest version of the ITRS suggests clearly that while Moore’s law itself may be slowing, the pace of innovation in system, process and device technology is continuing to accelerate. Atomic-scale printed feature sizes require us to harness the vertical or Z-dimension in order to continue Moore’s law-like device number per square unit area increases without relying solely upon traditional device area footprint scaling. The logic, flash and DRAM segments of the semiconductor industry have each made recent advances in the Z-dimension with 3-dimensional device structures and in the case of flash, monolithic 3D integration. New deposition and etch processes including selective depositions and etches are required in order to enable and make use of new non-planar device architectures (e.g. FinFETs, gate all-around nanowire FETs, and stacked DRAM capacitors), device arrays/stacking (e.g. 3D NAND and cross-point memory), and 3D integration (e.g. monolithic 3D, and chip stacking). Selective deposition and etch processes can simplify existing manufacturing flows, and may enable new integration schemes that will help to continue system performance and cost scaling into the future. Another factor driving new process development is the need to simultaneously reduce the device power as parasitic RC inherently increases with continued feature scaling. All currently available semiconductor devices rely in some way on moving current through a metal-semiconductor interface, which is limiting due to its inherent resistance. Taking logic devices as an example, FinFET and nanowire FET (NWFET) structures required for scaling have exacerbated the already significant manufacturing issues related to forming an acceptable metal-semiconductor contact. Thus new conformal processes are needed in order to optimize not only the specific contact resistivity of the interface, but also the metal-semiconductor contact area by creating a wraparound contact (WAC) structure. Likewise, the need to continue device and voltage scaling is driving innovations in materials engineering. So called High K films are finding new uses or being altered to provide new electrical effects such as ferroelectricity. This talk will give examples of the processes we are currently researching and developing to meet the challenges of the next decade and serve as a bridge to the processes that will continue scaling a decade from now.
4:30 PM - *ED7.2.05
Quantum Computing in Silicon with Donors
Michelle Simmons 1
1 UNSW Australia, Centre for Quantum Computation and Communication Technology, Kensington, New South Wales, Australia
Show AbstractExtremely long electron and nuclear spin coherence times have recently been demonstrated in isotopically pure Si-28 [1,2] making silicon one of the most promising semiconductor materials for spin based quantum information. The two level spin state of single electrons bound to shallow phosphorus donors in silicon in particular provide well defined, reproducible qubits [3] and represent a promising system for a scalable quantum computer in silicon. An important challenge in these systems is the realisation of an architecture, where we can position donors within a crystalline environment with approx. 20-50nm separation, individually address each donor, manipulate the electron spins using ESR techniques and read-out their spin states.
We have developed a unique fabrication strategy for a scalable quantum computer in silicon using scanning tunneling microscope hydrogen lithography to precisely position individual P donors in a Si crystal [4] aligned with nanoscale precision to local control gates [5] necessary to initialize, manipulate, and read-out the spin states [6]. During this talk I will focus on demonstrating spin transport [7] and single-shot spin read-out of precisely-positioned P donors in Si. I will also describe our approaches to scale up using rf reflectometry [8] and the investigation of 3D architectures for implementation of the surface code [9].
[1] K. Saeedi et al., Science 342, 130 (2013).
[2] J. T. Muhonen et al., Nature Nanotechnology 9, 986 (2014).
[3] B.E. Kane, Nature 393, 133 (1998).
[4] M. Fuechsle et al., Nature Nanotechnology 7, 242 (2012).
[5] B. Weber et al., Science 335, 6064 (2012).
[6] H. Buch et al., Nature Communications 4, 2017 (2013).
[7] B. Weber et al., Nature Nanotechnology 9, 430 (2014).
[8] M.G. House et al., Nature Communications 6, 8848 (2015)
[9] C. Hill et al., Science Advances 1, e1500707 (2015).
5:00 PM - ED7.2.06
Impact of In Situ Reducing Plasma Treatments on the Electrical Properties of RRAM Devices Based on ALD Deposited Al2O3 Dielectric Material
Brice Eychenne 1 2 , Patrice Gonon 1 2 , Marceline Bonvalot 1 2
1 , LTM-CNRS, Grenoble France, 2 , CEA-LETI, Grenoble France
Show AbstractNon-volatile RRAM memories, in which the dielectric material undergoes an electrically induced resistive switching, are an active research subject in microelectronics. The switching mechanism is thought to originate from the formation of a conductive filament induced by oxygen vacancy migration in the insulating material and charge injection from the electrode material. This switching behavior is observed in most insulating oxides such as HfO2, ZrO2, Ta2O5 and TiO2, which have been put on trial for this purpose. But conflicting results emerge in the literature regarding the specific case of Al2O3. Multiple studies show that using low work function electrode material such as TiN allows resistive switching of Al2O3.However we could never observe any resistive switching in as-deposited ALD Al2O3 cells using high work function electrode materials such as platinum. We believe that ALD deposition of Al2O3 inhibits resistive switching of the RRAM cell; indeed, the high energy required for charge injection and oxygen vacancy creation leads to a current overshoot in the dielectric material, consequently yielding to irreversible dielectric breakdown.
To assess these observations, we used an in-situ plasma hydrogen treatment in order to induce oxygen vacancies in the Al2O3 layer. The Al2O3 dielectric material has been deposited on the Pt bottom electrode by plasma-enhanced ALD with TMA as a precursor and an O2 plasma as an oxidant. The reducing plasma treatment has been applied between a various number of ALD cycles, prior to the Pt top electrode deposition. Both duration and frequency of plasma exposure have been varied, while chamber pressure and plasma power was maintained respectively at 200 mTorr and 300 W.
XPS measurements have been carried out to evaluate chemical state of Al2O3. As expected, results show that two states of Al oxidation are present in H2 treated oxides while only Al3+ can be detected in as-deposited Al2O3. The MIM resistive switching behavior has been evaluated by I-V and C-V measurements. Electrical characterizations show that resistive switching can be obtained on high work Pt material when the ALD Al2O3 layer has been treated by a H2 plasma. In addition, SET and RESET voltages are significantly reduced as compared to as deposited Al2O3. The electrical characteristics of the MIM also seem to be dependent on the in-situ plasma treatment conditions. This study supports the theory that resistive switching in RRAM cells is driven by filamentary conduction of oxygen vacancies. All these results will be discussed in the light of literature data.
5:15 PM - ED7.2.07
Investigation of the Cell-to-Cell Interference Induced by the Bended ONO Structure in 3D NAND Flash Memories
Won-Hyo Cha 1 , BongReol Park 1 , Jaehyun Chung 1 , Kyeong Rok Kim 1 , Hae Soon Oh 1 , Byeong Chan Bang 1 , Jung Woo Lee 1 , Han Soo Joo 1 , Yong Seok Suh 1 , Seok Won Cho 1 , Se Kyung Choi 1 , Ki Seog Kim 1 , Myoung Kwan Cho 1 , Heehyun Chang 1 , Jin Woong Kim 1
1 , SK HYNIX, Chung-Ju Korea (the Republic of)
Show AbstractThe 3-dimensional NAND flash memories(3D NAND) based on the charge trap device(CTD) had adopted to overcome degradation of the cell characteristics due to the scaling limitation of 2-dimension NAND flash memories(2D NAND) with the floating gate(FG). One of the main problem is the cell-to-cell interference phenomenon in PGM operation. The characteristics of the cell-to-cell interference are caused by stored electrons in adjacent cell. The interference characteristics of 3D NAND are much smaller than that of 2D NAND, because of using the insulator as a charge trap layer. Even though the cell-to-cell interference characteristics are better than that of 2D NAND, it could be increased final distribution of cells Vth in 3D NAND. It is not negligible in chip operation, which has been relevant to the high performance and reliability of the application.
In this paper, we have studied the mechanism of the cell-to-cell interference in accordance with the shape of charge trapped layer. The shape of charge trap layer has influenced the electric field and density of trapped electron distribution. We had a good cell-to-cell interference characteristics in bended charge trap layer toward word-line, however bended charge trap layer toward word-line had a poor reliability due to changing electric field profile. We characterized the bended charge trap layer, by electrical and physical methods, using transmission electron microscope (TEM), TCAD simulation and cell characteristics(IV and program/erase speed). We also investigated distribution caused by cell-to-cell interference, endurance and reliability properties in chip with each of experiments. Through the experiments, we investigated that the shape of charge trap nitride affected on the cell-to-cell interference and reliability properties. Finally we optimized the shape of charge trap nitride to obtain best performance in chip operation.
References
[1] Byungkyu Cho et al., IMW, 1 (2011).
[2] Yi-Hsuan Hsiao et al., IMW, 1 (2011).
5:30 PM - ED7.2.08
Controllable Formation of Conductive Filament by Selective Oxidation near the Tip-Region of Pyramid-Structured Active Electrode in Resistive Memory
Youngjin Kim 1 2 , Keun-Young Shin 1 , Jong Hyuk Park 1 , Sang-Soo Lee 1 2
1 , Korea Institute of Science and Technology, Seoul Korea (the Republic of), 2 KU-KIST Graduate School of Converging Science and Technology, Korea University, Seoul Korea (the Republic of)
Show AbstractThe formation of conductive filaments (CFs) within an insulating medium of resistive random access memory (RRAM) is critical factor in the determining memory performance of the filamentary-based RRAM. However, random formation and additional growth of CFs have still deteriorated the reliability and uniformity in resistive switching (RS) behavior. Herein, we demonstrate that the filament grows up in limited region via selective oxidation of structured active electrode arrays which have a high-quality tip and uniform size fabricated by template-stripping method. Since the tip-enhanced electric fields and high surface energy can facilitate the ionization of active metal and their ion-hopping of generated metal ion, the nucleation and growth of CF occurs only within tip region of Cu pyramid electrode. Moreover, the average forming voltages and their standard deviation for 20 pyramid-based cell were 0.645 V and 0.072 V, respectively. The selective oxidation and formation of CF were directly observed using electron microscopy analyses with elementary analysis of CF and were confirmed using theoretical simulation. When the practical estimation for the controlled formation of CF were carried out, the device exhibited excellent uniform and reliable cell-to-cell performance. This approach will promote the practical application in RRAM fields.
5:45 PM - ED7.2.09
The Low Temperature Data Retention Improvement in 1Znm TLC NAND Flash
Jaewook Yang 1 , Hyunyoung Shim 1 , Hae Soo Kim 1 , Honam Yoo 1 , Heonjin Choo 1 , Sangmi Kim 1 , Minchul Lee 1 , Namcheol Jeon 1 , Jihyeun Shin 1 , Keum-Whan Noh 1 , Heehyun Chang 1
1 Flash Development, SK Hynix Inc., Cheongju-si, Chungcheongbuk-do, Korea (the Republic of)
Show AbstractThe demand for TLC NAND Flash has been increasing due to the market shift from MLC to TLC in NAND Flash applications such as tablets, smart phones and SSDs that require cost effective Flash memory. TLC NAND is placed the 8 levels of Vth, which makes program window wider and Vth width narrower than the 4 levels of Vth in the MLC. We solved these problems by scaling down tunnel oxide(Tox) and ONO inter-poly dielectric thickness. But, a thinner Tox and ONO result in the reliability degradation such as data retention, especially, Low Temperature Data Retention(LTDR) [1,2]. We are mostly concerned about the charge loss of the highest programed level which is PV7 Vth in TLC after baking at room temperature, because it has the highest oxide electric field and therefore highest leakage.
In this paper, the results of process experiments for improving LTDR, which are adjustment of nitrogen concentration in Tox, dual p-type doping of floating gate(FG), ONO gate stack composition, are introduced.
A thinner Tox results in the reliability degradation such as data retention and high-field breakdown characteristics. Nitrogen concentration is important to fabricate a reliable Tox due to the small charge trapping amount and the low Stress-induced Leakage current(SILC)[1]. With Tox scaling, nitrogen concentration is adjusted to prevent oxide quality degradation. new condition is observed that nitrogen profile is decreased at interface and in the bulk oxide through Secondary ion mass spectroscopy(SIMS) analysis. The defect-related Charge-to breakdown (Qbd) probability is increased in new condition, which means that intrinsic defect is decreased. SILC characteristic is improved due to lowered interface and bulk trap density.
We developed dual doping of FG, where top of FG is highly doped and bottom is lowly doped. Erase bias of dual doping FG is lower than conventional FG but program speed is not decreased, which results in decreasing erase stress. Also Constant Current Stress Time(CCST) is increased because of suppressing the boron penetration at FG to Tox interface. SILC characteristic and disturbance are improved by decreasing erase stress and lowed interface trap density.
A thinner ONO leads to the increased leakage and charge retention problem at room and hot temperatures due to high electric field on the FG top edges [2]. The thinner ONO results in worse charge loss after P/E cycling because of Poole-Frenkel(PF) effect and Trap Assisted Tunneling(TAT) mechanism. Especially, a top-oxide plays a more important role to determine charge loss. The charge loss decreases as top oxide increses.
We successfully overcame the charge loss at low temperature throughout the advanced process integration technologies in 1Znm TLC NAND, such as nitrogen concentration control in Tox scaling, dual p-type doing of the FG, a top-oxide thickness increasement of ONO .
Symposium Organizers
Andrew Kummel, University of California, San Diego
Alexander Demkov, University of Texas, Austin
John Robertson, Cambridge Univ
Shinichi Takagi, University of Tokyo
ED7.3: CMOS
Session Chairs
Wednesday AM, April 19, 2017
PCC North, 100 Level, Room 131 A
9:00 AM - ED7.3.01
Selective Isotropic Etching of Silicon in Preference to Germanium and Si0.5Ge0.5
Christopher Ahles 1 , Jong Choi 1 , Richard Yang 2 , Andrew Kummel 1
1 , University of California, San Diego, La Jolla, California, United States, 2 , LAM Research, Fremont, California, United States
Show AbstractAs CMOS technology is scaled down to <10nm, new MOSFET architectures are required in order to maintain control over the device. The optimal design for such a device is the gate-all-around (GAA) architecture. Whereas in previous CMOS generations the MOSFETs were planar structures, GAA structures require highly selective isotropic etching for device fabrication. Previous isotropic gas phase selective etching of silicon employed sulfur passivation of Ge which can dope silicon, corrode process equipment, and cause ion mobility in dielectrics. In this report a sulfur-free isotropic selective etch is reported which has essentially infinite Si/Ge etch rate ratio (ERR) and Si/Si0.5Ge0.5 ERR > 300:1 using in a downstream plasma. The etch rates were simultaneously measured in-situ using a reactor chamber equipped with dual quartz crystal microbalances (QCMs). After in-situ removal of the surface oxides with a downstream NF3/H2 plasma, the Si and Ge films were dosed with gas from a downstream plasma of H2, CF4 and Ar. It was found that high Si/Ge(Si0.5Ge0.5) ERRs can be obtained over a wide range of H2/CF4 gas flow ratios, QCM temperatures and chamber pressure. For the optimal process window, there is an etch rate >1nm/min for Si and deposition of carbon onto Ge and Si0.5Ge0.5. The nature of the passivation layer has been investigated via XPS as well as isotopic labeling. The data is consistent with the less exothermic reaction of fluorine radicals with Ge and Si0.5Ge0.5 being strongly suppressed by a 2ML thick CxHyFz. Replacing H2 with D2 in the feed gas results in an increase of the Si and Si0.5Ge0.5 etch rates by a factor ~36. This D2 enhancement of the etch rates is consistent with a primary kinetic isotope effect resulting in less efficient scavenging of atomic F by CxDyFz species compared to CxHyFz species.
9:15 AM - ED7.3.02
Reducing Fermi Level Pinning at Contacts on Ge by Germanides
Hongfei Li 1 , John Robertson 1
1 , University of Cambridge, Cambridge United Kingdom
Show AbstractThe performance of highly scaled CMOS devices are limited by contact resistances, and in turn by the Schottky barriers (SBs) at these contacts. Fermi level pinning (FLP) stops us using different metals to minimise SB heights. It was noted that FLP is less for silicides on Si than for elemental metals themselves [1]. We calculate the barrier heights for germanides on Ge, as a function of the metal work function. We chose NiGe2 and YGe2 on Ge as lattice matched interfaces. We also calculate work functions of the germanides using supercells models. We find a pinning factor of S ~ 0.5. This means that rare earth germanides will have small n-type SB heights on Ge. This has recently been observed experimentally [2].
[1] L. Lin, Y. Guo, J. Robertson, Appl. Phys. Lett. 101 052110 (2012)
[2] T. Nishimura, T. Yajima, A. Toriumi, Tech Digest SSDM (Tsukuba, 2016) O-6-02
9:30 AM - ED7.3.03
Trap Characterization and Capacitance-Voltage Hysteresis of Al2O3/InGaAs Gate Stacks
Kechao Tang 1 , Felix Palumbo 2 , Ravi Droopad 3 , Paul McIntyre 1
1 , Stanford University, Stanford, California, United States, 2 , National Scientific and Technical Research Council, Buenos Aires Argentina, 3 , Texas State University, San Marcos, Texas, United States
Show AbstractFor future high performance III-V NMOS devices, In0.53Ga0.47As is a promising channel material due to its high electron mobility. Atomic layer deposited (ALD) Al2O3 has a large conduction band offset to InGaAs and can form a low defect-density interface with InGaAs.1 However, reliability studies of devices including an Al2O3/InGaAs interface show positive bias temperature instability (PBTI) is significantly greater in magnitude and weaker in gate voltage dependence compared to Si devices.2, 3 Moreover, there is a clear gate bias-induced degradation of the transconductance and subthreshold swing of Al2O3/InGaAs nMOSFETs.3 A deeper understanding of bias-dependent changes in MOS properties is required to achieve better reliability of InGaAs MOS devices. In this study, we explore the effects of MOS gate stack processing conditions and the initial interface density (Dit) and border trap density (Nbt) on the bias-dependent capacitance-voltage (C-V) hysteresis of Al2O3/InGaAs gate stacks, an important indicator of device reliability.
Four Al2O3/InGaAs gate stacks were prepared using different procedures. One set of samples were prepared by in-situ desorption of a protective As2 capping layer, followed immediately by Al2O3 ALD to give an abrupt interface. Another set of samples were made by inserting a 5-day room air exposure between the As2 decapping and the Al2O3 ALD, to intentionally degrade the interface quality by surface oxidation of the InGaAs substrate. A portion of the each set of MOS capacitors were thermally treated using a 5%H2/95%N2 forming gas anneal (FGA) after thermal evaporation of Pd gate electrodes. CV hysteresis measurements were performed on these four types of samples having significant variations in interface and border trap density. Both for gate stacks with intentional air exposure and with in-situ As2 decapping prior to ALD, even though FGA is very effective in reducing both the Dit and Nbt by passivation of the dangling bonds, it leads to larger hysteresis under bias stress and degraded stability of Al2O3/InGaAs stacks. The degradation of stability after FGA is attributed to the field-driven depassivation of incorporated hydrogen atoms from the dangling bonds at the interface or in the bulk of the Al2O3. The hydrogen depassivation at the interface is supported by a notable increase of Dit for the post-FGA samples and little change of Dit for the pre-FGA ones after the hysteresis measurement. In addition, when H2 FGA is replaced by deuterated FGA, the C-V data for the gate stacks remain the same but a decrease in the measured hysteresis is detected. This isotope effect suggests that the mass difference of H and D atoms affects the hysteresis behavior, consistent with the idea of slower field-driven depassivation of defects by deuterium than by hydrogen.
[1] J. Ahn, et al., Appl. Phys. Lett. 103 (2013), 071602 [2] F. Palumbo et al., J. Appl. Phys. 117 (2015), 104103 [3] J.Franco et al., IEEE IRPS, May 2014.
9:45 AM - ED7.3.04
Temperature Dependent Border Trap Response Produced by a Defective Interfacial Oxide Layer in Al2O3/InGaAs Gate Stacks
Kechao Tang 1 , Andrew Meng 1 , Ravi Droopad 2 , Paul McIntyre 1
1 , Stanford University, Stanford, California, United States, 2 , Texas State University, San Marcos, Texas, United States
Show AbstractFor future highly-scaled n-channel metal-oxide-semiconductor (MOS) devices, In0.53Ga0.47As and atomic layer deposited high-k dielectrics are among the candidate channel and dielectric materials, respectively.1 As defects that degrade the on-state performance of the device, apart from the well-known oxide/InGaAs interface charge traps, electrically-active defects in the oxide layer, called border traps, have also gained increasing attention.2 In multi-frequency capacitance-voltage (C-V) measurements, unlike the interface trap response that diminishes greatly with decreasing temperature, a very weak temperature dependence of the border trap response in accumulation is frequently observed.3 Nevertheless, several recently published reports indicate that the accumulation capacitance dispersion of InGaAs/high-k gate stacks decreases by more than 50% from room temperature (RT, ~300 K) to 77 K.4 In this research, we investigate the origins of the varying temperature dependence of the dispersive trap response measured in accumulation, and find that these discrepancies are correlated with the abruptness and defect density of the InGaAs/high-k interface.
Intentional oxidation of an As2-decapped (100) In0.57Ga0.43As substrate by additional H2O dosing during initial Al2O3 gate dielectric atomic layer deposition (ALD) increases the interface trap density (Dit), lowers the band edge photoluminescence (PL) intensity, and generates Ga-oxide detected by x-ray photoelectron spectroscopy (XPS). Aberration-corrected high resolution transmission electron microscopy (TEM) reveals formation of an amorphous interfacial layer which is distinct from the Al2O3 dielectric and which is not present without the additional H2O dosing. Observation of a temperature dependent border trap response, associated with the frequency dispersion of the accumulation capacitance and conductance of MOS structures, is found to be correlated with the presence of this defective interfacial layer. MOS capacitors prepared with additional H2O dosing show a notable decrease (~20%) of accumulation dispersion over 5 kHz to 500 kHz when the measurement temperature decreases from RT to 77 K, while capacitors prepared with an abrupt Al2O3/InGaAs interface display little change (< 2%) with temperature. Similar temperature-dependent border trap response is also observed when the (100) InGaAs surface is treated with a previously-reported HCl(aq) wet cleaning procedure prior to Al2O3 ALD.4 These results point out the sensitivity of the temperature dependence of the border trap response in metal oxide/III-V MOS gate stacks to the presence of processing-induced interface oxide layers, which alter the dynamics of carrier trapping at defects that are not located at the semiconductor interface.
[1] Q. Li et al., IEEE EDL 33, 1246 (2012). [2] K. Tang et al., Appl. Phys. Lett. 107, 212102 (2015). [3] E. J. Kim et al., J. Appl. Phys. 106, 124508 (2009). [4] A. Vais et al., Appl. Phys. Lett. 107, 053504 (2015).
10:00 AM - *ED7.3.05
Bringing III-Vs into CMOS—From Epitaxy to Circuits
Lukas Czornomaz 1 , Veeresh Deshpande 1 , Eamon O'Connor 1 , Marilyne Sousa 1 , Daniele Caimi 1 , Jean Fompeyrine 1
1 , IBM Research GmbH, Ruschlikon, ZH, Switzerland
Show AbstractHigh-mobility channel materials such as InGaAs and SiGe alloys are considered to be the leading candidates for replacing strained Si in future low power/high performance logic circuits. However, the integration of InGaAs on Si and the co-integration of InGaAs devices with SiGe devices are extremely challenging. On the one hand, the large lattice mismatch (8 to 10%) and the potential formation of antiphase domains at the polar/non-polar III-V/Si crystalline interface typically hinder the integration of high quality InGaAs crystals on Si. On the other hand, InGaAs and SiGe require very different processing conditions in terms of thermal budgets, dry and wet chemistries, passivation schemes and contacting schemes which complexifies the realization of CMOS circuits. Recently, tremendous progress were achieved as a result of innovation at the material and device levels [1,2]. In this presentation, we will report on our latest technology developments [3] which yielded the first demonstration of InGaAs/SiGe CMOS inverters and dense SRAM arrays on Si, fabricated with InGaAs selective epitaxy and standard front end of line processes. This novel and scalable CMOS integration scheme enables InGaAs nFET fabrication in close proximity to SiGe pFETs (down to 25 nm spacing), resulting in 6T-SRAM arrays having a minimum cell size below 0.45 μm2. This scheme can be combined with any bulk Si or SOI-based planar or fin technology, and is compatible with standard large-area Si substrate. [1] L. Czornomaz, et al., VLSI Technology (2015), [2] V. Djara, et al., VLSI Technology (2015), [3] L. Czornomaz, et al., VLSI Technology (2016).
11:00 AM - *ED7.3.06
Reliability of Metal Gate/High-K Devices and Its Impact on CMOS Technology Scaling
Andreas Kerber 1
1 , GLOBALFOUNDRIES, Malta, New York, United States
Show Abstract
MG/HK was introduced into CMOS technology and enabled scaling beyond the 45/32nm technology node. The change in gate stack from poly-Si/SiON to MG/HK introduced new reliability challenges like the positive bias temperature instability (PBTI) and stress induced leakage currents (SILC) in nFET devices which prompted thorough investigation to provide fundamental understanding of these degradation mechanisms and are nowadays well understood. The shift to a dual-layer gate stack also had a profound impact on the time dependent dielectric breakdown (TDDB) introducing a strong polarity dependence in the model parameter. As device scaling continues, stochastic modeling of variability, both at time zero and post stress due to BTI, becomes critical especially for SRAM circuit aging. As we migrate towards novel device architectures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices, impact of self-heating needs to be accounted during reliability testing.
In this paper we summarize the fundamentals of MG/HK reliability and discuss the reliability / characterization challenges related to scaling of future CMOS technologies.
11:30 AM - ED7.3.07
Al2O3-HfO2 Nanolaminate Gate Oxides with Organic Precursor on Silicon Germanium
Mahmut Sami Kavrik 1 , Kasra Sardashti 1 , Iljo Kwak 1 , Scott Ueda 2 , Andrew Kummel 2 1
1 Material Science and Engineering, University of California San Diego, La Jolla, California, United States, 2 Chemical Engineering, University of California, San Diego, La Jolla, California, United States
Show AbstractSilicon Germanium (SiGe) alloys are promising alternative for silicon in semiconductor industry due to their tunable bandgap and carrier mobility through variation in composition. However, replacement of Si with SiGe requires a new class of high-k dielectric gate oxides with low leakage current for CMOS processing. Germanium content in semiconductor induces new interface defects due to its bonding with oxygen; GeOx is soluble in water and also can out diffuse into the gate oxide. Al2O3 and HfO2 oxides were incorporated into nanolaminate stacks on the SiGe by Atomic Layer Deposition (ALD). Al2O3 was deposited with organic precursor trimethylaluminum (TMA) and H2O on SiGe at 250C after HF and sulfur surface treatments. Sulfur treatment forms Ge-S and Ge-S-Ge bonds and prevents GeOx formation. Further GeOx suppression was achieved via 20 TMA pre-pulses before Al2O3 deposition to reduce any preexisting GeOx and prevent GeOx formation. Subsequently, HfO2 oxide layers were grown with organic precursor Tetrakis(dimethylamido) hafnium(TDMAH) and H2O at 250C. Al2O3-HfO2 nanolaminates were terminated with one layer of Al2O3 to protect oxide from gate metal damage. MOSCAP studies showed low Dit with hig Cox.
11:45 AM - ED7.3.08
Yttrium Passivation of Defects in GeO2 and GeO2/Ge Interfaces
Hongfei Li 1 , John Robertson 1
1 , University of Cambridge, Cambridge United Kingdom
Show AbstractGe CMOS devices are of great interest because of the high electron and hole mobility of Ge. However, the Ge:GeO2 interface usually suffers from high CV hysteresis and poor stability, which are usually attributed to the charge traps in GeO2 or at the interface. Moreover, Lu and Toriumi have noted that the addition of Y2O3 and some other similar oxides can have a beneficial effect on GeO2 by increasing its network rigidity and improve the electrical stability[1]. They explain it to be the reduction of defect generation rate due to a stronger network. However, the key problem should be how the addition of Y2O3 influences the trapping of charge carrier at existing defects, which is not covered in their paper.
The O deficiency defects in SiO2 behave quite differently to in GeO2. As found by O’Reilly [2], the O vacancy in SiO2 reconstructs to form a Si-Si bond, which only creates gap states close to band edge of SiO2, that is well away from Si gap. On the other hand, the O vacancy can reconstruct to form valence alternation pair (VAP) defect, which also has much smaller formation energy in GeO2 than in SiO2. The critical thing is the VAP defect gives states quite near to Ge band edges[3,4].
We find by density functional calculations, including the screened exchanged band gap correction, that if we substitute the two Ge at the VAP site with Y, the VAP related defect states are removed out of GeO2 gap. Therefore, the addition of Y2O3 has a passivation effect on the O deficiency defects and can reduce charge-trapping centers in GeO2. We explain this by the fact that the two electrons originally localized at VAP site fall into the valence band of GeO2 due to the fewer electrons from 2 Y atoms. This process forms a closed shell configuration and the original defect orbital is now empty and pushed upwards into GeO2 conduction band, thus leaving the gap clean. This passivation mechanism is similar to the passivation of O vacancy in HfO2 by two La atoms, as previously found [5].
[1] C Lu, A Toriumi, J App Phys 116 174803 (2014)
[2] EP O’Reilly, Phys Rev B 27 3780 (1983)
[3] J Binder, A Pasquarello, App Phys Lett 97 092903 (2010); H. Li, J. Robertson, MicroElec Eng 109 244 (2013);
[4] L Zhang,..P C Mcintyre, ACS App Mat Int 8 19110 (2016)
[5] D Liu, J Robertson, App Phys 94 042904 (2009); K Xiong, J Robertson, S J Clark, J App Phys 99 044105 (2006)
12:00 PM - ED7.3.09
High-Dielectric Constant Al2O3 / TiOx Nanolaminates for Next Generation Gates in Nanoscale Devices
Orlando Auciello 1 , Geunhee Lee 1 , Bo-Kuai Lai 2 , Charudatta Phatak 3 , Ram Katiyar 4
1 Materials Science and Engineering & Bioengineering, University of Texas at Dallas, Richardson, Texas, United States, 2 , Lake Shore Cryotronics, Inc., Westerville, Ohio, United States, 3 , Argonne National Laboratory, Lemont, Illinois, United States, 4 , University of Puerto Rico, San Juan, Puerto Rico, United States
Show AbstractHigh dielectric constant materials are critical for applications in nanoscale microelectronics, and as capacitors for energy storage and memory devices. Both Al2O3 and TiO2 have been extensively investigated as high-k materials to replace SiO2 as a gate and for high-capacitance capacitors for electronics. The dielectric constants of Al2O3 and TiO2 are approximately 7 and 80, respectively. Our previous studies showed that amorphous TixAl1-xOy films exhibit dielectric constant of ~30, with 4.8 eV bandgap. Here we report that giant dielectric constants (> 800) can be achieved with Al2O3/TiOx nano-laminates, synthesized by atomic layer deposition (ALD) and with sub-layer thickness ≤ 1 nm, for frequencies up to 106 Hz. The high dielectric constant is attributed to Maxwell-Wagner (M-W) relaxations, resulting from electrical heterogeneity of the multilayers. Al oxidation is favored over Ti-oxide since the Gibbs free energy for Al oxidation is more negative than for Ti. It appears that the Ti-oxide sub-layers are not stoichiometric TiO2, but semiconducting TiOx. The difference in electrical conductivities of the TiOx and Al2O3 layers results in surface charge accumulation at the interfaces. The surface charges relax with AC field and cause M-W relaxation. An interface layer inserted at the interface between top electrode and Al2O3/TiOx nanolaminate is critical to yield high-k up to about 1 MHz with low dielectric losses (~0.02) and low leakage current (~ 10-9 A/cm2). We used ALD to produce large area capacitors via conformal coating of large area ridge arrays fabricated on Si surfaces. These capacitors can yield ≥ 10 µF/cm2 capacitance.
We also report the feasibility of controlling the dielectric properties - high dielectric constant (k) and substantially extended relaxation frequency of thin film nanolaminates (NLs) with various sublayer thicknesses, uniquely realized by ALD process. For 150 nm thick TiOx/Al2O3 NLs with sub-nanometer thick sublayers, few Angstrom change in sublayer thickness dramatically increases relaxation cut-off frequency by more than 3 orders of magnitude (from kHz to MHz) with high dielectric constant (> 800).
The nano-laminates are also explored for applications such as energy storage embedded capacitors in a Si microchip implantable in the human retina to restore sight to people blinded by genetically-induced degeneration of photoreceptors, for supercapacitors integrated with ferroelectric-based high-efficiency photovoltaic devices for energy generation/storage systems, and for high-k gate oxide with low leakage current and losses for next generation DRAMs and nanoscale CMOS devices.
12:15 PM - ED7.3.10
DFT Molecular Dynamic Simulations of Nealy Ideal Sub-Nanometer Interface Passivation Layer for a-HfO2/SiGe Devices and Comparison to Experiment
Andrew Kummel 1 , Evgueni Chagarov 1 , Kasra Sardashti 1 , Iljo Kwak 1 , Michael Yakimov 2 , Serge Oktyabrsky 2
1 , University of California, San Diego, La Jolla, California, United States, 2 , College of NanoScience, Albany, New York, United States
Show Abstract
Density functional theory (DFT) molecular dynamics (MD) simulations are presented for interfaces between a-HfO2 high-K oxide and Si0.5Ge0.5(001) with several amorphous stoichiometric and sub-stoichiometric SiOxNy interlayers (stoichiometric a-SiO0.8N0.8, substiochiometric a-SiO0.4N0.4, stoichiometric s-SiO2 substoichiometric a-SiO) to determine their electrical passivation properties. In general the sub-stoichiometric interlayers (ones with excess silicon compared to the O and N content) had superior electrical properties because they minimized Ge-O and Ge-N bond formation, had low internal bond strain, and minimized Ge dangling bond formation. The stack with oxygen deficient a-SiO interlayer demonstrated superior electric properties because it avoided all dangling bond formation. Experimental studies on HfO2/Si0.7Ge0.3(001) showed that MOSCAPs with low Dit correlated with formation of sub 0.5nm thick SiO interlayers with a low Ge content. The Dit can be as low as 6 x1011/cm2 in Al2O3/Si0.7Ge0.3 structures showing that nearly ideal interfaces can be formed on SiGe by avoiding Ge-O and Ge-N bond formation as well as Ge dangling bonds.
12:30 PM - *ED7.3.11
High Performance Ge and GeSn Epi Channels
C. W. Liu 1 2 , Fang-Liang Lu 1 , Yu-Shiang Huang 1 , I-Hsieh Wong 1
1 Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei Taiwan, 2 , National Nano Device Laboratories, Hsinchu Taiwan
Show AbstractGe and GeSn are attractive channel materials due to the superior mobility and compatibility with Si technologies. High performance Ge and GeSn epi channels grown by CVD are demonstrated in this work.
As the device size scales down, the S/D series resistance limits the drive current in 3D MOSFETs especially for Ge nFETs, which suffer severe Fermi level pinning and low active dopant concentration [1, 2]. In-situ CVD doping growth at low temperature (375oC) and selective laser annealing are used to increase the S/D doping concentration to reduce the S/D series resistance and to keep the channel doping concentration low in order to fully deplete the channel at off-state in Ge junctionless gate-all-around nFETs. From SIMS data and Van der Pauw measurement, P segregates to the surface and the Ge/Si interface during rapid thermal process at 550oC for 3 mins, which de-activates the electron concentration during this process. After the selective laser annealing, P in S/D region moves back into the Ge layer and re-activates. More than 1x1020 cm-3 active [P] is achieved after the selective laser annealing (the second laser annealing).
High-mobility strained GeSn on Ge buffer layers is also successfully grown on 200 mm Si by CVD. The mobility of CVD-grown GeSn channels with the low process temperature of 400oC significantly outperforms the Ge channels processed at the high temperature of 550oC. The mobility of best Ge cap/s-GeSn/Ge structure reaches ~430 cm2/V-s. For the GeSn device, low thermal budget is necessary to prevent the Sn loss during the process [3, 4]. Optimal Ge cap thickness, high quality GeSn channels, and low temperature gate stack process are the keys to obtain the high carrier mobility in GeSn channels.
The support of MOST of Taiwan (No. 103-2221-E-002 -253 -MY3, 103-2221-E-002 -232 -MY3, and 105-2622-8-002 -001 - ) and the AMAT are highly acknowledged.
Reference: [1] A. V.-Y. Thean et al., VLSI, pp. T26–T27, 2015. [2] T. Nishimura et al., Appl. Phys. Lett., 91, 123123, 2007. [3] H. Li et al., Appl. Phys. Lett., 102, 251907, 2013. [4] Wei Wang et al., Appl. Surf. Sci., 321, pp. 240-244, 2014.
ED7.4: Ferroelectrics
Session Chairs
Suman Datta
Alexander Demkov
Wednesday PM, April 19, 2017
PCC North, 100 Level, Room 131 A
2:30 PM - *ED7.4.01
Ferroelectric HfO2 or ZrO2 for Non-Volatile Memory Devices
Uwe Schroeder 1 , Tony Schenk 1 , Michael Hoffmann 1 , Claudia Richter 1 , Milan Pesic 1 , Franz Fengler 1 , Stefan Slesazeck 1 , Sergei Kalinin 5 , Alfred Kersch 3 , Jacob L. Jones 4 , James LeBeau 4 , Thomas Mikolajick 1 2
1 , Namlab, Dresden Germany, 5 , Oak Ridge National Laboratory, Oak Ridge, Tennessee, United States, 3 , UAS Munich, Munich Germany, 4 , North Carolina State University, Raleigh, North Carolina, United States, 2 , TU Dresden, Dresden Germany
Show AbstractWith the recent discovery of ferroelectric (FE) and field induced FE properties in doped HfO2 and ZrO2 the interest in FE based non-volatile memory devices is growing [1]. Continuous research is driven by the aim to understand the root cause and the determining parameters of this so far unknown behavior. Accordingly, the ferroelectric properties and crystal structure of these thin films processed under different conditions are investigated employing various physical as well as electrical characterization techniques. Piezo-response force microscopy (PFM) in conjunction with transmission electron microscopy (TEM) measurements revealed a domain size in the order of single grains with a grain diameter of ~20-30 nm for 10 nm thick films. Layers are only slightly textured, which caused a modulation of the polarization orientation within the layer. Electrical characterization of the defects and charges confirmed the influence of oxygen vacancies on the phase stability of the ferroelectric phase [2]. Based on this analysis, a qualitative model describing the influence of other basic parameters like stress, dopant concentration, and grain size on the crystal structure is proposed. With the understanding of the basic parameters to form the FE phase, the typical switching characteristics of HfO2 or ZrO2 based non-volatile memory devices can be explained.
Three different HfO2 or ZrO2 based memory concepts are described and compared: a ferroelectric doped HfO2 based FRAM, an anti-ferroelectric like ZrO2 based ‘non-volatile DRAM’, and a doped HfO2 based ferroelectric field effect transistor. Here, the field cycling behavior of HfO2 based FRAM capacitors is evaluated and compared to ZrO2 based ‘non-volatile DRAM’ structures [3]. ZrO2 based devices showed improved field cycling, endurance, fatigue, and imprint behavior. Already in 2012, a ferroelectric field effect transistor in 28 nm complementary metal-oxide-semiconductor (CMOS) technology was demonstrated [4] and recently the memory performance is verified in memory arrays up to a size of 19 kbit [5]. For single devices 10 year retention performance for up to 105 switching cycles is reached.
[1] T. S. Böscke et al., Appl. Phys. Lett. 99, 102903 (2011).
[2] M. Pešić et al., Adv. Funct. Mater. 26 (25), 4425 (2016)
[3] M. Pešić et al., International Electron Devices Meeting (IEDM), San Francisco, CA , December 2016
[4] J. Müller et al., Symposium on VLSI Technology (VLSI), June, 2012.
[5] M. Trentzsch et al.,International Electron Devices Meeting (IEDM), San Francisco, CA , December 2016
3:00 PM - ED7.4.02
Structural Study of Ferroelectric HfO2 in Metal-Insulator-Metal Stack—Lateral Grain Growth and Transition to Non-Centrosymmetric Phase
Takashi Ando 1 , John Bruley 1 , Xiao Sun 1 , Adam Pyzyna 1 , Martin Frank 1 , Vijay Narayanan 1
1 , IBM T.J. Watson Research Center, Ossining, New York, United States
Show AbstractFerroelectric HfO2 has been attracting much attention due to its scalability of physical thickness to below 10nm, which is not readily attainable with conventional ferroelectric materials. This opens up multiple new applications, such as FeFET memory or FeRAM embedded into the state-of-the-art CMOS device dimensions. We fabricated metal-insulator-metal (MIM) stacks with TiN electrodes and Al-doped HfO2 (8-20 nm) and investigated the structural changes that the HfO2 films undergo as the ferroelectric characteristics emerge from electrical measurements. The TiN electrodes were deposited by reactive sputtering and the Al-doped HfO2 was deposited by atomic layer deposition (ALD) using tetrakis(dimethylamino)hafnium (TDMAH), trimethylaluminum (TMA), and H2O precursors at 250 oC (Al to Hf cycle ratio: 1 to 15 and 20). Rapid thermal anneals (RTA) were performed at 850 and 1000 oC for crystallization of HfO2. The P-E hysteresis loops were obtained from 40x40um2 capacitors and the corresponding microstructures were studied using a high resolution scanning transmission electron microscope (HR-STEM). A position averaged convergent beam electron diffraction (PACBED) was used to investigate centrosymmetry of the local structure as originally reported for Gd doped HfO2 [1]. We observed a significant lateral growth of singly oriented grains after annealed at 850 and 1000oC, exceeding the range of STEM scan (> 100nm), for the Al-doped HfO2 samples exhibiting ferroelectric electric behaviors. On the other hand, an undoped HfO2 sample annealed at 1000oC did not show such lateral grain growth and it remained paraelectric. For the Al-doped HfO2 sample, the PACBED along the [111] orientation showed loss of 6-fold symmetry [2], which is a direct evidence of formation of non-centrosymmetric HfO2 phase. Roles of Al dopants and TiN electrodes in these structural changes will be discussed.
[1] X. Sang et al., APL 106, 162905 (2015)
[2] J. Bruley et al., to be published.
3:15 PM - ED7.4.03
Ferroelectric Capacitors with Quasi-Amorphous BaTiO3 Integrated on Silicon
Lucie Mazet 1 , Martin Frank 2 , Sylvie Schamm-Chardon 3 , Eduard Cartier 2 , Hiroyuki Miyazoe 2 , John Bruley 2 , Sang Mo Yang 4 , Sergei Kalinin 4 , Vijay Narayanan 2 , Catherine Dubourdieu 1 5
1 , Institut des Nanotechnologies de Lyon, Ecully France, 2 , IBM T.J. Watson Research Center, Yorktown Heights, New York, United States, 3 , CEMES-CNRS, Université de Toulouse, Toulouse France, 4 , Oak Ridge National Laboratory, CNMS, Oak Ridge, Tennessee, United States, 5 , Helmholtz Zentrum Berlin für Materialien und Energie, Berlin Germany
Show AbstractFerroelectric epitaxial films on silicon have attracted particular attention in the past years for their integration into negative capacitance ferroelectric field-effect devices with potentially steep sub-threshold slope. However, one major issue is that the high crystalline quality of the epitaxial oxide is associated with a large effective dielectric permittivity that is not suitable to counterbalance the low permittivity SiO2 interfacial layer.
Here, we show that ferroelectricity is obtained in "quasi-amorphous" BaTiO3 films (thickness ∼10nm) on an amorphous SrTiO3 (1.6 nm) buffer on p-type-silicon pre-patterned capacitive structures. The films were grown by molecular beam epitaxy. A TiN electrode was sputtered on top of the heterostructures and the metal-oxide-semiconductor capacitors were characterized by capacitance-voltage (C-V) measurements performed at various frequencies (0.1-100 kHz), voltage sweep rates (0.007V/s - 0.35V/s), and temperatures (25°C to 130°C). Both perovskite oxides were found to be X-ray amorphous. TEM investigations reveal an amorphous stack with the presence of nanocrystallites in the BaTiO3 film. A clockwise C-V hysteresis loop was observed, consistent with ferroelectricity, while a conventional dielectric on p-Si would exhibit an anti-clockwise hysteresis typical for charge trapping. The memory window is nearly independent of voltage sweep rate, excluding ion movement as a cause of clockwise hysteresis. Finally, the C-V versus temperature measurements clearly indicated the suppression of the hysteresis loop at a temperature of 105°C, near the bulk BaTiO3 Curie temperature of 120°C, and a fully reversible transition. Piezoresponse force microscopy was performed in the capacitor trenches directly on the oxide heterostructure (without a top TiN electrode) and evidenced also a ferroelectric response while the measurement performed on the stack deposited on the isolation oxide did not show any hysteretic electromechanical response. This result indicated that ferroelectricity did not arise from a phenomenon related to the top electrode deposition (strain, thermal effect...) but is established in the oxide film before gate encapsulation. Possible origins for the ferroelectric behavior will be discussed.
These results are promising since such BaTiO3 material exhibits advantageous properties of an amorphous dielectric of medium relative permittivity (∼24) with a low leakage current density (∼10-7 A/cm2 at -1V) while being ferroelectric with a phase transition (105°C) occurring above typical CMOS logic operation temperatures. This material may therefore be particularly suitable for negative capacitance field-effect devices and other nanoelectronic applications.
4:30 PM - *ED7.4.04
Ferroelectricity in Hf-Based Oxide—Negative Capacitance FETs for Steep Subthreshold Swing
Min-Hung Lee 1 , P.G. Chen 1 2 , S.T. Fan 2 , C.Y. Kuo 1 , C.-H. Tang 1 , H.H. Chen 1 , C. W. Liu 2
1 , National Taiwan Normal University, Taipei Taiwan, 2 , National Taiwan University, Taipei Taiwan
Show AbstractThe integrating ferroelectric gate stack into FETs with negative capacitance effect for subthreshold swing (SS) improvement has attracted lots of attention due to hafnium (Hf)-based oxide with ferroelectricity. The HfO2 with suitable dopants and annealing for ferroelectric (FE) transition would be studied, and demonstrated NC effect for steep-slope FET (SS-FET) and memory applications. The compatible CMOS process and scaling film thickness are the advantages to integrate into semiconductor industry by comparison with perovskite material. The capacitance of the semiconductor and ferroelectric film is matched to obtain the hysteresis-free. The feasible concept of coupling the polarization Hf-based oxide was applied, the proposed promising technology with the opportunity to be the candidate for low-power electronics, such as wearable devices, bioelectronics, and IoT (internet of things) applications.
5:00 PM - *ED7.4.05
Recent Advances in Negative Capacitance for Ultra-Low Power Computing
Asif Khan 1
1 , Georgia Institute Technology, Atlanta, Georgia, United States
Show AbstractNegative capacitance-an unusual physical phenomenon, where the stored charge decreases with an increasing voltage-can find interesting applications in electronics. For example, when used as the gate oxide in the MOSFET, a negative capacitance material can reduce the subthreshold swing below the fundamental physical limit of 60 mV/decades [1]. This device technology can, in turn, significantly lower the energy dissipation in CMOS circuits by enabling new pathways for arbitrarily reducing the power supply voltage. I will give an overview of the exciting developments in the field of negative capacitance over the past eight years starting from the theoretical prediction in 2008 to the clean experimental demonstration of this phenomenon in ferroelectric oxides recently [2,3]. I will also discuss our recent experimental work on negative capacitance transistors [4] and energy and performance projections of circuits based on negative capacitance MOSFETs [5,6].
References:
[1] Salahuddin et al. "Use of negative capacitance to provide voltage amplification for low power nanoscale devices." Nano Letters 8, 405 (2008).
[2] Khan et al. “Negative capacitance in a ferroelectric capacitor.” Nature Mater. 14, 182 (2015).
[3] Khan et al. “Experimental evidence of ferroelectric negative capacitance in nanoscale heterostructures.” Appl. Phys. Lett. 99, 113501 (2011).
[4] Khan et al. “Negative capacitance in short-channel FinFETs externally connected to an epitaxial ferroelectric capacitor.” IEEE Electron Dev. Lett. 367, 111 (2016).
[5] Khan et al. “Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation.” Proc. IEEE Electron Devices Meeting (IEDM), pp. 11-3 (2015).
[6] Khandelwal, S., et al. "Circuit performance analysis of negative capacitance finfets." Proc. IEEE Symp. VLSI Technology (2016).
5:30 PM - ED7.4.06
Flexible Ferroelectric Hafnia Films and Devices
Hyeonggeun Yu 1 , Ching-Chang Chung 1 , Jacob L. Jones 1 , Franky So 1
1 , North Carolina State University, Gainesville, Florida, United States
Show AbstractOxide ferroelectrics have been under fervent research for non-volatile memory applications. Compared to conventional lead zirconate titanate (PZT), hafnia–based ferroelectrics exhibit large polarization densities at few nanometer film thickness. However, demonstrations of flexible memory devices based on these materials were challenging due to the high crystallization temperatures. By employing a non-rapid thermal annealing process, here we report a direct growth of hafnia-based ferroelectric films on a flexible substrate with a remnant polarization of 10 μC/cm2. The ferroelectricity was retained at a bending radius down to 5 mm and a repetitive bending cycles up to 1,000. Finally, a non-volatile memory is demonstrated on a flexible substrate using vertical field-effect transistor configuration.
5:45 PM - ED7.4.07
Rapid Imaging of Polarization Switching in Ferroelectrics Using the Complete Information Stream from Scanning Probe Microscopes
Suhas Somnath 1 , Sergei Kalinin 1 , Stephen Jesse 1
1 , Oak Ridge National Laboratory, Oak Ridge, Tennessee, United States
Show AbstractPolarization switching in ferroelectric and multiferroic materials forms the basis for the next generation of electronic devices such as field effect transistors, race-track memories, and tunneling devices. The switching mechanisms in these materials are very sensitive to the micro- and nanometer scale local defects and structural imperfections which have undesirable effects on ferroelectric domains. These considerations led to the development of Piezoresponse Force Microscopy (PFM) for imaging and manipulating local polarization states. In PFM, a micro-cantilever with a conductive tip is brought into contact with the sample surface. Bias applied to the tip deforms the sample, which in turn causes the cantilever to deflect or vibration, and these vibrations are recorded using an optical setup in the microscope. The current state-of-art PFM imaging techniques measure the bias dependent material deformation either at a single frequency (using a lock-in-amplifier) or over a narrow band of frequencies thereby discarding valuable information from higher vibrational modes of the cantilever and multiple harmonics. Similarly, PFM spectroscopy techniques suffer from serious compromises in the measurement rate, voltage and spatial resolutions since they require the combination of a slow (~ 1 sec) switching signal and a fast (~ 1 – 10 msec) measurement signal. The slow speed results in undesirable compromises between the imaged area, spatial resolution, and voltage resolution.
We report on a new PFM spectroscopy technique that rapidly acquires dense 2D maps of material response. This technique combines the acquisition of the complete information about the cantilever response with intelligent signal filtering techniques to enable direct measurement of material strain in response to the probing bias. Our technique enables precise spectroscopic imaging of the polarization switching phenomena 3,500 times faster than currently reported methods. The probing bias waveform can be modulated such that the material response can be measured for all combinations of electric field which allows rapid construction of Preisach density maps as well. By rapid acquisition of a large number of hysteretic loops on very dense grids, this technique will enable significant insight into nanoscale polarization dynamics and phenomena such as polarization fatigue or local wall displacements that remain difficult to study at the desired spatial and temporal scales, and are crucial for integration of ferroelectric nanostructures in future electronic devices.
This research was conducted at the Center for Nanophase Materials Sciences, which is sponsored at Oak Ridge National Laboratory by the Scientific User Facilities Division, Office of Basic Energy Sciences, U.S. Department of Energy.
ED7.5: Poster Session
Session Chairs
Andrew Kummel
John Robertson
Thursday AM, April 20, 2017
Sheraton, Third Level, Phoenix Ballroom
9:00 PM - ED7.5.01
Hydrogen Silsesquioxane (HSQ) Resistance Switching Nanopillar Arrays
Wing Ng 1 , Mark Buckwell 1 , Adnan Mehonic 1 , Anthony Kenyon 1
1 , University College London, London United Kingdom
Show AbstractResistance switching memories (RRAM) have attracted a lot of attention in recent years due to fast switching times, and low switching voltages. These qualities make RRAM a promising candidate for the next generation of memory. The ever-increasing demand for memory storage and capacity motivate the ever-decreasing dimensions of individual memory elements.
In this paper, we present our recent work on resistance switching in a multilayer nanopillar array with hydrogen silsesquioxane (HSQ) as an active switching layer. We demonstrate this material has SiO2-like properties upon crosslinking and is capable of intrinsic switching in ambient conditions. We also demonstrate that this material can be applied on metallic and semiconductor surfaces by spin coating. This makes the fabrication process much simpler compared to most active resistance switching materials (e.g. HfO2, TiO2, TaOx etc), which require sputtering in high vacuum conditions or precision control in atomic layer deposition. The HSQ nanopillar array was fabricated using a fast electron beam lithography technique with throughput on the order of 106 μm2/hr. The diameter of the individual nanopillar can be scaled down to less than 50 nm.
We demonstrate that the HSQ thin film can achieve bipolar switching, multiple switching states cycling with voltage pulses, and over 105 seconds retention of the low resistance state (LRS) and high resistance state (HRS).
The electrical characteristics of individual nanopillars were probed using conductive atomic force microscopy (CAFM), which enabled us to address individual nanopillars. These observations make HSQ a promising candidate as an active switching material for the next generation of RRAM.
9:00 PM - ED7.5.02
Investigation of Ferroelectric Behavior in Doped Hafnium Oxide
Irving Cashwell 1 , Aswini Pradhan 1 , Bo Xiao 1
1 , Norfolk State University, Norfolk, Virginia, United States
Show AbstractStudies of Ferroelectric properties of the high-k dielectric material Hafnium Oxide (HfO2) are very important for CMOS memory applications. In this research, we have performed the electrical and structural properties of has been investigated. The HfO2 films were deposited on Si by the electron beam evaporation technique at room temperature using HfO2 pellets. The cryllographic peak associated with HfO2 monoclinic and triclinic phases are enhanced on annealing at 800C temperature. XPS results show phase stoichiometry and expected doping level. The polarization-electric (PE) field curves of HfO2 films were measured by Radiant ferroelectric loop tracer. We have demonstrated that the HfO2 films show pronounced PE hysteresis ferroelectric behavior and is enhanced through doping and as well as increasing crystalline quality of the films via annealing processes. On further optimization, the ferroelectric properties were enhanced. We will compare our results with atomic layer deposited HfO2 films on Si. The detailed results will be presented.
9:00 PM - ED7.5.03
Dependences of Memory Characteristics on Schottky Parameters in Pt/Nb:SrTiO3 Schottky Junction Type Resistive Memory
Kentaro Kinoshita 1 2 , Shiomi Toshiki 1 , Yuuto Hagihara 1 , Satoru Kishida 1 2
1 , Tottori University, Tottori Japan, 2 , Tottori Integrated Frontier Research Center, Tottori, Tottori, Japan
Show AbstractResistive switching (RS) caused by the voltage induced modulation of Schottky barrier attracts attention thanks to its high performance [1]. Therefore the elucidation of the mechanism of the barrier modulation should be elucidated urgently. In this study, we extracted Schottky barrier parameters of Pt/Nb doped SrTiO3 (Nb:STO) structures by performing both current-voltage (I-V) and capacitance-voltage (C-V) measurements. Pt and Ti electrodes were deposited on the surface of a single crystalline Nb:STO (Nb 0.5 wt%) substrate with (100) orientation for the formation of Schottky and Ohmic contacts, respectively. A barrier height ΦB and ideality factor n were extracted by fitting I-V data to the formula of I = SA*T2exp(-qΦB/kT)(exp{qV/nkT}-1) [3], where S is an electrode area, A* is Richardson constant [2], T is temperature, q is elementary charge, and k is Boltzmann constant. As a result, ΦB*n was kept constant for Vset < 2.0 V and Vreset > -4.0 V and ΦB became larger for higher resistance, where Vset and Vreset are set and reset voltages, respectively. It was reported that n increased with decreasing temperature while ΦB*n was kept constant [4]. Therefore, the RS without changing ΦB*n is suggested to be caused by electron trapping at the Pt/Nb:STO interface. We also investigated the dependence of retention characteristics of resistance in low resistance state (RL) on the number of write/erase cycles until which the current resistance value was written. The increasing rate (IR) of the RL became smaller with increasing the number of write/erase cycles. Similar phenomenon was reported in PbZrTi and the origin was explained by formation of atomic vacancies [5]. Accordingly, the phenomenon that we observed can also be caused by the formation of atomic vacancies during the repetition of switching cycles.
References:
[1]Sim et al., Tech. Dig. IEDM 2005, p. 758,
[2]Shimizu et al., J. Appl. Phys. 85, 7244 (1999),
[3]Cheung et al., Appl. Phys. Lett.49, 85(1986),
[4]Yamamoto et al.,Jpn J. Appl. Phys. 37(1998)4737-4746,
[5]Bourim et al., Sensors and Actuators A 155 (2009) 290–298.
9:00 PM - ED7.5.04
Beyond the Nanoparticle—Memory Devices Using Near Atomic Structures
Febin Paul 1 , Shashi Paul 1
1 , De Montfort University, Leicester United Kingdom
Show AbstractThe rise of the flash memory technology has completely revolutionised modern electronics by radically increasing the storage capacity per unit area [1]. Not very long ago people used to boast of their Commodore 64s that had a 64 kb RAM. But in the shadow of the magnificent success we have gained all that seems to be a chapter from the ancient history. The ITRS roadmap last year dubbed the memory technologies to be the ‘driving force’ of Moore’s law [2]. With the rise of better performing devices, the horizontal device area has been shrinking at a consistent pace. But the shrinking hasn’t been without flaws. Many problems like the leakage of the charges due to insulator layer defects still affect the device performance and charge retention [3].
This work explains the working of a memory device using a thin film consisting of particles of conducting and/or semiconducting materials in the quantum realm. Such nano-bits exhibit exotic properties which are greatly desirable for memory application. A thin film of such an active material acts as a quantum traps for charges. It is these traps that we employ to store information. Many quantum phenomena like the quantum confinement is experienced in a significant manner in such quantum scales. Due to this, the scale and size of the material being used in the fabrication of the device remain consistent with the small device area without compromising on the performance. Moreover, the fabrication process is also designed to be easily scalable and can result in a 3D architecture for memory devices.
Current-Voltage (I-V), data retention time (Current-Time), write-read-erase-read (W-R-E-R) measurements were conducted using HP 4140B pico-ammeter and Capacitance-Voltage (C-V) measurements of memory devices were conducted using an LCR bridge HP 4192A. All the electrical measurements were conducted in an electromagnetic shielded dark box.
REFERENCE:
[1] Galatsis, K. et al. "Emerging Memory Devices". IEEE Circuits and Devices Magazine 22.3 (2006): 12-21.
[2] International Technology Roadmap for Semiconductors 2.0, 2015 ed. Executive Report: 2015.
[3] Prime, D., S. Paul, and P. W. Josephs-Franks. "Gold Nanoparticle Charge Trapping And Relation To Organic Polymer Memory Devices". Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 367.1905 (2009): 4215-4225.
9:00 PM - ED7.5.05
Analog Memcapacitance in Pt/HfOx/n-IGZO Structure through Redistribution of Oxygen
Paul Yang 1 , Hyung Jun Kim 1 , Hong Zheng 1 , Jong-Sung Park 1 , Chi Jung Kang 1 , Tae-Sik Yoon 1
1 , Myongji University, Yongin, Gyeonggi-do Korea (the Republic of)
Show AbstractThe memcapacitance, i.e. a memorized capacitance change induced by either microscopic geometric changes or history-dependent permittivity changes, was investigated in a MOS structure of Pt/HfOx/n-IGZO. In this study, the Pt/HfOx/n-IGZO structure exhibited analog, polarity-dependent, and reversible memcapacitance through the redistribution of oxygen ions between HfOx and IGZO. When a positive voltage was applied to the Pt electrode, an accumulation capacitance increased gradually owing to the migration of oxygen ions from IGZO to HfOx, which increased the permittivity of HfOx layer. Consequently, the depletion capacitance increased owing to the increased oxygen vacancy concentration in the IGZO layer. The capacitances could be restored by applying a negative potential to repel oxygen ions from HfOx back to IGZO. The exchange of oxygen ions between HfOx and IGZO, which were confirmed by Auger electron spectroscopy analysis, led to the strong and reversible change of the permittivity of HfOx layer and the doping concentration of IGZO layer. The analog increase and decrease of capacitance emulated the synaptic potential and depression behavior, respectively. The reversible memcapacitance and subsequent change of the doping concentration of the semiconductor could potentially be used in the gate stack of transistor to modulate electrical properties for digital and analog memory, reconfigurable logic devices, and artificial synapse device.
Acknowledgments
This work was supported by Samsung Research Funding Center of Samsung Electronics under Project number SRFC-MA1502-03.
9:00 PM - ED7.5.06
Strain-Induced Shift of the Electrical Properties in AlGaN/GaN Heterostructures
Wulin Tong 1 , Wu Tang 1
1 , University of Electronic Science and Technology of China, Chengdu China
Show AbstractThe effect of strains in AlGaN barrier layer on the electrical properties in AlGaN/GaN heterostructures was investigated by Sentaurus TCAD simulations. The strain adjustment is achieved through adjusting lattice constant (a0) and strain relaxation. The threshold voltage and saturated drain current are proportional to the strain values, which is beneficial to regulate the electrical properties in AlGaN/GaN heterostructures. When added the local step-strain in AlGaN layer near the gate edge, the low concentration region is formed due to the decrease of the 2DEG concentration. As a result, the surface electric field becomes more uniform and the breakdown voltage is enhanced, while the effect on the threshold voltage and saturated drain current is little.
9:00 PM - ED7.5.07
Directly Observation of the Switching Behaviors in VCM-Based Ta2O5 Memristor
Jui-Yuan Chen 1 , Chun-Wei Huang 1 , Wen-Wei Wu 1
1 Materials Science and Engineering, National Chiao Tung University, HsinChu Taiwan
Show AbstractResistive random access memory (RRAM) is considered to be the promising candidate for next generation nonvolatile memories due to its outstanding performance and convenient fabrication process. However, the origin of the switching mechanism is still controversial, especially in VCM (valence change mechanism). In the work, we use TEM to observe the switching behavior in Au/Ta2O5/Au system. The shape and size of the conducting filament were obtained, and the composition of the filament was identified by electron energy loss spectroscopy (EELS) and energy dispersive spectroscopy (EDS). The switching effects affected by the evolution of conducting filament in Ta2O5−x layer, which consist of nanoscale TaO2−x filaments. The knowledge of filament would provide a foundation for clarifying VCM, which benefit improving the stability and scalability in oxide metal for commercial applications.
9:00 PM - ED7.5.08
Effect of Displacement Damage on Tantalum Oxide Resistive Memory Devices
Joshua Holt 1 , Karsten Beckmann 1 , Zahiruddin Alamgir 1 , Jean Yang-Scharlotta 2 , Nathaniel Cady 1
1 , State University of New York Polytechnic Institute, Albany, New York, United States, 2 , Jet Propulsion Laboratory, Pasadena, California, United States
Show AbstractRadiation effects are a primary concern for electronic devices in aerospace or nuclear environments. Electronics developed for these applications must be designed for radiation tolerance. However, existing rad-hard design approaches cannot fully protect devices from radiation effects. For aerospace applications, the implementation of damage mitigation strategies is further limited by mass and power limitations. Resistive memory (RRAM) is an emerging memory technology that has strong potential as a rad-hard memory element, as well as considerable potential as an alternative memory technology. While transistors rely on the tight control of charge within the channel, RRAM depends on the movement of much larger ions through an insulator. Switching occurs based on the formation and partial destruction of a conductive filament of oxygen vacancies within an insulating oxide. Since the filament is composed of oxygen vacancies, a sudden increase in electrons and holes due to radiation is very unlikely to affect the filament. High linear energy transfer (LET) ionic radiation can affect the filament through displacement damage, generating oxygen vacancies and oxygen interstitials within an oxide. Changes in TaOx-based device behavior due to radiation have been observed at 1019 radiation-generated oxygen vacancies per cm3, as calculated by Stopping Range of Ions in Matter (SRIM).
We present a study of radiation damage in tantalum oxide-based RRAM, with the goal of understanding RRAM switching behavior and radiation damage mechanisms in the devices. In a previous study, devices were exposed to gamma radiation (60Co source, 64.7 Mrad(Si)) and several types of ionic radiation (H, N, Ar+; 1MeV, 1015 ions/cm2). These experiments resulted in no significant changes in RRAM switching parameters. The devices used for this study were based on an improved photolithography device fabrication process, resulting in higher device yield, uniformity, and retention. Radiation experiments were carried out at the University at Albany, using Ar+ ions tuned to maximize displacement damage, calculated using SRIM. The combination of improved device uniformity and a focus on displacement damage make this study a significant contribution toward understanding the radiation response of these devices.
9:00 PM - ED7.5.09
Resistive Memory Structures of Nano-Layered Al2O3
Sita Dugu 1 , Shojan Pavunny 1 , Ram Katiyar 1
1 , University of Puerto Rico, San Juan, Puerto Rico, United States
Show AbstractNon-volatile memory technology scaling has been driven by the ever increasing needs for high-capacity and low-cost data storage. Resistive switching behavior of several materials has recently attracted considerable attention for non-volatile memory device applications due to their high endurance, sub-nanosecond switching, long retention, scalability, low power consumption, high ON/OFF ratio and CMOS compatibility. Among various dielectric materials studied, Al2O3 has several promising features as a resistive switching material in addition to its wide band gap (~7 eV), large dielectric strength (~5 MV/cm), high permittivity (~8), and good thermal stability. With this motivation, we studied the resistive switching characteristics of ITO/Al2O3/Pt hetero-structures for resistive memory applications. Amorphous Al2O3 thin films of ~15 nm thickness was deposited by remote-plasma enhanced ALD in a self-limiting vapor-phase chemisorption window on ITO coated glass substrates kept at a temperature of 200 oC using trimethyl-aluminum precursor and oxygen plasma. Platinum metal top electrodes were deposited by DC sputtering at room temperature through square metal shadow mask. The above non-volatile memory structures exhibited a typical bipolar, reliable, and reproducible resistive switching behavior, with ON/OFF resistance ratio of ~104, narrow spread of set and reset voltages, better switching endurance ~102 cycles, and longer data retention (>103 s) in a wide temperature range of 200–400 K. The possible resistance switching and current conduction mechanisms in these potential transparent trilayer memory devices will be presented.
9:00 PM - ED7.5.10
Switching Characteristic Improvement of TaOx-Based ReRAM Stack by Magnetron Sputtering Method
Yusuke Miyaguchi 1 , Shunpei Ota 1 , Kazushi Fuse 1 , Hyung-Woo Ahn 1 , Shun Manita 1 , Takehito Jimbo 1
1 , Institute of Semiconductor and Electronics Technologies, ULVAC, Inc., Susono Japan
Show AbstractCurrently next generation memory undergo intense study for embedded, Storage Class Memory(SCM), replacement of NAND Flash memory application and so on. Resistive Random Access Memory (ReRAM) have attracted great attention and is one of the prime candidates for next generation memory, because it shows low power and high speed operation and is good in terms of process integration and cost in comparison with other nonvolatile memories. Ta2O5/TaOx bi-layer thin films for ReRAM cell were prepared by magnetron sputtering method because of having several advantages such as lower cost and structural stability for mass-production [1]. In this study, we evaluated switching characteristics of ReRAM cell using Ta2O5/TaOx bi-layer film with electrode such as TiN that is materials with high affinity to an existing semiconductor manufacturing process and line are even required for ReRAM manufacturing. Electrode films were also prepared by magnetron sputtering method same as Ta2O5/TaOx bi-layer film. We employed a multi chamber type mass production tool as sputtering system for substrate with 300 mm in diameter. Switching characteristic with good property of ReRAM cell was obtained by fine tuning of electrode sputtering process.
Reference
[1] Natsuki Fukuda et al, Mater. Res. Soc. Symp. Proc. Vol. 1430-e03-16, 2012 Materials Research Society
9:00 PM - ED7.5.11
Taguchi Design of Experiment Enabling the Reduction of Spikes on the Sides of Patterned Thin Films for Tunnel Junction Fabrication
Pawan Tyagi 1 , Beachrhell Jacques 1 , Edward Friebe 1 , Tobias Goulet 1 , Stanley Travers 1
1 , University of the District of Columbia, Washington, District of Columbia, United States
Show AbstractThin film deposition after photolithography often produces unwanted spikes along the side edges of a sputtered target material after chemically etching away the background. These spikes are a significant issue for the development of magnetic tunnel junction based memory and molecular spintronics devices, microelectronics, and micro-electro- mechanical systems because they influence the properties of the other films deposited on the top. This is why tapered thin film edges are critically needed in devices. Here, we report a very cost efficient and fast way of creating an optimum photoresist profile for the production of ‘spike-free’ patterned films. This approach is based on performing a soaking in the photoresist developer after baking and before the UV exposure. However, the success of this method depends on multiple factors accounted for during photolithography - photoresist thickness (spin speed), baking temperature, soaking time and exposure time. Our recent experiments systematically studied the effect of these factors by following the L9 experimental scheme of the Taguchi Design of experiment (TDOE). The L9 experimental scheme effectively accommodated the study of four photolithography factors, each with three levels. After performing photolithography as per L9 TDOE, we conducted sputtering thin film deposition of 20 nm Tantalum. Then we conducted an atomic force microscope (AFM) study of thin film patterns and measured the spikes along the edges of the deposited tantalum. We utilized spike height as the desired property and chose “smaller the better” criteria for TDOE analysis. TDOE enabled us to understand the relative importance of the parameters, relationship amongst the parameters, and impact of the various levels of the parameters on the edge profile of the thin film patterns. We discovered that baking temperature was the most influential parameter; presoak time and photoresist thickness were two other influential factors; exposure time was the least effective factor. We also found that 4000 rpm, 100 C soft baking, 60 s soaking and 15 s UV exposure yielded the best results. Finally, the paper also discusses the interdependence of selected factors, and impact of the individual levels of each factor. This study is expected to benefit MEMS and micro/nanoelectronics device researchers because it attempts at finding a cheaper and faster alternative to creating an optimum photoresist profile.
9:00 PM - ED7.5.12
Polarity Dependent Resistive Switching Characteristics in Ta2O5/Ag2Se and Ag2Se/Ta2O5 Bilayer Structures
Lee Tae Sung 1
1 , Myoung Ji University, Yong in city Korea (the Republic of)
Show AbstractThe resistive random access memory(RRAM) devices with heterostructure have been investigated due to cycling stability, non-linear switching, complementary resistive switching and self-compliance. The heterostructured devices can modulate each layer and interface on the switching properties. Ta2O5 and Ag2Se acted as the switching materials, which are transition-metal oxide(TMO) and chalcogenides, respectively. It was reported that switching mechanism in Ta2O5 was ascribed to oxygen vacancy and switching mechanism in Ag2Se was caused by Ag filament. In this study, the bipolar resistive switching characteristics in the bilayer structures of Ta2O5/Ag2Se and Ag2Se/Ta2O5 were investigated. All voltages were applied on Ag top electrode as bottom Pt electrode grounded. In our previous research, it showed that Ag/Ag2Se/Pt device and Ag/Ta2O5/Pt device had bipolar resistive switching characteristics with set process at negative voltage and at positive voltage, respectively. The Ta2O5/Ag2Se device showed a negative set process and a positive reset process. The Ag2Se/Ta2O5 device, however, showed a positive set and a negative reset process. Therefore, the polarity of resistive switching was attributed to the stacking sequence of Ta2O5 and Ag2Se. Since the combination of two heterostructured devices show the threshold switching characteristics, sneak path leakage can be reduced without using additional selectors. In addition, the heterostructure has advantages such as self-compliance, reproducible and stable resistive switching without electroforming. It conforms the possible applications of TMO and chalcogenide heterostructures in RRAM.
9:00 PM - ED7.5.13
Oxygen Vacancy Electromigration versus Joule Heating in Local Programming of TiO2 RRAM Conductivity
Kechao Tang 1 , Andrew Meng 1 , Fei Hui 2 , Yuanyuan Shi 2 , Trevor Petach 1 , David Goldhaber-Gordon 1 , Mario Lanza 2 , Paul McIntyre 1
1 , Stanford University, Stanford, California, United States, 2 , Soochow University, Suzhou China
Show AbstractResistive random access memory (RRAM) made of transition metal oxides sandwiched by two metallic electrodes has received great attention recently, due to the possibility of switching between high resistance states and low resistance states.1 The formation and breaking of conductive filaments (CFs) in oxide layer is generally considered responsible for the switching of the RRAM device.2 Nevertheless, the mechanism of the CF formation is still not yet well understood, especially considering the role of Joule heating in conductivity switching. In this report, for the first time, we replaced a top metal electrode by an ionic liquid (IL) gate to study conductivity switching and CF formation in TiO2. Because IL’s can be readily rinsed off from the programmed oxide surface, this configuration saves the trouble of removing the top metal electrode, which can greatly complicate subsequent characterization of the CF after formation. In addition, current flow is significantly limited due to the high resistivity of the IL, enabling testing that will discriminate the effects of local electromigration of defects in the oxide from those of local Joule heating.
We investigate the effects of IL gating on atomic layer deposited (ALD) TiO2 thin films (~15 nm). The local conductivity of the ALD-TiO2 layer can be switched on and off by applying positive and reverse bias on the IL, respectively, at very low biasing current (< 10 nA). Conductive AFM (C-AFM) imaging shows a number of conductive regions of lateral dimension varying from ~10 nm to ~100 nm formed by IL gating, as well as a consistent set and reset behavior. Secondary ion mass spectroscopy (SIMS) combined with 18O isotope labelling are in support of the oxygen vacancy creation and annihilation as the mechanism for local TiO2 conductivity changes. This oxygen-mediated conductivity switching is further confirmed by plan-view scanning transmission electron microscopy (STEM) combined with electron energy loss spectroscopy (EELS) signal mapping, showing chemically reduced Ti bonding states in nanoscale size clusters exclusively in the TiO2 layer switched on by IL gating. Despite the generation of oxygen vacancies, IL gating produces no strong and highly-localized CFs in TiO2. The absence of CFs is attributed to the lack of Joule heating during IL gating, supported in a follow-up experiment in which the IL is replace by a potassium nitrite (KNO3) solution (200 g/L), a far more conductive electrolyte. With KNO3 gating, a single dominant CF is created, indicated by the independence of on-state current with device area and directly characterized by C-AFM. This study shows clear evidence of electric field induced creation and electro-migration of oxygen vacancies in TiO2 conductivity switching, but the necessity of sufficient Joule heating to create a nanoscale CF.
1. J. J. Yang et al., Nature Nanotechnology, 3, 429 (2008). 2. D-H. Kwon et al., Nature Nanotechnology, 5, 148 (2010).
9:00 PM - ED7.5.14
Multi-Level Organolead Halide Perovskite Resistive Random Access Memories
Feichi Zhou 1 , Yang Chai 1
1 , HK Polytechnic Universtiy, Hong Kong Hong Kong
Show AbstractMulti-Level Organolead Halide Perovskite Resistive Random Access Memories
Feichi ZHOU1, Yang Chai1
1. Department of Applied Physics, The Hong Kong Polytechnic University, Hung Hom, Hong Kong.
Resistive random access memory (RRAM) has emerged as a next-generation non-volatile memory devices due to their scalability, high switching speed, and low power consumption. RRAM can store and process information based on their switchable resistances. Recently, organic-inorganic hybrid perovskites have been intensively investigated in applications of solar cells with high power conversion efficiency for their excellent light absorption, long electron-hole diffusion length, ambipolar charge transport, unusual defect physics, tunable band gap and dielectric polarization properties. 1, 2A hysteresis usually exists in the perovskite device, possibly caused by the formation and movement of traps states and ion migration in the perovskites.3 This characteristic in the perovskite device enables us to design a memory device.
Perovskite based memory devices were fabricated in a configuration of Au/CH3NH3PbI3−xClx hybrid perovskite/fluorine-doped tin oxide (FTO). The continuous and well-crystalized CH3NH3PbI3−xClx perovskite films were prepared by solution processing at low temperature on FTO substrates. The devices exhibit typical bipolar resistive switching behavior and non-volatile memory characteristics with low operating voltage, good endurance and data retention. Specifically, the device can be set from high-resistance state (HRS) to the low-resistance state (LRS) at a low SET voltage of 0.45 V with an on/off ratio of 3200. The reset process occurs at -0.43 V, which is the lowest operation voltage and largest on/off ratio of the hybrid perovskite memories reported till now. The HRS and LRS nearly remain unchanged after 104 s. Multi-level resistances can also be achieved by applying different compliance currents. The resistance switching mechanism can be explained by trap-controlled space-charge-limited conduction mechanism.
1. Gu, C, Lee, J.-S., Flexible Hybrid Organic–Inorganic Perovskite Memory. ACS nano 2016, 10 (5), 5413-5418.
2. Xu, W. Cho, H, Kim, Y. H.; Kim, Y. T, Wolf, C,Park, C. G, Lee, T. W., Organometal Halide Perovskite Artificial Synapses. Advanced Materials 2016.
3. Xiao, Z, Huang, J, Energy Efficient Hybrid Perovskite Memristors and Synaptic Devices. Advanced Electronic Materials 2016.
9:00 PM - ED7.5.16
Subsurface Engineering of Silicon for 3D Devices
Onur Tokel 1 , Ahmet Turnali 1 , Ghaith Makey 1 , Parviz Elahi 1 , Serim Ilday 1 , Tahir Colakoglu 2 , Ozgun Yavuz 1 , R. Huebner 3 , Mona Zolfaghari 2 , Ihor Pavlov 1 , Alpan Bek 2 , Rasit Turan 2 , Omer Ilday 1
1 , Bilkent University, Ankara Turkey, 2 , Middle East Technical University, Ankara Turkey, 3 Helmholtz-Zentrum Dresden - Rossendorf, Institute of Ion Beam Physics and Materials Research, Dresden Germany
Show AbstractRecently we have demonstrated a new 3D-laser-fabrication method which enabled, for the first time, creating highly-controlled subsurface structural modifications (structural imperfections, or defects) buried deep inside Silicon (Si) wafers [1]. Characterizing the material properties of these subsurface Si structures are very critical towards enabling new optical and micro-mechanical applications inside chips [2,3]. Here, we present optical, chemical and microscopic analysis of these buried structures. Specifically, Transmission Electron Microscopy (TEM) studies, Optical Birefringence Analysis and Selective Chemical Etching analysis of the modifications will be presented. Infrared Transmission Microscopy will be shown to be applicable for subsurface imaging, providing a diagnostic tool without damaging the samples.
Material properties of the disruptions in the crystal lattice are then exploited for fabricating various micro-devices. For instance, oxidation-reduction chemistry on laser-induced modifications enables the creation of highly-controllable, uniform and large-area micropillar arrays for solar cell applications, embedded microfludic channels for chip cooling and thru-Si vias for electrical interconnects in Si. These elements, which are challenging to form with conventional methods, can find use in various MEMS and electronics applications. The optical properties (refractive index change) of the structures are used to fabricate functional components such as lenses and gratings buried in chips. Further, the birefringence effect induced in Si may lead to holograms and other photonic applications, such as creating wave plates and polarizers. These functional optical and MEMS elements created inside Si, may find use in imaging and sensing in the near- and mid-infrared wavelength range, as well as in micro-devices towards micro-surgical tools, micro-motors, and micro-resonators. Thus, these capabilities are leading to a new fabrication approach in Si, which is fully CMOS compatible, rapid and mechanically robust, and builds on the optical,electrical and chemical properties of the modified volumes in Si.
[1] Tokel et. al., arxiv.org/abs/1409.2827
[2] Tokel et. al, Direct Laser Writing of Volume Fresnel Zone Plates in Silicon., CLEO/Europe - EQEC, Munich, Germany, 2015.
[3] Tokel et. al., 3D Functional Elements Deep Inside Silicon with Nonlinear Laser Lithography, APS March Meeting, Baltimore, USA, 2016.
9:00 PM - ED7.5.17
The Influence of Local Defects on the Magnetic Properties of NiCo2O4
Sibylle Gemming 1 2 , Matthias Zschornak 1 3 , Parul Pandey 1 , Yugandhar Bitla 4 , Ying-Hao Chu 4
1 , Helmholtz-Zentrum Dresden-Rossendorf, Dresden Germany, 2 Institute of Physics, Technische Universität Chemnitz, Chemnitz Germany, 3 Experimental Physics, TU Bergakademie Freiberg, Freiberg/S Germany, 4 , National Chiao Tung University, Hsinchu Taiwan
Show AbstractTransition metal oxides exhibit a wealth of physical phenomena, among them ferroic properties such as ferroelasticity, ferroelectricity and ferromagnetism, or their combination in multiferroics. In addition, they are also sensitive to further environmental changes such as temperature, irradiation with light, the external partial pressure of oxygen or the bombardment with ions and subsequent structural changes. Here we study the spinel NiCo2O4 (NCO), which exhibits a unique combination of electrical conductivity, infrared transparency, electro catalytic activity, and ferrimagnetic order, which makes it an attractive material for spintronic applications. The NCO thin film’s electrical and magnetic properties can be manipulated from high temperature ferrimagnetic and metallic to low temperature ferromagnetic and insulating by changing the growth temperature. High quality epitaxial NCO films on MgAl2O4 (100) substrate exhibit metallic behavior accompanied by ferrimagnetic order with a moment ~2 μB/fu. He-ion irradiation with fluence ranging from 5×1015/cm2 – 3×1016/cm2 results in changes of the out-of-plane lattice parameter of these films without changing its in-plane lattice parameter. Upon irradiation the magnetic moment increases drastically to ~ 4 μB/fu. X-ray absorption spectroscopic studies suggest possible charge redistribution between the different metal sites, which complies well with the increase in the magnetic moment.
For analyzing the influence of defects on magnetization, conductivity and stability of NCO we performed spin-polarized electronic structure calculations with density functional theory. Total energies, magnetization, and densities of states have been calculated to analyze the dependence of the magnetization on different structural deviations from the perfect bulk crystal: epitaxy strain caused by the substrate, he ion-induced reordering of the site occupancy by the cations and damage by the ion beam, which results in oxygen vacancies and local stoichiometry deviations. The epitaxy strain is modeled by a biaxial compression and a resulting expansion in the third dimension, matching well the experimental structure data. Epitactic clamping reduces the band gap and quenches the magnetic moment of the ground state bulk structure. To account for possible ion-induced redistributions of the metal cations between different lattice sites, we investigated inverse spinel and the highly symmetry spinel. Cation reordering likewise quenches the magnetic moment observed for the bulk ground state. As X-Ray absorption measurements indictae reduced cation valence we also took into account oxygen vacancies. For both metal occupancy patterns, vacancy configurations are obtained, which lead to a magnetic moment comparable with the experimental value even in the presence of an epitaxy strain. These findings underline the importance of point defects for the macroscopic properties of the material.
Funding by the VI Memriox is gratefully acknowledged.
9:00 PM - ED7.5.18
Reliable Resistive Switching Memory with Self-Compliance Based on Electrodeposited CuOx Multilayer
Min-Kyu Kim 1 , Jang-Sik Lee 1
1 , Pohang University of Science and Technology (POSTECH), Pohang Korea (the Republic of)
Show AbstractResistive random access memory (ReRAM) is a kind of emerging nonvolatile memory with metal-insulator-metal structure and has been regarded as the potential next-generation memory device to replace the charge-based memory because of its simple device structure, good scalability, and fast switching speed. Despite these advantages, the practical application of ReRAM has been limited due to reliability and current compliance issues. To facilitate the practical application of ReRAM, it is necessary to solve the problem of reliability and compliance current issues at low production cost. Here, we demonstrate that reliable ReRAM with self-compliance can be fabricated by electrochemical deposition (ECD) of CuOx multilayer. The multilayer CuOx structure, which can be easily synthesized by the simple solution process, is adopted to improve the electrical properties of devices. This structure including a current limiting layer can limit ON current and enhance the device uniformity. Devices with a multilayer structure show reliable and uniform self-compliant resistive switching behavior. The origin of resistive switching is thought to be due to formation and rupture of conductive Cu filaments. Devices based on the multilayer structure exhibit long data retention and good endurance characteristics. This simple method to improve the electrodeposited ReRAM performance can offer an opportunity to realize the next generation nonvolatile memory based on electrochemical deposition process with reliability as well as self-compliance property.
9:00 PM - ED7.5.19
Flexible Threshold Switching Device Based on Electrochemical Deposition
Youngjun Park 1 , Jang-Sik Lee 1
1 , POSTECH, Pohang Korea (the Republic of)
Show AbstractWith conventional semiconductor fabrication process approaching its scaling limit, cross-point memory device structure has recently been attracted considerable attention as the future device technology. Among candidates for the next-generation memory device, resistive switching random access memory (ReRAM), which has advantages of simple structure, fast write/erase speeds, and low power consumption, has been researched for cross-point device applications to achieve high-density memory devices. However, the undesired sneak currents originated from low-resistance state of ReRAM cells may induce sensing errors and power consumption. To solve these issues we fabricated threshold switching device using electrochemical deposition to suppress the undesired sneak current. Also, we prepared the device on the flexible polyethylene terephthalate (PET) substrate to show a feasibility of application to high-density flexible memory devices. Electrochemical deposition was used to deposit the threshold switching layer by bottom-up process. We demonstrate that the electrical characteristics and flexibility of fabricated flexible switching devices offer new possibilities for flexible high-density cross-point memory applications.
9:00 PM - ED7.5.20
First-Principles Study on Charge Trap States in Amorphous Si3N4-x
Gijae Kang 1 , Seungwu Han 1
1 , Seoul National University, Seoul Korea (the Republic of)
Show AbstractAs the flash memory market has grown rapidly during the last decades, the needs to overcome the scaling limitation and the reliablity problem of the floating gate memory have been increased significantly. One of the most promising alternatives to the convential floating gate storage is the charge trap memory device in which amorphous silicon nitride (Si3N4) is utilized as the charge trapping layer. The high scalability and the retention capability originated from localized mid-gap states render the material to be a viable candidate for the memory application. It is clear that the device performance of charge trap memory is governed by the characteristics of the trap level, and yet the origin of the trap states is still under debate.
In this study, we carried out first-principles calculations to study the nature of the trap states in nitrogen-deficiant amorphous silicon nitride (Si3N4-x). The amorphous structures are generated by melt-quench procedure using density functional theory (DFT) molecular dynamics. Each structure is optimized with hybrid functinoal method in which the description of energetics and electronic structure is superior to conventional DFT.
The trap states are analyzed and categorized by their atomic and electronic configuration, and the charge injection levels are calculated using the thermodynamic formation energy of each charged trap. It turns out that the undercoordinated Si atoms originated from the missing N atom form various types of defect state, and the trap level distribution from the states is in close agreement with experimental data. This study will give a useful insight into designing and optimizing the charge trap devices based on amorphous Si3N4.x.
9:00 PM - ED7.5.21
Resistive Switching Characteristics of All-Solution-Processed Ag/TiO2/Mo-Doped In2O3 Nonvolatile Memory Device
Sujayakumar Vishwanath 1 , Jihoon Kim 1
1 , Kongju National University, Chungcheongnam-do Korea (the Republic of)
Show AbstractA resistive random access memory device plays an important role in all modern electronic devices for data storage, processing and communication; thus, the developments of solution based resistive memory devices are essential for the realization of cost effective electronics. In this paper, we demonstrate that electrochemical-metallization-based resistive switching random access memory (ECM-based ReRAM) devices with an Ag/TiO2/Mo-doped In2O3 configuration through a simple solution-based process. Both TiO2 and Mo-doped In2O3 layers in the memory device were spin-coated with polymer-assisted-solution inks formulated by coordinating Ti-, Mo-, and In-complex with a water soluble polymer. The Ag top electrode was inkjet-printed with Ag nanoparticle ink. The memory devices fabricated by all-solution processes demonstrated excellent bipolar switching behavior with a high resistive switching ratio of 103, excellent endurance of more than 1000 cycles, stable retention time greater than 104 s at elevated temperatures, and fast programming speed of 250 ns. The characterization results of the conduction mechanism in high and low resistive states indicate that the resistive switching is caused by the formation and rupture of nano-sized Ag conducting filaments in the TiO2 layer. These results suggest the potential of all-solution-based ECM-based ReRAM for developing future nonvolatile memory devices at low cost.
9:00 PM - ED7.5.22
Effect of Off-Center Ion Substitution in Morphotropic Composition Lead Zirconate Titanate
Mohan Bhattarai 1 , Shojan Pavunny 2 , Alvaro Instan 1 , James Scott 3 1 , Ram Katiyar 2
1 , Department of Physics and Institute for Functional Nanomaterials, University of Puerto Rico, San Juan, Puerto Rico, United States, 2 , Department of Physics and Institute for Functional Nanomaterials, University of Puerto Rico, San Juan, Puerto Rico, United States, 3 School of Chemistry and Physics, St Andrews University, St Andrews, Scotland, United Kingdom
Show AbstractA detailed study of the effect of off-center donor ion (Sc3+) substitution on structural, microstructural, optical, dielectric, electrical and ferroelectric properties of morphotropic composition lead zirconate titanate electroceramics with the stoichiometric formula Pb0.85Sc0.10Zr0.53Ti0.47O3 (PSZT) and synthesized by a high energy solid-state reaction method was carried out. Powder x-ray diffractometry was used to identify the stabilized tetragonal phase (space group ) with considerably reduced tetragonal strain, c/a = 1.005. An analysis of the thermal dependence of the Raman results indicated the smooth order-disorder displacive (ferroelectric-paraelectric) phase transition as revealed by the observed disappearance of the soft modes A1 (1TO) and A1 (2TO) and the emergence of TO2, TO3, and TO4 hard modes above 460 K. The dielectric response of Pt/PSZT/Pt metal-ferroelectric-metal (MFM) capacitors was probed over a wide range of temperatures (85-600 K) and frequencies (102-106 Hz). Thermally activated dynamic and static conduction processes indicates hopping conduction mechanism (Eact ≤ 0.015 eV) and the formation of small polarons induced by the electron and/or hole-lattice (phonon) interaction ( Eact ≥ 0.1 eV) at low (100−300 K) and high temperatures (300−600 K), respectively. The reduced ferroelectricity obtained is in good agreement with the largely reduced tetragonal strain observed in this sample. DC current conduction is dominated by Poole-Frenkel mechanism that assumes a Coulombic attraction between detrapped electrons and positively charged stationary defect species in the polycrystalline matrix.
9:00 PM - ED7.5.23
Forming-Free Resistive Switching Characteristics of Ag/CeO2/Pt Structure
Hong Zheng 1 , Hyung Jun Kim 1 , Paul Yang 1 , Jong-Sung Park 1 , Chi Jung Kang 1 , Tae-Sik Yoon 1
1 , Myongji University, Yongin Korea (the Republic of)
Show AbstractResistive switching characteristics of metal oxide layer have been actively investigated for the application to a nonvolatile resistive random access memory (RRAM) operating by the reversible transition between high and low resistance states. In general, the resistive switching results from the reversible formation and rupture of conducting filaments or modulation of oxide/electrode interfaces, which involves the migration of oxygen ions. Considering this regard, we investigated the resistive switching of CeO2 layer, which is known to be a good oxygen ionic conductor with variable valence states (Ce3+ and Ce4+). In this study, the Ag/CeO2(45-nm)/Pt structure with a sputter-deposited and subsequently annealed CeO2 layer exhibited a forming-free resistive switching with a large memory window (resistance ratio > 106) at a low switching voltage (< ±1~2 V) in voltage sweep condition. Notably, the switching did not require the high-voltage forming operation to induce the local soft-breakdown. Also, it retained a large memory window (> 105) even at a voltage-pulse operation (±5 V, 10 ms). The switching is thought to be facilitated thanks to the high oxygen ionic conductivity particularly at the grain boundaries of the CeO2 layer, where the oxygen vacancy-rich conducting filament could be formed without a high voltage forming operation. The presented results demonstrated the feasibility of the application of CeO2 for the resistive switching devices with a large memory window and a low switching voltage without a high voltage forming operation.
Acknowledgments
This research was supported by Nano×Material Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (NRF-2011-0030228).
9:00 PM - ED7.5.24
Resistive Switching Properties and Behaviors in Core-Shell Ni/NiO/HfO2 Nanowire ReRAM Device
Ting Kai Huang 1 , Jui-Yuan Chen 1 , Yi-Hsin Ting 1 , Wen-Wei Wu 1
1 Materials Science and Engineering, National Chiao Tung University, Hsinchu Taiwan
Show AbstractResistive Random Access Memory (RRAM) is one of the most promising nonvolatile memory because it has several advantages; for example, simple MIM (metal-insulator-metal) structure, fast operation speed, high endurance, high retention, and low energy consumption. However, the reliability is not persistent and completely switching mechanism is not fully understood.
In this work, we deposited different metal oxide (HfO2, Al2O3) covering the Ni/NiO nanowire by atomic-layer-deposition (ALD). The different properties, including electrical characteristics, surface morphology, and elements distribution have been systematically investigated. The electrical characteristics were excellent, and the endurance could up to 205 cycles. It is pretty good for 1-D nanostructure. Also, we used focus-ion-beam (FIB) to prepare TEM sample subsequently following TEM observation. From the TEM analysis, we made sure where the conducting filament (CF) was and what the element components of CF were. The diffusion of oxygen vacancies formed the conducting filament, resulting in the change of morphology. The study enriched the understanding of the mechanism and could help achieve better switching properties of RRAM.
9:00 PM - ED7.5.26
Direct Observation of Resistive Switching Behavior in Core-shell Ni/NiO Nanowires Based Memristor Crossbar
Yi-Hsin Ting 1 , Jui-Yuan Chen 1 , Chun-Wei Huang 1 , Ting Kai Huang 1 , Wen-Wei Wu 1
1 Materials Science and Engineering, National Chiao Tung University, Hsinchu Taiwan
Show AbstractThe crossbar structure of Resistive Random Access Memory (RRAM) is the most promising technology in the future nonvolatile memory devices, which is expected to develop nanoscale, high performance, and low power consumption devices. The aim of this work is to observe the reversible formation and disruption of the conductive filament (CF) by real time observation.
The Ni/NiO nanowires was utilized to form a cross structure, which restricted the position of CF at the cross-center. From in situ TEM images, the significant change of morphology appearing at the cross-center was observed, which resulted from the absence and backfill of the oxygen-ions. In addition, EDS analysis showed that there was a lower O/Ni ratio at the cross-center after the SET process; conversely, a higher O/Ni ratio would present after the RESET process. The results demonstrated that the CF is dominated by oxygen-ions movement. Moreover, the crossbar structure of RRAM device exhibited good electrical characteristic.
Owing to the crossbar structure of RRAM is the most potential method to fabricate high density nanoscale RRAM devices. This study provides a useful information for understanding the switching mechanism of crossbar structure.
9:00 PM - ED7.5.27
Organic Non-Volatile Memory Using Nickel Oxide Nano-Floating-Gate and Polymer Electrets
Yeon-Ju Kim 1 , Minji Kang 1 , Min Hye Lee 1 , Ye-Jin Jeon 1 , Kyeongil Hwang 1 , Kyoungtae Hwang 1 , Dong-Yu Kim 1
1 , GIST, Gwangju Korea (the Republic of)
Show AbstractOrganic non-volatile memories made of organic materials and nano-floating-gates have received great attraction recently, due to simple manufacture, light-weight, low-cost and flexibility. Especially, it has been shown that organic field-effect transistor (OFET)-type memory devices can involve non-destructive readout, easily integrated structure and high reliability. Here we demonstrate the OFET-type memory devices fabricated by combination with polymer electret (poly(2-vinyl naphthalene) (PVN)) as a tunneling dielectric layer and nano-floating gates (nickel oxide nanoparticles) as a charge trapping layer, which are inserted between the electret layer and a high-k polymer dielectric, poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)]. Poly(3-hexylthiophene) and high-mobility poly(thienylvinyl ethylhexyl benzotriazole (PTVEhB) were used as p-channel semiconductors in top-gate/bottom-contact device structure. The optimized memory devices showed significant improvement in memory performance such as a large memory window, a quasi-permanent retention time, low power consumption and stable switching behavior. Moreover, solution-processed nickel oxide nano-floating-gates exhibited excellent charge trapping ability in the OFET-type memory devices.
9:00 PM - ED7.5.28
Detection and Mapping of Static Charges in Nanometer Scale Memory Devices
Rudra Dhar 1
1 Electronics & Communication Engineering, National Institute of Technology Mizoram, Aizawl, Mizoram, India
Show AbstractDetecting and mapping the charges stored as data bits in memory devices through reverse engineering via scanning probe microscopy is the goal of this work. The data present in the nanoscale memory devices are stored as electrical static charges in the floating gates (FG’s) of each transistor (FET) in each memory cell. Detecting these charges in the form of logic levels of “1b” and “0b” from each FG a mapping of the charges was acquired. Previous work has been performed on 0.15 mm Flash memory devices and also on 0.35 mm CMOS technology node NOR Flash EEPROM [1-3]. Here for the first time charge detection has been carried out on nanometer scale discrete memory devices of 80 nm gate length.
Direct charge measurement has been carried out using Scanning Capacitance Microscopy (SCM) to detect and map the charges in each memory cell of the FG’s in a Sandisk 1GB memory device. The SEM cross section image clearly detected the FG transistor gate length of the memory device to be 80 nm. Binary logic programming was performed and word bits in the form of “1b” and “0b” was written across the nanoscale memory device. Reverse Engineering was performed based on failure analysis on the memory device and the sample was prepared by removing the bulk silicon substrate from the backside of the die. The bulk substrate removal was executed keeping a nano-layer of around 50 nm of thin silicon to achieve the contact potential at the time of scanning. The contact potential acquired at the back-contact helped in performing reverse engineering via SCM measurements, which eventually generated a mapping of the static charges along with the FGs/channels and the active regions of the device from the backside of the die. The SCM images evidently detected the static charges (ON/OFF or “1b/0b”) on the FGs of the devices.
Reference
[1] R. S. Dhar, St. J. Dixon-Warren, M. A. Kawaliye, J. Campbell, M. Green, and D. Ban, Material Research Society (MRS) Proceedings Fall 2012 conference, 1527, 2012.
[2] C.D. Nardi, R. Desplats, P. Perdu, C. Guérin, J.L. Gauffier, and T.B. Amundsen, Proc. 31st ISTFA, pp. 256-261, Nov. 2005.
[3] C.D. Nardi, R. Desplats, P. Perdu, C. Guérin, J.L. Gauffier, and T.B. Amundsen, Proc. 32nd ISTFA, pp. 86-93, Nov. 2006.
Symposium Organizers
Andrew Kummel, University of California, San Diego
Alexander Demkov, University of Texas, Austin
John Robertson, Cambridge Univ
Shinichi Takagi, University of Tokyo
ED7.6: 2D and Others
Session Chairs
Thursday AM, April 20, 2017
PCC North, 100 Level, Room 131 A
9:00 AM - ED7.6.01
Cause of RRAM Device Switching Variability and its Impact on Memrisitve Dynamic Adaptive Neural Network Arrays
Karsten Beckmann 1 , Joshua Holt 1 , Nadia Suguitan 1 , Joseph Van Nostrand 2 , Nathaniel Cady 1
1 , SUNY Polytechnic Institute, Albany, New York, United States, 2 , Air Force Research Laboratory/RITB, Rome, New York, United States
Show AbstractResistive Random Access Memory (RRAM) is a novel form of non-volatile memory and slowly making its entry into the field of neuromorphic or neuro-inspired circuit architecture. It has already been demonstrated as a good candidate for storage applications, with promising write/read times and storage density. One particular problem that needs be addressed is the dilemma of high on/off resistance ratio, switching variability and manufacturability in a high throughput process. These properties are widely seen as mutually exclusive. High on/off ratio with low variability typically requires fabrication of an in situ, sub-stoichiometric switching layer. Slight changes in the stoichiometry have a strong effect on switching performance and attaining the desired consistency across a 300mm wafer is extremely difficult. Hence, there is a desire to use precise atomic layer deposition (ALD) techniques to deposit a stoichiometric oxide for the switching layer, in conjunction with a strong oxygen scavenger layer to allow for a robust manufacturing process. Common oxygen scavenger layers like titanium, hafnium or zirconium introduce a high amount of variability due to redox reactions at the interface of the switching and oxygen scavenger layer. This is likely to cause a local change to the grain boundaries or a switching of crystallographic direction in the vicinity of the filament, thus contributing to a significant amount of the encountered HRS variability. In response to these shortcomings of existing RRAM devices, we developed a reliable process to build RRAM using a fully stoichiometric HfO2 switching layer and a tungsten top and bottom electrode. Titanium, hafnium and zirconium were each investigated as a strong oxygen scavenger layers, due to their material properties introduce a high amount of switching variability. Beyond these materials, we are currently testing novel oxygen scavenger layers, including lanthanum, erbium and niobium. In particular niobium shows a promising behavior, in particular the niobium monoxide allotrope which has the lowest Gibbs free energy of oxide formation. The niobium monoxide allotrope is particularly attractive due to its relative conductivity (vs. other more insulating oxides) allowing it to preserve the conductivity of the electrode / switching oxide interface. In summary, our work will lead to a pathway of choosing an oxygen scavenger layer material. Characteristic properties of each material will be connected to the gathered variability value. These results should lead to a way to a reliable process utilizing a stoichiometric and precise ALD process for the switching layer.
9:15 AM - ED7.6.02
The Analog Information Limit of Magnetic Domain Wall Positions in Nanowires
Sumit Dutta 1 , Saima Siddiqui 1 , Joseph Finley 1 , C. A. Ross 1 , Marc Baldo 1
1 , Massachusetts Institute of Technology, Cambridge, Massachusetts, United States
Show AbstractNonvolatile memory and logic devices are often made of magnetic nanowires with mobile domain walls (DWs). When the wire width is scaled to below 100 nm, the line edge roughness (LER) plays a larger role in domain wall dynamics. LER leads to a discrete number of DW positions along a nanowire [1]. We look into how domain wall pinning sites are distributed in sub-100-nm-wide wires with LER and explain their effects on information density and control in DW memory and logic applications such as racetrack memory.
We explore the edge profile of fabricated 60-nm-wide Co wires and develop a model of wire edge profiles based on a fractal function. The fabricated wires have an LER of 2-3 nm, which is a result of our process [2]. We determine a correlation length from the power spectral density of the edge profile of fabricated wires, and use that to set the period of the fundamental component in the Weierstrass-Mandelbrot function used to model deviations in the wire edge. The fractal function modeling the wire edge is made of summed periodic sinusoids with a random phase, where the amplitude decreases with increasing spatial frequency. The fractal model represents a physically reasonable method to capture the effects of wire patterning [3]. The agreement we find between the fractal edge profile and the edge profile in SEM images of fabricated wires allows us to model realistic DW dynamics.
We use a micromagnetic solver to model DW motion and pinning in wires generated with fractal LER. We nucleate a single DW at each position along the wire and observe the equilibrium position of each DW in the landscape of pinning sites. We find that the DW traps are spaced at a scale no longer than the correlation length. Our Fourier analysis of fractal edge profiles shows decreasing power spectral density with increasing spatial frequency. In wires generated with uniformly distributed random edge deviations, our Fourier analysis shows a more uniform power spectral density over spatial frequencies. In experiment, we apply an external magnetic field along the nanowires to move DWs between pinning sites. The distributions of the distances that the DWs travel are related to the distributions of discrete DW pinning sites. We will explain how LER-influenced trap distributions affect the scaling limits of memory and logic devices based on magnetic nanowires.
[1] X. Jiang et al, Nano Letters, 11 (2011)
[2] J. A. Currivan et al, J. Vac. Sci. Tech B, 32, 021601 (2014)
[3] H. Ji and M. O. Robbins, Physical Review B, 46 (1992)
9:30 AM - *ED7.6.03
Tunnel FETs—Vertical or Lateral?
Huili Xing 1 , Rusen Yan 1 , Mingda Li 1 , Suresh Vishwanath 1 , Xiang Li 1 , Hyunjea Lee 1 , Randall Feenstra 2 , Debdeep Jena 1
1 School of Electrical and Computer Engineering, Cornell University, Ithaca, New York, United States, 2 Department of Physics, Carnegie Mellon University, Pittsburgh, Pennsylvania, United States
Show AbstractTunnel Field Effect Transistors (TFETs) have been touted as the most promising candidate for beyond Si CMOS electronic switches. Both the vertical geometry, where tunneling is parallell to the gate electric field line, and the lateral geometry, where tunneling is perpendicular to the gate electric field line, have been under intense investigation in various groups worldwide. What are the pros and cons for each geometry? In this talk, we will discuss these issues as well as present the recent experimental results on TFETs based on 2D materials.
10:00 AM - *ED7.6.04
2D Semiconductor Electronics—Advances, Challenges and Opportunities
Ali Javey 1
1 , University of California, Berkeley, Berkeley, California, United States
Show AbstractTwo-dimensional (2-D) semiconductors exhibit excellent device characteristics, as well as novel optical, electrical, and optoelectronic characteristics. In this talk, I will present our recent advancements in defect passivation, contact engineering, surface charge transfer doping, ultrashort transistors, and heterostructure devices of layered chalcogenides. We have developed a defect repair/passivation technique that allows for observation of near-unity quantum yield in monolayer MoS2. The work presents the first demonstration of an optoelectronically perfect monolayer. Forming Ohmic contacts for both electrons and holes is necessary in order to exploit the performance limits of enabled devices while shedding light on the intrinsic properties of a material system. In this regard, we have developed different strategies, including the use of surface charge transfer doping at the contacts to thin down the Schottky barriers, thereby, enabling efficient injection of electrons or holes. We have been able to show high performance n- and p-FETs with various 2D materials, including the demonstration of a FET with 1nm physical gate length exhibiting near ideal switching characteristics. Additionally, I will discuss the use of layered chalcogenides for various heterostructure device applications, exploiting charge transfer at the van der Waals heterointerfaces. I will also present progress towards achieving tunnel transistors using layered semiconductors.
11:00 AM - *ED7.6.05
Graphene and Beyond—Creating and Exploring Atomically Thin Materials
Joshua Robinson 1
1 , The Pennsylvania State University, University Park, Pennsylvania, United States
Show AbstractThe last decade has seen nearly exponential growth in the science and technology of two-dimensional materials. Beyond graphene, there is a huge variety of layered materials that range in properties from insulating to superconducting. Furthermore, heterogeneous stacking of 2D materials also allows for additional “dimensionality” for band structure engineering. In this talk, I will discuss recent breakthroughs in two-dimensional atomic layer synthesis and properties, including novel 2D heterostructures and novel 2D nitrides. Our recent works demonstrate that the properties of 2D materials, especially those grown via CVD, are extremely sensitive to the substrate choice. I will discuss substrate impact on 2D layer growth and properties, doping of 2D materials with magentic elements, selective area synthesis of 2D materials, and the first demonstration of 2D gallium nitride (2D-GaN). Our work and the work of our collaborators has lead to a better understanding of how substrate not only impacts 2D crystal quality, but also doping efficiency in 2D materials, and stabalization of nitrides at their quantum limit.
11:30 AM - ED7.6.06
Quasi-2D β-Ga2O3 Field-Effect Transistors with Hexagonal Boron Nitride Gate Dielectric
Janghyuk Kim 1 , Sooyeoun Oh 1 , Jihyun Kim 1
1 , Korea University, Seoul Korea (the Republic of)
Show Abstractβ-Ga2O3 is a wide band gap (4.8 eV) semiconducting material with excellent chemical and thermal stabilities. As the breakdown voltage of β-Ga2O3 is estimated to be as high as 8 MV/cm, it can be utilized as high-power electronic switching applications. After β-Ga2O3 thin layers were successfully cleaved from bulk single crystals by mechanical exfoliation method, the study of high power 2D nano-electronics using β-Ga2O3 received a huge attention. β-Ga2O3 is not a two dimensional van der Waals material such as graphene and MoS2. However bulk β-Ga2O3 crystal which has monoclinic structure can be easily cleaved into thin nano-flakes in the (100) direction since it has larger lattice constant compared to other directions. And this ultrathin β-Ga2O3 flakes can be combined with other 2D materials such as hexagonal boron nitride (h-BN) and graphene to make down-scaled, flexible devices.
We demonstrated β-Ga2O3 nano-flakes based dual gated thin film transistors with h-BN gate dielectric. After β-Ga2O3 nano-flakes were mechanically exfoliated from bulk crystal using scotch tape method, field-effect transistors were fabricated using these nano-flakes as a channel material using conventional photolithography process. 2D h-BN a gate dielectric, was transferred onto β-Ga2O3 nano-flakes using PDMS stamp method. The quality of β-Ga2O3 flakes and h-BN was maintained during exfoliation and photolithography process as observed using raman spectroscopy.
The device showed an typical FET behavior, which is represented by the drain current modulation with high on/off ratio and low gate leakage current. It also operated stably at elevated temperatures without suffering from air-unstability. The dual gated nano-flakes FETs exhibited superier channel modulation when both front and back gates operational compared to either front or back-gating alone. There was no electrical breakdown up to biases of VDS =100 V and VGS = -100 V, and the stable performance of the front and back-gated FETs shows the potential for electronic applications. The Introduction of 2D h-BN with very smooth and dangling bond free surface can enhance the electrical properties and stability of the thin film transistors. All these results indicate that the β-Ga2O3 is a promising material for high power and high temperature nano-electronics. The details of the fabrication procedure and results will be presented.
11:45 AM - ED7.6.07
Approaching the Quantum Conductance Limit in Carbon Nanotube Array Transistors
Gerald Brady 1 , Austin Way 1 , Nathaniel Safron 1 , Katherine Jinkins 1 , Harold Evensen 2 , Padma Gopalan 1 , Michael Arnold 1
1 , University of Wisconsin–Madison, Madison, Wisconsin, United States, 2 Engineering Physics, University of Wisconsin-Platteville, Platteville, Wisconsin, United States
Show AbstractThe quantum conductance limit (2G0 = 4e2/h) for carbon nanotubes (CNTs) was reached over a decade ago in field-effect transistors (FETs) constructed from a single tube channel. However, in large-scale arrays of CNTs like those needed for technology, challenges in CNT sorting, processing, alignment, and contacts, which give rise to non-idealities, have resulted in a conductance per CNT far from the quantum conductance limit. As a result, CNTs have failed to live up to their hype, while underperforming bulk semiconductors such as Si and GaAs in terms of on-state current and conductance, by 6-fold or more. We present our recent progress overcoming these materials science challenges to achieve CNT array FETs approaching the quantum limit with a high packing density and high performance in the metrics of current and conductance density. The CNT array FETs are fabricated through a combination of CNT purification, solution-based assembly, and CNT treatment, which enables a high conductance reaching 0.46 G0 per CNT. The current density is seven times higher than the previous state-of-the-art CNT array FETs made by other methods while the high semiconducting purity of the polymer sorted CNTs enables simultaneous high on/off conductance modulation greater than 104. Importantly, the saturated on-state current density is as high as 900 μA μm−1, and exceeds Si and GaAs FETs of similar dimensions, which, for the first time, demonstrates the competitive advantage of CNT arrays for logic, wireless communications, and other semiconductor electronics technologies.
12:00 PM - *ED7.6.08
Two Dimensional Materials for Electronic Devices
Seongjun Park 1
1 , Samsung Advanced Institute of Technology, Suwon-si, Gyeonggi-do Korea (the Republic of)
Show AbstractTwo dimensional (2D) materials are crystalline materials with layered structures, including Graphene, h-BN, and Transition Metal Di-chalcogenides (TMD’s). Each of their layers is consisting of one or a few atomic layers and they form van der Waals interactions with neighbouring layers. Atomically thin 2D materials range from semi-metallic graphene, semiconducting TMD’s to insulating h-BN. They have been studied intensively due to their extraordinary material properties.
We have been investigated 2D materials in two directions. One is to enhance the performance and the processibility of Si technology for near term applications. Especially, we have focused 2D materials as interface materials due to their atomically thin nature. For example, they are good candidates for diffusion barrier and interface materials between metal and Si to reduce the Schottky barrier heights and contact resistance in source and drain, which is one of the most critical issues for scaling down. We demonstrated a graphene hybrid interconnect for conventional Si semiconducting devices and demonstrated converting the Schottky nature of the Metal and Semi-conductor junctions into the Ohmic contact with 2D materials.
The other direction is to replace Si with 2D materials for post-Si technology and for functional devices that Si technology cannot cover well. We explored the possibility of 2D materials for photo detector and sub-10 nm graphene nanoribbons (GNRs) for a transistor channel. Also we demonstrated a robust way of depositing dielectric materials on chemically inert Graphene, one of the most fundamental challenges for the successful incorporation of 2D materials in electronic devices using physisorbed-precursor-assisted atomic layer deposition.
In this talk, we will cover most of the topics listed above.
12:30 PM - ED7.6.09
Internal Photoemission Spectroscopy Measurement of Energy Barriers between Amorphous Metals and High-K Dielectrics
Melanie Jenkins 1 , Dustin Austin 1 , John McGlone 1 , L. Wei 2 , Nhan Nguyen 2 , John Wager 1 , John Conley 1
1 School of EECS, Oregon State University, Corvallis, Oregon, United States, 2 SDM Division, National Institute of Standards and Technology (NIST), Gaithersburg, Maryland, United States
Show AbstractAs scaling continues beyond the end of the roadmap, device structures with film thicknesses below 10 nm are becoming more common. Conduction through high quality ultrathin layers is dominated by tunneling, which depends exponentially on both the thickness and the height of the energy barrier. Accordingly, smooth electrodes and interfaces are necessary for repeatable performance. In some cases, an appropriate thin dielectric layers may be inserted to "unpin" an interface and thus engineer band offsets. Precise knowledge of barrier heights is therefore critical for predicting and understanding device operation.
Metal-insulator-metal (MIM) tunnel diodes based on Fowler-Nordheim tunneling have shown promise for use in high-speed applications, such as rectenna based energy harvesting and hot-electron transistors. The amorphous metal ZrCuAlNi (ZCAN) has been shown to function well as an ultra-smooth bottom electrode. However, ZCAN suffers from an interfacial oxide layer and thermal instability above ~300C. TaWSi is an alternative amorphous metal that has recently been shown to have a larger work function and stability above 900C.
In this work, internal photoemission (IPE) spectroscopy is used to directly measure the barrier heights between amorphous metal bottom electrodes and various dielectrics in MIM diode structures. To date, there have been few reports of IPE measurements of MIM structures and none on these amorphous metals.
ZCAN, TaWSi, and, TaN bottom amorphous metal bottom electrodes were sputtered onto 100 nm of thermally grown SiO2 on silicon. Dielectric barriers were then deposited via either atomic layer deposition (ALD) or a novel mist deposition technique known as aerosol jet fog (ajFOG). Al and Au dots were then evaporated through a shadow mask to serve as semitransparent (~10 nm thick) top gates. Finally a thicker layer of the same metal served as a contact pad. IPE measurements were performed using a 150W Xe lamp. Photon energy was swept from 2 to 5 eV while voltage was applied to the bottom electrode and current was monitored. A range of negative and positive biases were used to characterize both bottom and top electrodes, respectively. The measured current was corrected to remove dark current and converted to yield. Voltage dependent spectral thresholds were extracted from plots of the (yield)^1/2 vs. incident photon energy. Schottky plots of the spectral threshold vs. square root of the dielectric field were used to determine the zero-field barrier height.
Barrier heights will be reported for all electrode/insulator combinations. Briefly, barrier heights / effective workfunctions were found to be influenced by the specific metal/dielectric combination as well as by the opposite metal electrode. The TaWSi electrodes showed consistently higher barrier heights than the ZCAN, indicating promise as a thermally stable bottom electrode for MIM tunnel diodes.
Supported by the NSF Center for Sustainable Materials Chemistry, CHE-1102637.
12:45 PM - ED7.6.10
All-Transparenet and Flexible Schottky Barrier Transistors and Logics Based on Ion Gel-Gated Graphene/Metal Oxide Heterostructure
Seong Chan Kim 1 , JaeHoon Park 1 , Jeong Ho Cho 1
1 , Sungkyunkwan University, Suwon Korea (the Republic of)
Show AbstractWe demonstrate all transparent and flexible vertical Schottky barrier (SB) transistors and logic gates based on graphene-metal oxide-metal heterostructures and ion gel gate dielectrics. The vertical SB transistor structure was formed by (i) vertically sandwiching a solution-processed indium-gallium-zinc-oxide semiconductor layer between graphene (source) and metallic (drain) electrodes and (ii) employing a separate coplanar gate electrode bridged with the vertical channel through an ion gel. The channel current was modulated by tuning the Schottky barrier height across the graphene-IGZO junction under an applied external gate bias. The high specific capacitance of the ion gel gate dielectrics enabled the Schottky barrier height at the graphene-IGZO junction to be modulated by 0.87 eV using a voltage below 2 V. The resulting vertical devices showed high current densities (~ 4 Acm–2) and on-off current ratios (> 103) at low voltages. The simple structure of the unit transistor enabled successful fabrication of low-power logic gates based on assemblies of devices such as the NOT, NAND, and NOR gates on a plastic substrate. The simple, scalable, and room-temperature deposition of both metal oxide semiconductors and gate dielectrics integrated with transparent and flexible graphene opens up new opportunities for realizing future transparent, flexible, and low-power electronics.
ED7.7: TFET
Session Chairs
Lukas Czornomaz
Huili Xing
Thursday PM, April 20, 2017
PCC North, 100 Level, Room 131 A
2:30 PM - *ED7.7.01
The Impact of Contact Deposition Ambient on the Interfacial Chemistry of 2D Materials
Robert Wallace 1
1 , University of Texas at Dallas, Richardson, Texas, United States
Show AbstractAmong the processes in 2D device fabrication, high contact resistance continues to limit the transition metal dichalcogenide (TMD) device performance and prevent a true understanding of the transport properties in these materials. An often overlooked aspect is the impact of the deposition ambient employed during contact deposition, and the resultant interfacial chemistry that may impact contact/2D conductivity. This aspect has been recently investigated from a device characterization perspective.1,2 In this presentation, we present our recent studies of the in situ interface chemistry of contact interfaces compared to that used in devices fabricated under typical ex situ methods. We find that the chemical state of the metal and the metal−semiconductor interface is highly dependent on the metal deposition conditions.3,4
This work was supported in part by the US/Ireland R&D Partnership (UNITE) under the NSF award ECCS-1407765, the Center for Low Energy Systems Technology (LEAST), one of the six SRC STARnet Centers, sponsored by MARCO and DARPA, and by the Southwest Academy on Nanoelectronics (SWAN) sponsored by the Nanoelectronic Research Initiative and NIST.
1. English, C. D.; Shine, G.; Dorgan, V. E.; Saraswat, K. C.; Pop, E., “Improving Contact Resistance in MoS2 Field Effect Transistors.” In 72nd Annual Device Research Conference (DRC), June 22−25, 2014; IEEE: Santa Barbara, CA, 2014; pp 193−194;
2. English, C. D.; Shine, G.; Dorgan, V. E.; Saraswat, K. C.; Pop, E., “Improved Contacts to MoS2 Transistors by Ultra-High Vacuum Metal Deposition,” Nano Lett. 2016, 16, 3824−3830
3. McDonnell, S.; Smyth, C.; Hinkle, C. L.; Wallace, R. M., “MoS2-Ti Contact Interface Reactions,” ACS Appl. Mater. Interfaces 2016, 8, 8289−8294.
4. Smyth, C.M., Addou, R., McDonnell, S., Hinkle, C. L., Wallace, R. M., “Contact-Metal-MoS2 Interfacial Reactions and Potential Implications on MoS2-Based Device Performance,” J. Phys. Chem. C, 2016, 16, 14719-14729.
3:00 PM - ED7.7.02
Vertical InAs/GaAsSb/GaSb Tunneling Field-Effect Transistors on Si with Sub 50 mV/dec. Operation
Elvedin Memisevic 1 , Johannes Svensson 1 , Markus Hellenbrand 1 , Erik Lind 1 , Lars-Erik Wernersson 1
1 , Lund University, Lund Sweden
Show AbstractVertical InAs/GaAsSb/GaSb nanowire TunnelFETs with diameters of about 20 nm have been fabricated on Si. The nanowire growth technology is used to form a heterostructure where the large lattice mismatch is accommodated by radial relaxation. The geometry further provides excellent electrostatic control, required for TunnelFET operation. While our previous InAs/GaSb TunnelFETs showed close to 60 mV/dec. operation [1], we now introduced an intermediate segment transforming the broken gap to a staggered band alignment. The adjusted bandstructure allowed demonstration of TunnelFETs operating at a min subthreshold slope of 44 mV/dec [2].
For steep slope transistors, operation with limited hysteresis at low drive voltages is required to provide benefits at low Vds (<0.3V) operation. Furthermore, current matching for targeted applications are necessary to benefit from the steep slope operation. For IoT applications, typically 1 nA/µm Ioff is targeted above which the steep slope should extend over a few decades. Finally, sufficient drive current should be delivered in the on-state to drive the parasitics.
We demonstrate that our InAs/GaAsSb/GaSb TunnelFETs can operate with a hysteresis of only 5 mV at I60 and that sub 60 mV/dec operation can be extended over more than two decades. At Vds=0.3V, an I60 of 0.3 µA/µm is evaluated. For a 1 nA/µm Ioff, we achieve Ion=10 µA/µm, demonstrating superior performance compared to Si MOSFFETs at scaled nodes.
[1] E. Memisevic et al Scaling of Vertical InAs–GaSb Nanowire Tunneling … IEEE EDL 37, 966 (2016)
[2] E. Memisevic et al Vertical InAs/GaAsSb/GaSb Tunneling Field-EffectTransistor on Si … IEDM 2016
3:15 PM - ED7.7.03
Band Engineering, Doping and Tunnel FETs with InSe
Yuzheng Guo 1 , John Robertson 2
1 , University of Swansea, Swansea United Kingdom, 2 Engineering Department, University of Cambridge, Cambridge United Kingdom
Show AbstractThere is presently intense interest in the 2D semiconductors such as the transition metal dichalcogenides (TMDs) including MoS2. However, the band edges of TMDs have d-like orbital characters. This means their carrier mobilities are typically of order of 100 cm2/V.s, much less than those of graphene. Black phosphorus(b-P) was discovered in the past few years. This is a 2D semiconductor with p-type band edges. This has mobilities of order 1000 cm2/V.s. However, b-P reacts with water and needs to be encapsulated. Additionally, substitutional dopants tend not to form shallow donor or acceptor sites, but form rebounded closed shell structures. Thus, despite its carrier mobilities, b-P is not such a practical semiconductor.
There is a third class of 2D semiconductors, the GaSe and InSe family. They consist of a vertically stacked metal-chalcogen double layer with van der Waals bonding between layers. Carrier mobilities in InSe are of order 1000 cm2/V.s, which is an order of magnitude larger than MoS2. Here, we consider the band offsets and doping strategies within these systems, particularly from viewpoint of their use in tunnel FETs (TFETs).
The TFET is one method to make a steep slope device with a sharper turn-on characteristic. At present the focus is typically on the WSe2/HfS2 or WSe2/SnS2 heterojunctions which have the desired band alignments. However, HfS2 has low carrier mobilities. Many dopants are unlikely to be active or shallow in HfS2. On the other hand, SnS2 is less chemically stable. Therefore InSe/GaSe could be a good candidate for TFET.
Each layer in InSe has a Se-In-In-Se stacking. The formation energy of GaSe per formula unit is calculated to be 1.95 eV, which is consistent with previous works. InSe has a band gap 2.4 eV. The In sites are 4-fold sp3 bonded, and In-In bond means that the In valence s states are partly filled.
We have calculated the electron affinity (EA) and ionization potential (IP) for monolayers of these materials. We see that the IPs of InSe etc are deeper below the vacuum level than those of the MoS2 group, and thus they are potential higher mobility alternatives to HfS2 or SnS2 in TFET heterojunctions.
We have also calculated substitutional doping at both In and Se sites in monolayer InSe. Zn doping at the Ga site is shallow, only 0.2eV above the VB while Ge doping is deeper, 0.4eV below the CB. Substitutional doping at the Se site by VI and VII elements are all very shallow. As and P doping is just 0.3-0.4eV above the VB while Br and Cl doping is 0.2 and 0.4eV below the CB. The Sn donor site is slightly off-center, but it is still shallow. This behavior contrasts with that of dopants in b-P where they undergo reconstructions to form non-doping sites obeying the 8-N rule.
We also calculated the energy levels of the Se vacancy. These are likely to pin the Fermi level of any metal contacts and determine the Schottky barrier height. The vacancy level lies near midgap.
3:30 PM - *ED7.7.04
2D Crystals for Smart Life
Kaustav Banerjee 1
1 , University of California, Santa Barbara, Santa Barbara, California, United States
Show AbstractThe experimental demonstration of graphene in 2004 has opened up a window to the two-dimensional (2D) world of materials. This has subsequently triggered a surge of research activities on various 2D crystals including single layers of hexagonal-boron nitride (h-BN), several dichalcogenides (such as MoS2 and WSe2), and complex oxides, with novel electronic properties. Atomic scale thicknesses (few Å/layer) of 2D semiconducting crystals and their controllable precise band gaps as a function of number of layers also enable the scaling of electronic devices without inducing performance variations. Moreover, seamless planar synthesis and stacking of 2D crystals on various substrates can be exploited to build novel lateral and vertical heterostructures, respectively.
This talk will highlight and discuss the prospects of such 2D crystals and their heterostructures for designing ultra-low power, low-loss, and ultra-energy-efficient active and passive devices targeted for designing next-generation green electronics needed to support the emerging paradigm of Internet of Everything. More specifically, this talk will examine the genesis of the power dissipation challenge in conventional MOSFETs, and provide an overview of the recently demonstrated 2D-channel tunneling transistor from my group (Nature, 2015) that overcomes this challenge and is a fundamentally different transistor employing several innovations. This talk will also bring forward some other applications uniquely enabled by 2D crystals, including interconnects, sensors and flexible radio-frequency electronics for improving quality of life, and discuss related challenges and opportunities.
4:30 PM - *ED7.7.05
Exploring Interfacial Properties of Pristine MoS2 MOS Interface
Mitsuru Takenaka 1 2 , Shinichi Takagi 1 2
1 , The University of Tokyo, Tokyo Japan, 2 , JST-CREST, Tokyo Japan
Show AbstractTransition metal dichalcogenides (TMDs) have emerged as promising channel materials for deeply-scaled metal-oxide-semiconductor (MOS) transistors since the first transistor operation using exfoliated MoS2 was reported in 2011 [1]. Especially, MoS2 features atomically thin body, semiconductor properties with a sizable bandgap, high mobility, and low permittivity, being expected to enable the device scaling beyond Si MOS transistors. Since each MoS2 layer is believed to have no dangling bond on its surface, a low interface trap density (Dit) is expected at an MoS2 MOS interface. However, interfacial properties of MoS2 MOS interface have not been unveiled yet. Although several group have attempted to evaluate MoS2 interfacial properties by measuring a capacitance and conductance in MoS2 FETs or MoS2 MOS capacitors [2, 3], there are several obstacles to extracting its energy distribution of Dit. One of the obstacles is a large frequency dispersion in capacitance and conductance measurements caused by a large series resistance of a thin MoS2 channel, which requires a complex numerical fitting for Dit extraction. Second is an MoS2 thickness in a MOS capacitor. Since the MoS2 thickness is much thinner than its maximum depletion-layer width, there is no capacitance change according to the depletion-layer width change in C-V measurements, which prevents us from determining the energy distribution of Dit.
To resolve those issues, we have proposed to use a thick-body MoS2 MOS capacitors for C-V measurements. Since the MoS2 thickness is large enough for achieving full depletion, we can apply the conventional techniques to evaluate the energy distribution of Dit, which have originally been developed for evaluation of Si MOS interfaces. By developing a transfer method of a thick MoS2 layer on a Si substrate, we successfully obtained well-behaved C-V curves for MoS2 MOS capacitors with Al2O3, HfO2, and SiO2 gate dielectrics. By applying the Terman method, we found that there were interface traps with a Dit peak of 1×1013 cm-2eV-1 at the energy level of 0.35 eV from the midgap regardless of the gate dielectric, which might be associated with sulfur vacancies. Since we also found that some MoS2 capacitors exhibited no such a Dit peak, the pristine MoS2 interface with no sulfur vacancies seems to have a nearly constant Dit of around 1×1012 cm-2eV-1. when there seems to be no sulfur vacancies. In conjunction with the S.S. analyses of the MoS2 MOSFETs, we have successfully clarified the energy distribution of Dit at MoS2 MOS interfaces. The energy distribution of Dit obtained from the Terman method was also verified by the subthreshold slop analyses of MoS2 MOS transistors. Thus, we successfully clarified native properties of MoS2 MOS interface.
[1] B. Radisavljevic et al., Nat. Nanotechnol., vol. 6, pp. 147, 2011.
[2] W. Zhu et al., Nat. Commun., vol. 5, pp. 1–8, 2014.
[3] X. Chen et al., Nat. Commun., vol. 6, p. 6088, 2015.
[1] M. Takenaka et al., IEDM, 5.8, 2016.
5:00 PM - *ED7.7.06
ON Current Boosting Technology for Si-Based Tunnel Field-Effect Transistors Utilizing Isoelectronic Trap
Takahiro Mori 1
1 , National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba Japan
Show AbstractEntering the age of the Internet of Things, progress in low-power LSI technologies must be accelerated. However, switching characteristics of MOSFETs are fundamentally limited by the subthreshold swing (SS) of 60 mV/decade at 300 K, now which limits further reduction of the operation voltage. Tunnel FETs (TFETs) have been actively investigated because their steep switching characteristics as a result of the tunneling current enable them to achieve sub-60 mV/decade operation.
TFETs utilize tunneling junction, and its high resistivity precludes a sufficiently high ION. For this reason, many researchers are now exploring the use of Ge or III-V materials for the TFET channel because these materials can realize much higher tunneling rates than can be achieved in Si [1]. Si is an indirect gap semiconductor in which the band-to-band tunneling (BTBT) current flows indirectly with the assistance of the phonons. There was a time when this appeared to be the material limit; however, we proposed and then demonstrated new technology that incorporated an isoelectronic trap (IET) to realize higher tunneling rates in Si [2].
In the first demonstration, 11 times ION enhancement was experimentally realized in N-type Si-TFETs using an Al–N IET which was intentionally codoped into the channel [2]. We have also proposed an ION enhancement mechanism in which the IET state intermediates the tunneling transport [3]. Now it is revealed that the IET acts as a stepping stone for electron tunneling and realizes IET-assisted tunneling (IETT) as opposed to BTBT and the IETT enhances the tunneling current in Si by relaxing the k-conservation rule and shortening the tunneling distance [4]. Recently, we demonstrated the ION enhancement for both N-type and P-type IET-TFETs and the better performance of complementary integrated TFET circuits that are inverters and ring oscillators [4]. Unfortunately, the current is still low in TFETs; however, we demonstrated 735 times enhancement of tunneling current in IET-assisted Si-diodes [2]. This is the ION enhancement we can expect under the optimized IET introduction into Si-TFETs. If ION enhancement similar to that in the diode can be realized in TFETs, the IET-TFET circuit would operate with much faster speed. Especially in the VDD range below 0.5 V, it is expected that the IET-TFET circuit operates with comparable speed to the subthreshold MOSFET circuit [5].
Toward the real application, the IET technology provides a new option that is high probability Si-TFETs instead of Ge or III-V TFETs. We believe that the IET technology paves the way to realize the greater performance in Si-based TFET circuits.
References
[1] S. Takagi et al., Symp. VLSI Technol. Dig. Tech. Papers, 2015, p. 22.
[2] T. Mori et al., Symp. VLSI Technol. Dig. Tech. Papers 2014, p. 86.
[3] T. Mori et al., Appl. Phys. Lett. 106, 083501 (2015).
[4] S. Iizuka et al., Mater. Sci. Semicond. Process, in printing.
[5] T. Mori et al., IEDM Tech. Dig., 2016, p. 512.
5:30 PM - ED7.7.07
Probing the Nanostructure in State-of-the-Art FinFET Devices
Pritesh Parikh 1 , Corey Senowitz 3 , Don Lyons 3 , Michael DiBattista 3 , Arun Devaraj 2 , Y. Shirley Meng 1
1 , University of California, San Diego, La Jolla, California, United States, 3 , Qualcomm Technologies Inc., San Diego, California, United States, 2 Physical and Computational Sciences Directorate, Pacific Northwest National Lab, Richland, Washington, United States
Show AbstractWith the current technology node at 16nm and below for CMOS (complementary metal oxide semiconductor) devices, observing variability in individual device structures is a bottleneck for future device engineering. In this respect, visualizing and understanding defects in nanoscale devices presents a challenging goal for the semiconductor device industry. In particular, identifying dopant concentration and structural irregularities are important aspects of this understanding. The ability to observe dopant concentrations as well as gate dielectric stacks in state-of-the-art FinFET devices presents the next frontier towards developing high fidelity logic and memory systems. Using atom probe tomography (APT) and energy dispersive X-ray spectroscopy (EDX), we observe various structural regions in 14 nm finFET devices. The high spatial resolution provided by energy dispersive spectroscopy (EDX) used in a transmission electron microscope (TEM), gives an accurate map of the gate dielectric stack in two dimensions (2-D); but lacks the ability to observe low Z, low concentration dopant species such as boron. The ability of atom probe tomography to probe low concentration species provides a unique benefit in enhancing our understanding of dopant profiles in three dimensions (3-D) and its effect on device performance. This would enable the development of next generation of logic and memory devices.
5:45 PM - ED7.7.08
Charge Transition Levels in ZrO2 and Si:ZrO2 Interfacial Layer Probed by DLTS
Arvind Kumar 1 , Sandip Mondal 1 , KSR Koteswara Rao 1
1 Physics, Indian Institute of Science, Bangalore, Karnataka, India
Show AbstractThe native defects in ZrO2 band gap or at ZrO2/Si interface leads to the threshold voltage shifts, Fermi level pinning and various other reliability concerns in CMOS devices. Henceforth, it is necessary to recognize the origin of defects and their quantifications. There are large numbers of theoretical reports dealing with the oxygen vacancy related defects states in ZrO2. On the other end, experimental assessments are limited due to the large band gap of ZrO2. In spite of its industrial significance a consistent experimental estimation of these traps states distribution in ZrO2 band gap and their capture cross-sections are limited. The theoretical and first principal studies are constructed on the basis of ideal circumstances and which are not true in the case of real devices. DLTS is a powerful method to study the traps parameters. In this work, the origin of the traps in zirconia films and at the Si/ZrO2 interface is experimentally probed with DLTS. The traps present in the bulk of ZrO2 communicating with interfacial traps (as it is in the range of tunneling/hopping distances), lastly this can be emitted to Si conduction or valence band. We observed five prominent traps states and we believe these are associated to oxygen vacancy in various charge states. The activation energies of traps states are in the range of 1.16 – 1.84 eV from the ZrO2 conduction band edge. The capture cross-sections (s) values are low enough (10-21 cm2), which recommend a negligible influence during the device operation. The quite low ‘s’ values corroborated the fact that the traps levels are oxygen related trap in ZrO2 band gap. This study will be useful to disclose the numerous fascinating facts witnessed in ZrO2 such as resistive switching, threshold voltage instabilities and leakage current problems reconciled by oxygen vacancy related traps.
Symposium Organizers
Andrew Kummel, University of California, San Diego
Alexander Demkov, University of Texas, Austin
John Robertson, Cambridge Univ
Shinichi Takagi, University of Tokyo
ED7.8: Processing and Others
Session Chairs
Alexander Demkov
John Robertson
Friday AM, April 21, 2017
PCC North, 100 Level, Room 131 A
9:45 AM - ED7.8.02
How Do the Electrodes Affect the Electrical Response of a M/La2NiO4/M' Memristive Device?
Klaasjan Maas 1 , Dolors Pla Asesio 1 , Sarunas Bagdzevicius 1 , Michel Boudard 1 , Quentin Rafhay 2 , Carmen Jimenez 1 , Monica Burriel 1
1 , Univ Grenoble Alpes, CNRS, LMGP, Grenoble France, 2 , Univ Grenoble Alpes, CNRS, IMEP-LAHC, Grenoble France
Show AbstractThe simple Metal-Insulator-Metal (MIM) capacitor-like structure has gained increasing interest with the recent development of research around ReRAMs, or Resistive Random-Access Memories. ReRAM is an emerging type of non-volatile memory which has already shown impressive performances in most memory benchmarks (operation speed, memory density, retention time, ON/OFF ratio and endurance). Nevertheless, they still present a major shortcoming: their device to device memory characteristics reproducibility, especially in the case of multilevel memory cells (where more than one bit of information can be stored).
The strive to increase control over the switching phenomenon as well as to increase their reliability and reproducibility has led to a multitude of creative ideas to engineer the materials composing the MIM memristive stacks (composition, structure, additional layers or metallic nanoparticles, doping, etc.). The electrodes are a very important aspect of the final electrical memristive cell. By changing the nature of the electrodes, different scenarios can occur: an ohmic or a Schottky contact can be created solely by the change in work function of the metal. If the “sandwiched” material is an oxide (either insulating or, in some cases, semiconducting), the electrode can undergo an oxidation process when the device is functioning, i.e. when an external bias is applied to one of the electrodes. The creation of this new interfacial metal-oxide layer will also influence the electrical characteristics of the device.
This presentation is focused on how the electrical response of a M/La2NiO4/M’ heterostructure is affected when changing the electrode materials (M and M’ can be different or the same electrodes). Here the sandwiched material is a well-documented mixed ionic-electronic conductor (MIEC). This aspect is of importance since the drift of oxygen has been shown to play a major role in the switching mechanisms of oxide-based Valence-change memories and interface-type ReRAM devices.
Highly-oriented La2NiO4 was grown in the form of thin films using Metal-Organic Chemical Vapor Depostion (MOCVD) on LaAlO3 and SrTiO3 single crystals. The metallic electrodes were deposited by standard lithography process using e-beam evaporation. The structural and microstructural characterization of the samples under different deposition conditions will be presented, and special emphasis will be given to the electrical characterization and the conduction mechanisms leading to the observed I(V) characteristics for each pair of electrode materials.
10:00 AM - ED7.8.03
Structural Properties of Cerium Dioxide Film Prepared by Atomic Layer Deposition on TiN and Si Substrates
Silvia Vangelista 1 , Rossella Piagge 2 , Satu Ek 3 , Tiina Sarnet 3 , Gabriella Ghidini 2 , Alessio Lamperti 1
1 , IMM-CNR, MDM unit, Agrate Brianza Italy, 2 , STMicroelectronics, Agrate Brianza (MB) Italy, 3 , Picosun Oy, Espoo Finland
Show AbstractIn the last years, CeO2 based materials have attracted much attention for their applications in many application areas such as catalysis, hydrogen production, gas sensing and electrodes in fuel cells. In microelectronics, CeO2 has been considered as high κ-gate oxide material due to its moderate band gap (3–3.6 eV), high dielectric constant (κ: 23) and high refractive index (n: 2.2–2.8). For many applications CeO2 needs to be grown on metallic substrates, but few studies exist on CeO2 deposited on metals and mainly at ultra-low thickness (below 2 nm).
CeO2 has been reported to be grown by several techniques (e-beam, physical vapor deposition, RF-magnetron sputtering, chemical vapor deposition). However, when highly stoichiometric oxide thin films with conformality and uniformity on large areas are required, atomic layer deposition (ALD) is the suitable technique.
In this work, we aim to a deep understanding of the structural properties of ALD grown CeO2 deposited either on Si substrate or on metals (or electrically behaving as metals, i.e. TiN), concentrating ourselves on the differences between the film properties when performed on such substrates. Moreover, we investigated the effects of temperature and atmosphere in post-deposition annealing on the CeO2 films, including crystalline structure, grain size and shape, and Ce chemical state.
The films were studied by using an ample set of techniques: X-ray reflectivity and diffraction (XRR-XRD), Time-of-Flight Secondary Ion Mass Spectrometry (ToF SIMS), Transmission Electron Microscopy (TEM), X-ray Photoelectron Spectroscopy (XPS), Spectroscopic Ellipsometry (SE) and electrical characterization (CV and IV).
CeO2 films deposited at 250°C by ALD resulted in polycrystalline cubic phase on both substrates, but with crystallographic preferential orientation along <200> direction for CeO2/Si and <111> direction for CeO2/TiN. Additionally, depending on the substrate, the CeO2 films show differences in interface roughness and concentration of Ce3+ species.
The annealing has been performed at temperatures up to 900 °C for CeO2/SiO2, while for CeO2/TiN we limited the annealing up to 600 °C, to avoid the onset of diffusive phenomena from the interface. We found out an enhancement of the diffraction signal connected to the <200> crystalline orientation of the grains in the case of silicon substrate, compared to the enhancement of the diffraction signal connected to the <111> direction for the TiN substrate, which is explained into the frame of the Mochvan–Demchishin model.
Our results indicate that the transfer of the ALD growth of CeO2 on substrates other than Si can be not trivial from the point of view of the layer structural properties; the observed differences have to be carefully evaluated in order to validate CeO2 deposition on top of metallic layers.
This work was partially supported by ECSEL-JU R2POWER300 project under grant agreement n.653933.
10:15 AM - ED7.8.04
Characterization of Low Temperature Thermal ALD BN on Si0.7Ge0.3(001)
Steven Wolf 1 , Mary Edmonds 1 , Kasra Sardashti 1 , Max Clemons 1 , Ellie Yieh 2 , Srinivas Nemani 2 , Daniel Alvarez 3 , Andrew Kummel 1
1 , University of California, San Diego, La Jolla, California, United States, 2 , Applied Materials, Santa Clara, California, United States, 3 , Rasirc, Inc, San Diego, California, United States
Show AbstractBoron nitride (BN) has several useful properties including a high thermal conductivity, high chemical stability, a relatively low dielectric constant, and a wide bandgap. Due to its advantageous properties, BN can be deposited in electrical devices as an insulating layer, such as in a MOSFET (metal-oxide-semiconductor field effect transistor), or be deposited on interconnects, such as copper, as a diffusion barrier. An interfacial layer of amorphous BN could even be deposited prior to dielectric deposition in MOSFET device architectures to prevent substrate diffusion into the high-k material, producing a device with a lower density of interfacial traps (Dit). In this study, low temperature ALD amorphous BN from N2H4 and BCl3 was performed on Si0.7Ge0.3(001) due to its high mobility and utility in strain engineering [1], and the deposited films were studied using x-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM). Al2O3/a-BN/Si0.7Ge0.3(001) MOSCAPs were fabricated for C-V and I-V characterization of defects. Previous work has shown that BN ALD with triethylborane and ammonia with H2 carrier gas occurs at 600°C-900°C with a growth rate of 0.7 Å/ cycle on sapphire and Si [2], but above this window, the process was not self limiting. George and coworkers showed that ALD with a growth rate of ~1 Å/ cycle of BN with BCl3 and NH3 on ZrO2 nanoparticles was possible at 500K, but required very large exposures [3]. By using reactive anhydrous N2H4 the plasma-less BN ALD was accomplished with lower temperatures and smaller exposures.
The Si0.7Ge0.3(001) surface underwent a hydrogen clean to remove most surface contamination prior to the deposition of 5 cycles of alternating exposures of 150 MegaL N2H4 and 150 MegaL BCl3 at a sample temperature of 350°C. To prove saturation of the ALD cycles, an additional 150 ML and additional 300 ML of BCl3 was dosed, which changed the corrected and normalized XPS B 1s signal from 5.4% to 6.2% to 6.3%. In a similar fashion, the corrected and normalized N 1s signal increased from 11.6% to 12.5% to 12.8% after additional exposures to N2H4. The virtually unchanged percentages after maximum exposures demonstrate the saturation of the half cycles. AFM of 60 cycles of BN ALD on Si0.7Ge0.3(001) and the corresponding C-V and I-V measurements indicate a uniform, pinhole-free film was deposited. Al2O3/a-BN/Si0.7Ge0.3(001) MOSCAPs resulted in lower Dit, less leakage in accumulation, and a higher device yield. In summary, low temperature thermal ALD with anhydrous N2H4 and BCl3 deposited uniform, pinhole-free films on Si0.7Ge0.3(001), as well as producing a device with better performance when incorporating a thin interfacial layer prior to high-k gate oxide.
1. Datta, S., et al. Proceedings of the 2004 Meeting. 2004. IEEE.
2. Snure, M., et al. Thin Solid Films, 2014. 571, Part 1: p. 51-55.
3. Ferguson, J., A. Weimer, and S. George. Thin Solid Films, 2002. 413(1): p. 16-25.
10:30 AM - ED7.8.05
Uniform Atomic Layer Deposition of Al2O3 on Graphene by Reversible Hydrogen Plasma Functionalization
Rene Vervuurt 1 , Bora Karasulu 1 , Marcel Verheijen 2 , Erwin Kessels 1 , Ageeth Bol 1
1 , Eindhoven University of Technology, Eindhoven Netherlands, 2 , Philips Innovation Labs, Einhoven Netherlands
Show AbstractGraphene is a promising candidate for post-silicon electronic devices, due to its exceptional electrical, mechanical an optical properties. For device integration the ability to deposit ultra-thin uniform dielectric layers on graphene is essential. Atomic layer deposition (ALD) is the preferred method to deposit such layers on graphene, due to its ability to deposit high quality and uniform materials with precise control of the layer thickness. However, the initiation of ALD growth on graphene is a challenge due to the lack of out-of-plane bonds and surface hydrophobicity. ALD growth of dielectrics on pristine graphene therefore only occurs on defect sites or grain boundaries where dangling bonds or functional groups are present.
To overcome these nucleation issues several different surface preparation techniques to initialize ALD on graphene have been explored over the years. Among them, plasma functionalization is the preferred method due to its processing ease, compatibility with silicon technology and limited amount of extra steps required. However, when O2 or N2 plasmas are used for functionalization, the sp2 backbone of graphene is damaged, deteriorating its electrical properties, such as the charge carrier mobility.
In this contribution a new method to deposit ultrathin, uniform Al2O3 layers on graphene using reversible hydrogen plasma functionalization followed by ALD is presented. We show that hydrogen plasma functionalization of graphene leads to uniform ALD of closed Al2O3 films down to 8-nm in thickness. Hall measurements and Raman spectroscopy reveal that the hydrogen plasma functionalization is reversible upon Al2O3 ALD and annealing at 400°C and improves graphene’s charge carrier mobility to 152% of its initial value. This is in contrast with the normally used oxygen plasma functionalization, which leads to a uniform 5-nm thick closed film, but is not reversible and leads to a drastic reduction of the charge carrier mobility.
Density functional theory (DFT) calculations attribute the uniform growth on both H2 and O2 plasma functionalized graphene to the high adsorption energy of Trimethylaluminum (TMA) on these surfaces. A DFT analysis of possible reaction pathways for TMA precursor adsorption on hydrogenated graphene predicts a H2 and CH4 release mechanism that cleans off the hydrogen functionalities from the graphene surface, which explains the observed reversibility of the hydrogen plasma functionalization of graphene upon Al2O3 ALD. This indicates that the functionalization of graphene by a H2 plasma is an excellent way to enable direct ALD growth of thin uniform dielectric layers on graphene without deteriorating graphene’s electrical properties
10:45 AM - ED7.8.06
Inkjet-Printed Four-Terminal Microelectromechanical Relays for 3-Dimensional Logic Applications
Seungjun Chung 1 2 , Muhammed Karim 2 , Hyuk-Jun Kwon 3 , Takhee Lee 1 , Vivek Subramanian 2
1 , Seoul National University, Seoul Korea (the Republic of), 2 EECS, University of California, Berkeley, Berkeley, California, United States, 3 Mechanical Engineering, University of California, Berkeley, Berkeley, California, United States
Show AbstractInkjet-printing is regarded as one of the most promising candidates for realization of electronic applications due to its ultra-low-cost, non-vacuum, and environment-friendly processes abilities. Recently, although printed TFTs have shown drastically improved electrical characteristics respecting to the carrier mobility and switching speed because high-performance semiconductor and gate dielectric materials have been developed, further enhancements are still needed with respect to their power-consumption, environmental stability, subthreshold swing (SS), and on/off ratio for a wide range of applications. An alternative approach that is particularly attractive for applications requiring ultra-low device leakage is the use of printed microelectromechanical (MEM) relay with movable cantilevers operated by electrostatic actuation. A semiconductor layer is not required in mechanical switching devices; therefore, extremely low on-state resistance, off-state leakage, and SS value below 1 mV/dec are normally observed without interfacial issues.
In this presentation, we will report the first demonstration of inkjet-printed 4-terminal microelectromechanical (MEM) relays and inverters with hyper-abrupt switching that exhibit excellent electrical and mechanical characteristics. This first implementation of a printed 4-terminal device is critically important, because it allows for the realization of full complementary logic functions. The floated fourth terminal (body electrode), which allows the gate switching voltage to be adjusted, is bonded to movable channel beams via a printed epoxy layer in a planar structure. The floated part can move downward together via the electrostatic force between the gate electrodes and body such that the channel can also actuate downward and touch the drain electrode. Because the body, channel, and drain electrodes are completely electrically separated, no detectable leakage or electrical interference between the electrodes is observed. The printed MEM relay exhibited an on-state resistance of only 3.48 Ω, immeasurable of off-state leakage, SS <1 mV/dec, and a stable operation over 104 cycles with a switching delay of 47 μs, and the relay inverter exhibits abrupt transitions between on/off states. The operation of the printed 4-terminal MEM relay was also verified against the results of a 3-dimensional (3D) finite element simulation. We believe that the printed 4-terminal MEM relay can be a promising device for low-cost, large-area and high-performance logic applications due to its low on-resistance, lower power capability, and usefulness for implementing complementary logic functions.
11:30 AM - ED7.8.07
Chemical Vapor Deposition of Stiochiometric TaSi2 on Si(001)
Jong Youn Choi 1 , Christopher Ahles 1 , Sang Wook Park 2 , Raymond Hung 2 , Andrew Kummel 1
1 , University of California, San Diego, La Jolla, California, United States, 2 , Applied Materials, Santa Clara, California, United States
Show AbstractTransition metal disilicides are of great interest in Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) due to their ability to tune the work function at the metal contact in the source/drain regions. Various kinds of transition metal silicides such as TiSi2, NiSi2 and WSi2 have been studied in previous decades; however, nanoscale studies of tantalum silicide (TaSi2) are relatively scarce. Previously, Lemonds et al. reported atomic layer deposition (ALD) of tantalum silicide (TaSix) on SiO2 using TaF5 and Si2H6. In this work, however, it is demonstrated that using similar reaction conditions TaSi2 can be only grown by Chemical Vapor Deposition (CVD) process on oxide-free clean Si(001). Various dosing conditions and temperatures were examined to deposit TaSix via controlled CVD process. X-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM), Cryo-Focused Ion Beam (Cryo-FIB) and Scanning Electron Microscope (SEM) have been used to investigate the chemical composition of TaSix and surface and cross section morphologies after TaSix film deposition. HF cleaned Si(001) was used for the substrate. The chemical composition was determined by XPS after CVD to be that of a stoichiometric TaSi2 and/or Ta rich silicide film formed on the Si. The key variables in forming stoichiometric TaSi2 is to minimize the oxygen contamination from the system since silicide reaction is highly sensitive to background oxygen and also to have a reliable dosing mechanism to control the amount of TaF5 using a carrier gas. It is hypothesized that true ALD does not occur on Si(001) using TaF5 and Si2H6 up to 300oC when the dosing system is well purged to eliminate trace CVD processes. AFM and cross section SEM following cryo-FIB showed that the films had ~30 nm tall TaSix particles. By controlling purging and pumping time, CVD of TaSix film can be managed to have controlled sizes of TaSix particles in the range of 4 nm.
11:45 AM - ED7.8.08
Antiferromagnetic Ordering in 25% Ca Doped Antisite-Disordered Ferromagnetic La2CoMnO6 Double Perovskite
Ramchandra Sahoo 1 , Amitabh Das 2 , Tapan Nath 1
1 , IIT Kharagpur, Kharagpur India, 2 Solid State Physics Division, Bhabha Atomic Research Centre, Mumbai, Maharashtra, India
Show AbstractMultifunctional hole-doped double perovskite oxides with a chemical formula La2-xA'xCoMnO6 (where A′=alkaline-earth (Ca, Sr, Ba, etc.)) have recently gained much attention to different research groups beacuse of fascinating structual, magnetic, electronic properties possessing intense intrinsic competition between the ferromagnetic (FM) and antiferromagnetic (AFM) insulating phases. In view of spintronics and interface device applications of perovskites, the present observation of magnetic properties in this double perovskite may have great importance. In the present work we present structural and magnetic properties of bulk La1.5Ca0.5CoMnO6 (LCCMO) double perovskite oxide and compare with its disordered parent compound La2CoMnO6 (LCMO). We have synthesized the polycrystalline double perovskite LCCMO by conventional sol-gel method. The structural properties have been carried out using neutron powder diffraction patterns (NPD) (λ= 1.2443 Å, PD2 diffractometer, Dhruva Reactor). Magnetic measurements have been carried out using a superconducting quantum interference device magnetometer (SQUID, Quantum Design, USA). The Rietveld refinement of powder NPD data using FullProf Suite software suggested a monoclinic (P21/n) crystal structure of antisite disordered LCCMO sample. An additional peak starts growing below 200 K, which corresponds to magnetic transition of LCCMO - not for any structural phase transition. These superlattice reflections are the clear indication of long-range AFM ordering in our double perovskite instead of FM ordering near 230 K of parent LCMO. Thermal evolution of dc magnetization in zero field cooled (ZFC) and field cooled warming (FCW) modes under H= 100 Oe magnetic field clearly suggests a significant FM component at 157 K. Upon cooling below 150 K, a sharp down-turn of the ZFC curve and noticeable divergence between the ZFC and FC curve at lower temperature are attributed to canted AFM. On the other hand a disordered LCMO exhibits monoclinic crystal structure with two FM transition one at 230 K due to superexchange interactions and other one at 150 K due to vibronic superexchange interactions by transition metal ions. These results of LCCMO may be useful to manipulate multi-magnetic ordering for engineering and scientific applications.
References:
1. R. C. Sahoo, S. K. Giri, D. Paladhi, A. Das, and T. K. Nath, J. Appl. Phys. 120, 033906 (2016).
2. S. Baidya and T. Saha-Dasgupta, Phys. Rev. B 84, 035131 (2011).
12:00 PM - ED7.8.09
Flexible Memristive Memory Arrays Based on Vapor-Phase Deposited Polymer Thin Film
Byung Chul Jang 1 , Hyejeong Seong 1 , Jong Yun Kim 1 , Beom Jun Koo 1 , Sung Kyu Kim 1 , Sang Yoon Yang 1 , Sung Gap Im 1 , Sung-Yool Choi 1
1 , KAIST, Daejeon Korea (the Republic of)
Show AbstractFlexible electronics have received huge attention as a breakthrough in electronics market. In particular, the development of flexible nonvolatile memory is necessary for flexible electronic systems, due to its fundamental roles of data storage, processing, and communication with external devices in electronic system. As one of the most promising flexible nonvolatile memory, memristive memory has attracted much attention due to its outstanding characteristics. The filament type memristive memory based on polymer thin films has many advantages for flexible nonvolatile memory application owing to its low cost, simple structure, high scalability, low operating voltage, and flexibility. However, memristive memory based on polymer thin films has serious drawbacks regarding the uniformity, long-term stability, and incompatibility with photolithography, resulting from the solution-based synthesis of polymer thin film. Here, we present a poly(1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3)-based memristive memory arrays fabricated via the solvent-free technique called initiated chemical vapor deposition (iCVD) on plastic substrate for flexible memory application. The pV3D3-memristor arrays can be fabricated by a conventional photolithography process on flexible substrate due to outstanding chemical stability of pV3D3 films, and showed unipolar resistive switching behavior with an on/off ratio of over 107, cycling endurance over 105 cycles, stable retention time for 105 s, and excellent mechanical stability. Furthermore, pV3D3-memristor showed good uniformity in terms of device-to-device distribution, resulting from highly uniform and pure pV3D3 films via solvent-free process. By investigating the temperature dependent and cell-area dependent switching characteristics, and through conductive atomic force microscopy (C-AFM), we demonstrated that the switching mechanism of pV3D3-memristor is based on the reversible formation and rupture of Cu filaments. The pV3D3-memristor arrays fabricated on flexible substrate not only provides an feasible solution to the bottleneck of existing solution-processed polymer-based memristor, but also shows potential for flexible nonvolatile memory applications.
12:15 PM - ED7.8.10
Resistive Switching of Nanoengineered LaMnO3±d Thin Films for ReRAM Applications
Dolors Pla Asesio 1 , Klaasjan Maas 1 , Sarunas Bagdzevicius 1 , Herve Roussel 1 , Odette Chaix 1 , Xavier Mescot 2 , Quentin Rafhay 2 , Michel Boudard 1 , Monica Burriel 1 , Carmen Jimenez 1
1 , Laboratoire des Matériaux et du Génie Physique (LMGP), Grenoble France, 2 , Institut de Microélectronique Electromagnétisme et Photonique and LAboratoire d'Hyperfréquences et de Caractérisation, Grenoble France
Show AbstractManganite perovskites are among the most promising materials for the development of new resistive random access memories (ReRAMs) with multiple-bits-per-cell [1-3]. However, from a material point of view, an in-depth comprehension of the resistive switching (RS) mechanisms and their correlation with the nanochemistry and nanostructure of the manganite films are required. Besides, in terms of device applicability, their integration in mainstream semiconductor technology bounded to the microelectronics industry remains unsolved due to the high deposition temperatures required for obtaining crystalline films.
Epitaxial and polycrystalline thin films of La1-XMn1-YO3±d (LMO) grown on single crystalline substrates (i.e. SrTiO3, Nb-doped SrTiO3, and LaAlO3) and on Si were synthetized by pulsed injection metalorganic chemical vapor deposition. The LMO nanostructure (i.e. crystallinity, strain, morphology and grain size) and composition (i.e. La/Mn ratio and oxygen content) were controlled at the nanoscale and studied combining scanning electron microscopy, electron probe micro-analyzer, x-ray photoelectron spectroscopy, inductively coupled plasma mass spectrometry, high resolution transmission electron microscopy, x-ray diffraction and in-situ Raman measurements under temperature. Moreover, a strategy to coordinate the growth of crystalline LMO films with a thermo-mechanically stable platinum metal layer implemented on a Si-based device was proposed, obtaining a metal (top electrode)/LMO/Pt (bottom electrode)/TiO2/SiO2/Si device. Cyclic voltammetry measurements were performed (from ±0.5 to ± 5 V with sweeps rates 10-100 mV/s) using Ag, Au and Pt as top electrodes. LMO films with a hyperstoichiometric oxygen content, a coexistence of orthorhombic and rhombohedral phases, and a cationic disproportion showed the best RS behavior with a programming window of up to several orders of magnitude. The switching phenomena could be related to a deviation from the La/Mn ratio stoichiometry and the presence of mixed Mn oxidation states. A segregation of the Mn cations creating/destroying a preferential charge carrier pathway under bias might lead to a ferromagnetic/antiferromagnetic behavior with enhanced/diminished conductivity, defining the high and low resistance states.
[1] Moreno, C. et al. Nano Lett. 2010, 10, 3828-3835
[2] Sawa, A. Mater; Today 2008, 11, 28-36
[3] Pan, F. et al. Mat. Sci. Eng. R 2014, 83, 1–59.
12:30 PM - ED7.8.11
Interface-Type Resistive Switching in Epitaxial GdBaCo2O5+δ Thin Film Heterostructures
Sarunas Bagdzevicius 1 , Klaasjan Maas 1 , Dolors Pla Asesio 1 , Raquel Rodrígues-Lamas 1 2 , Carmen Jimenez 1 , Michel Boudard 1 , Jose Santiso 2 , Monica Burriel 1
1 , Univ Grenoble Alpes, CNRS, LMGP, Grenoble France, 2 , Institut Catala de Nanociencia i Nanotecnologia (ICN2), Barcelona Spain
Show AbstractGdBaCo2O5+δ double perovskite (GBCO for short) was established as a fascinating material with a rich phase diagram (magnetism with ferromagnetic, antiferromagnetic and re-entrant paramagnetic phases, metal-insulator transition, colossal magnetoresistance phenomenon, spin state transitions [1]). A very appealing feature is that it is possible to continuously dope the CoO2 planes with electrons or holes changing only the O content (maintaining the same Gd, Ba and Co stoichiometry). GBCO is one of the strongly correlated systems – homogeneous distribution of doped carriers (electrons or holes) that becomes unstable at low temperatures leading to a nanoscopic phase separation, showing the coexistence of insulating and metallic states at low temperature [1].
Recently GBCO was re-examined for its potential application as mixed conducting oxide for intermediate temperature Solid Oxide Fuel Cell cathodes due to the high electronic and ionic conductivities observed. 18O tracer experiments [2] showed preferential crystallographic direction for the ionic conductivity (mainly through oxygen vacancies), giving an additional degree of freedom (anisotropic ionic conduction) for engineering functional devices.
In devices e.g. memristors GBCO would be in the contact with metals or semiconductors. Oxygen diffusion and semiconducting transport in GBCO allows the creation of barriers for conduction at the interfaces with metal and oxide electrodes. The interplay between the created barriers, depletion regions and redox mediated change in oxygen stoichiometry can give rise to new phenomena e.g. Mott transition in ultrathin LaNiO3 [3] or stoichiometry controlled metal-insulator transition in GBCO [1]. Combined effect leads to non-volatile change in device resistance, so called resistance switching (RS). Continuous change of the device resistance usually observed in interface-type RS devices paves the way for its use in future memristive applications, such as neuromorphic computing.
Taking into account the combined metal-insulator transition obtained by materials interfaces engineering at the nanoscale we have examined GBCO heterostructures formed with top metal (Pt, Ag, Al, Ti) and bottom epitaxial conducting oxide (LaNiO3, SrRuO3) electrodes for its potential application in resistive switching memories. In this work we will show the structural and electrical characterization results of GBCO epitaxial thin films deposited by PLD on single crystal substrates and apply a few possible scenarios to elucidate the observed continuous change in the device resistance (possible multilevel RS) and bipolar RS with long retention time (3.5*106 s).
[1] A. A. Taskin, A. N. Lavrov, and Y. Ando, Phys. Rev. B, 71, 13, 134414 (2005).
[2] J. Zapata, M. Burriel, P. García, J. A. Kilner, and J. Santiso, J. Mater. Chem. A, 1, 25, 7408 (2013).
[3] D. Misra and T. K. Kundu, Eur. Phys. J. B, 89, 1, 4 (2016).