Martin Frank, IBM T.J. Watson Research Center
Hyunsang Hwang, Pohang University of Science and Technology
Paul McIntyre, Stanford University
John Robertson, Cambridge University
Symposium Support Air Liquide
Applied Materials, Inc.
Lam Research Corporation
ULVAC Technologies, Inc.
AA2: GaN-Based Devices
Tuesday PM, April 07, 2015
Moscone West, Level 2, Room 2005
2:30 AM - AA2.01
A Comparative Study of Al2O3, HfO2 and AlN on AlGaN/GaN HEMT Heterostructures
Xiaoye Qin 1 Angelica Azcatl 1 Hui Zhu 1 Robert M. Wallace 1
1The University of Texas at Dallas Richardson United StatesShow Abstract
AlGaN/GaN high electron mobility transistors (HEMTs) are ideal for high-frequency and high power devices. One main and urgent issue that degrades this device is a large leakage current. To address this issue, metal insulator semiconductor HEMTs with high-k dielectrics is favorite method. Among a great number of insulator materials, atomic layer deposited (ALD) Al2O3, HfO2 and plasma enhanced atomic layer deposited (PEALD) AlN are attractive. However, there are still some challenges for AlGaN/GaN due to its unique properties. For example, the insertion of the insulation layer would shift the threshold voltage to negative values, which is not desirable for enhancement mode AlGaN/GaN HEMT. The interface state density (Dit) occupying levels below the conduction band edge at the oxide/AlGaN interface, which degrades the device stability, is another concern. Whether ALD of Al2O3, HfO2 and PEALD AlN could passivate the AlGaN surface is still not clear.
In this work, the ALD-Al2O3/AlGaN, ALD-HfO2/AlGaN and PEALD-AlN/AlGaN interfaces were systematically investigated using in situ XPS, and ex situ electrical characterization. Band alignments are also proposed from high resolution XPS measurements. Initial results have shown that the Al2O3 and HfO2 dielectric layers reduce the leakage current as expected with respect to metal/AlGaN/GaN Schottky. However, a high density of interface states and positive charges are detected, which originate from the AlGaN interface. The passivation effect of Al2O3, HfO2 and AlN on AlGaN will be presented.
This work is supported by the AFOSR Asian Office of Aerospace Research and Development (AOARD) under Grant No. FA2386-14-1-4069.
2:45 AM - AA2.02
Oxide Charge Engineering Approaches to Produce Enhanced Mode Al2O3/GaN Device Operation
Muhammad Adi Negara 1 Rathnait Long 1 Dmitry Zhernokletov 1 Baylor Triplett 1 Paul C. McIntyre 1
1Stanford University Stanford United StatesShow Abstract
In recent years, significant research efforts have focused on developing enhancement mode (E-mode) GaN-based devices fueled by many potential applications. Simpler power amplifier circuits using a single polarity voltage supply and increased safety using a normally-off device can be achieved using E-mode devices leading to lower cost and an improvement of system reliability. Using the combination of E-mode and depletion mode (D-mode) devices in direct coupled logic open up also new applications for nitride semiconductors. To realize normally-off operation of GaN transistors, several approaches have been reported in the past including recessed gate structures , p-type gate injection , fluorine plasma treatment , surface channel GaN , thermally oxidized gate insulator  and oxide charge engineering . In this project, we report two approaches to modify the threshold voltage (Vth)/flat band voltage (Vfb) of GaN based devices. We present the application of fixed and oxide charges after TiO2-alloying and annealing processes of Al2O3 on GaN and AlGaN/GaN based devices. As reported in , the use of AlxTiyOz mixtures on p-Si device can shift the flat band voltage to more positive values after annealing due to the increasing number of negative fixed charges. In a second approach, we extend the previous research in  on fluorine plasma treatment by implanting fluorine ions directly into Al2O3 gate dielectrics to modify their fixed charge values. The effectiveness of these approaches for fixed charge modification of ALD-grown Al2O3 will be presented.
 W. B. Lanford, et al., Electron. Lett. 41, no. 7, 449 (2005).
 Y. Uemoto, et al., IEEE Trans. Elect. Dev. 54, no. 12, 3393 (2007).
 Zhang et al., Appl. Phys. Lett. 103, 033524 (2013).
 W. Huang, et al., IEEE Elect. Dev. Lett. 27, no. 10, 796 (2006).
 K. Inoue et al., Elect. Dev. Meet., IEDM Technical Digest. International, pp. 25.2.1 (2001).
 B. Lu, et al., in Proc. Int. Workshop Nitride Semicond. Abstr.,536 (2008)..
 Jogi et al., J. Appl. Phys. 102, 114114 (2007).
3:00 AM - *AA2.03
The PowerGaN Project - Materials and Devices
Iain Thayne 1
1University of Glasgow Glasgow United KingdomShow Abstract
In this presentation, the current status of the PowerGaN consortium, a ~$10M UK project in the area of GaN power electronics will be reviewed. The project consortium comprises over 30 researchers in the Universities of Bristol, Cambridge, Glasgow, Liverpool, Manchester, Nottingham and Sheffield with expertise in the areas of GaN on silicon materials growth, power electronics device design, silicon compatible semiconductor process optimisation, power electronics device reliability evaluation, power device packaging and power device evaluation in realistic power switching testbeds.
The overall aim of the project is to demonstrate a diversity of GaN-based power electronic devices which are fully compatible with silicon manufacturing approaches.
The presentation will review recent developments in the optimisation of areas such as the growth of the buffer layer between the silicon substrate and the GaN device channel with emphasis on the routes to minimise buffer leakage current, imcrease breakdown voltage, and minimise device current collapse. The status of the high-k/GaN gate stack optimisation will emphasis on device threshold voltage control, gate leakage current and hysteresis minimisation will be discussed. In addition, routes to mitigiate current collapse by appropriate engineering of the surface of the drift region between the gate and drain of the transistor will be considered.
3:30 AM - AA2.04
Band Offset Engineering of Polar Oxide Wide Band Gap Semiconductors Interfaces
Vlado Lazarov 1 2 Phil J Hasnip 1 Martin Stankovski 1 Katherine Zeimer 2
1University of York York United Kingdom2Northeastern University Boston United StatesShow Abstract
Wide band gap semiconductors are of special interest for device applications that require high temperature operations, high frequency and high power density. Recent advance in polar oxide thin film growth ( e.g MgO, CaO, and Al2O3) on SiC and GaN growth has open possibilities for metal-oxide wide band gap semiconductor heterostructures with large tunable electronic properties. In this work we present experimental and theoretical study on MgO(111)/SiC(0001), and MgO(111)/GaN(111) heterostructure interfaces with focus on atomic and electronic properties. Atomic resolution transmission electron microscopy imaging reveals that molecular beam epitaxy grown MgO(111) films form atomically sharp interfaces with both SiC and GaN. In addition we demonstrate that the atomic interface structure of these interfaces can be engineered by suitable preparation of the substrate surfaces. First principle total energy calculations show that the driving force that determines atomic stacking at these interfaces is the screening of the interfacial dipole moment. The interface electronic properties are very sensitive on the atomic structure due to abrupt change of the electrostatic potential across the polar heterostructures. For example, the Mg terminated MgO(111)/SiC(0001) interface is insulating with valence- band offset of 3.5 eV, in contrast to n-doped O terminated interface that has a 1.5 eV valence-band offset. The systematic studies by density functional theory with GW corrections show that band offsets at these heterostructures can vary from ~ 1eV to ~3.7 eV as a function of the interface atomic structure. This property makes polar oxide/semiconductor heterojunctions very attractive for device applications.
3:45 AM - AA2.05
Electronic States of Plasma-Enhanced Atomic Layer Deposited SiO2 on GaN
Brianna Eller 1 Jialing Yang 1 Robert J. Nemanich 1
1Arizona State University Tempe United StatesShow Abstract
Silicon dioxide is a stable dielectric with large band offsets that may be suitable for wide bandgap semiconductors. This research is focused on the band offsets and band bending for PEALD grown SiO2 on in situ cleaned GaN. We have investigated the ALD deposition of low-temperature SiO2 using tris(dimethylamino)silane (TDMAS) and oxygen plasma on GaN substrates. Samples were cleaned ex-situ with acetone, methanol, and NH4OH to increase the number of OH groups on the surface and increase nucleation during ALD deposition. PEALD was then used to deposit thin films using varied parameters to ensure self-saturating deposition. Thin film thicknesses, compositions, and band offsets were then determined with in-situ x-ray photoelectron spectroscopy (XPS). Results show the growth rate for TDMAS and oxygen plasma process increases as temperature decreases—at least within the ALD regime. The growth rate is higher at 550 °C, which is likely the result of thermal decomposition of TDMAS. In addition, the high-temperature films demonstrate small concentrations of contamination from the molybdenum sample holder. Results demonstrated temperature does not greatly affect the stoichiometry of the films. In addition, a more detailed analysis of the films shows increasing the deposition temperature resulted in the increase of a secondary O1s peak; however, this peak was not present for thick films, where the substrate was undetectable. This secondary peak suggests the high temperature may oxidize the substrates. This effect may also explain the variation in the valence band offsets (VBO) of the materials deposited at different temperatures which varies by nearly 0.5 eV, where the measurement technique does not account for the potential drop across the interfacial Ga-O layer. The next stage of this work will employ electrical measurements to ascertain the quality of this interface on SiO2/Si and ascertain the effects of potential plasma damage.
This research is supported by the Office of Naval Research through the DEFINE MURI program, N00014-10-1-0937.
4:30 AM - AA2.06
Pyroelectric Control of Rashba Spin-Split States and Spin-Relaxation Times of a GaN/InN/GaN Quantum Spin Hall Transistor
Parijat Sengupta 1
1University of Wisconsin Madison Madison United StatesShow Abstract
Strong spin-orbit coupling leading to band inversion in bulk is necessary for creation of topological insulator states (TI) or quantum spin Hall systems. Electric field can also be used to invert the band structure. Nitrides in wurtzite phase possess an internal electric field due to spontaneous and piezoelectric polarization which is sufficient to invert the band-ordering of a narrow-gap InN. A TI state exists in a thin-film of InN sandwiched between GaN layers . InN is specifically chosen as quantum well material because it is a low band-gap material and has considerable lattice mismatch with GaN giving a pronounced piezoelectric effect in addition to spontaneous polarization. For a certain quantum well thickness, inversion of bands happen at a threshold value of the polarization field. Polarization fields in nitrides can be controlled by selecting a facet orientation of the quantum well layer determined by the dominant polarization mechanism.
The dispersion of GaN/InN/GaN quantum well heterostructure is computed with a 6-band k.p Hamiltonian. The 6-band Hamiltonian is used in conjunction with the electrostatic and strain effects that are present in the GaN/InN/GaN heterostructure. The strain Hamiltonian is computed using the Bir-Pikus deformation potential theory. In a normal ordered wurtzite material, the Γ1 symmetry point is energetically placed over Γ6 . The band structure of the GaN/InN/GaN heterostructure due to the strong internal electric field has this sequence reversed demonstrating the inverted band profile. Band-gap closing edge states (degenerate Dirac cones) are therefore found when a nano-ribbon is constructed from the inverted quantum well. The nano-ribbon is confined along the y and z-axes and periodic along x-axis. The edge states of this ribbon are also determined to be spin-polarized.
Under the influence of an external electric field (1.5 MV/cm), the two degenerate Dirac cones split in energy and separate along the energy axis. Similarly when an external magnetic field is applied along the z-axis, the two Dirac cones shift along the x-axis. The B-field therefore acts like a horizontal gate and allows the possibility of a spin-tunnel device between the two shifted states with opposite spin polarization.
Further, at a finite k-vector, the Rashba-induced spin-splitting on the surface of this heterostructure is computed. The splitting under a first-order approximation is independent of k-vector  and corresponds to the polarization field&’s contribution to the Rashba coefficient. Finally, the interplay of mechanisms that control spin-relaxation times is used to design a spin transistor. An enhancement in the lifetime of the spin-polarized states under certain growth conditions is observed due to mutual cancelation the Rashba and Dresselhaus splitting  to suppress spin-relaxation.
 M.Miao et al., Phys. Rev. Lett. 109, 186803
 V. Litvinov, Appl. Phys. Lett. 89, 222108
 Q. Zhang et al., Appl. Phys. Lett. 95, 031902
AA3: Transition Metal Dichalcogenides I
Tuesday PM, April 07, 2015
Moscone West, Level 2, Room 2005
4:45 AM - *AA3.01
Contact Engineering, Chemical Doping and Heterostructures of Layered Chalcogenides
Ali Javey 1
1UC Berkeley Berkeley United StatesShow Abstract
Two-dimensional (2-D) semiconductors exhibit excellent device characteristics, as well as novel optical, electrical, and optoelectronic characteristics. In this talk, I will present our recent advancements in contact engineering, surface charge transfer doping, and heterostructure devices of layered chalcogenides. Forming Ohmic contacts for both electrons and holes is necessary in order to exploit the performance limits of enabled devices while shedding light on the intrinsic properties of a material system. In this regard, we have developed different strategies, including the use of surface charge transfer doping at the contacts to thin down the Schottky barriers, thereby, enabling efficient injection of electrons or holes into MoS2 and WSe2 mono- and multi-layers. Additionally, I will discuss the use of layered chalcogenides for various heterostructure device applications, exploiting charge transfer at the van der Waals heterointerfaces.
5:15 AM - AA3.02
Analysis of Schottky Barriers, Contacts and Doping Properties of MoS2 and Other Transition Metal Dichalcogenides
Yuzheng Guo 1 John Robertson 1
1University of Cambridge Cambridge United KingdomShow Abstract
The layered transition metal dichalcogenides (TMDs) such as MoS2 are being extensively studied as possible channel materials for ‘beyond-Roadmap devices&’ . However, their contact resistances are often rather large, and it is not clear what controls contact resistances and how to improve them. The standard model of contact behavior would be the metal induced gap state (MIGS) model of Schottky barrier heights (SBHs) [2,3]. However, for top contacts on layered materials, it might be argued that that the van de Waals bonding causes the metal to semiconductor distance to be too large, so that the MIGS model is less relevant, and that the SBH becomes ‘unpinned&’ as in one previous analysis . Here we calculate the SBH of for the top and edge contacts on various TMDs, both bulk and monolayer, covering metals with a wide range of work functions from Sc to MoO3, using a supercell (slab) model and density functional theory. We extract the SBH in each case by using the Mo 4s core level as a reference energy to identify the valence band top in cases of strong hybridization with the metal - the theory analogue of Kraut&’s method. We find that the Schottky barrier pinning factor S is of order S=0.34 and 0.28 for bulk and monolayer MoS2, respectively. This is consistent with the stronger pinning of S= 0.1 found experimentally , and not with the weakly pinned S=0.7 found by Gong . We then find that S follows the standard dependence on optical dielectric constant found for 3 dimensional semiconductors found many years ago within the MIGS model by Monch . We note that old SBH data for layered GaS, GaSe and GaTe  also follow the MIGS model. Thus, TMD contacts do follow a pinned MIGS model, despite van de Waals gaps. This might lead to larger SBHs in some cases. We find that substitutional doping can be used to lower depletion lengths and thereby reduce contact resistances in some cases.
1. S. Das, H. Y. Chen, A. V. Penumatcha, and J. Appenzeller, NanoLett 13, 100 (2013)
2.W Mönch, Phys Rev Lett 58 1260 (1987);
3. J Robertson, J Vac Sci Technol B 18 1785 (2000)
4. C Gong, L Colombo, R M. Wallace, K J Cho,Nano Lett., 14, 1714 (2014)
5. S Kurtin, C A Mead, J Phys Chem Solids 30 2007 (1969)
5:30 AM - AA3.03
The Doping Effect on Electronic Structure of MoS2: From Monolayer to Few-Layer
Chenxi Zhang 3 Cheng Gong 1 Weihua Wang 2 Bin Shan 4 Robert M. Wallace 3 Kyeongjae Cho 3
1UC Berkeley Richardson United States2Univ of Texas-Dallas Richardson United States3University of Texas at Dallas Richardson United States4HuaZhong University of Science and Technology Wuhan ChinaShow Abstract
Recently, transition metal dichalcogenides (TMDs) have stimulated much interest because of their two-dimensional structures and sizable band gaps for potential applications in electronic devices2. Among all TMDs, MoS2 a promising candidate with thickness-dependent band gaps: 1.8 eV for monolayer to 1.2 eV for bulk 1. As a major strategy for modulating the properties of semiconductors, doping on monolayer MoS2 has been widely studied including the S vacancies3, alkali adsorption, halogen, nitrogen group elements substitution and molecular adsorption doping5,6,7. Some doping have been applied to experiments and device fabrications8, 9. Regarding doping in multilayer MoS2, there are only a few investigations in the literature. As doping will usually cause the effect of scattering which will decrease the mobility of electrons, it is important to investigate the effect of doping in multilayer MoS2.
In this work, the first-principle calculations are adopted to investigate the doping effect on the electronic structure of monolayer and multilayer MoS2 by substitutional doping at S site with halogen group (F, Cl, Br, I) and nitrogen group (N, P, As, Sb) species. It is found that halogen doping causes an n-type doping and nitrogen doping causes a p-type doping of MoS2. In the multilayer case the energy bands of the doped layer are shifted with respect to the undoped layer, resulting in the decoupling between layers. These results are interesting for TMD electronics, optoelectronics, and catalyst applications. Furthermore, in order to know the energetic stability, formation energy is also calculated and for the charged case there is an artificial electrostatic interaction between image charges which will cause inaccurate formation energy. Gaussian model charge and the scaling scheme are used to eliminate this effect.
This work was supported in part by the Center for Low Energy Systems Technology (LEAST), one of six centers of STARnet, a Semiconductor Research Corporation program sponsored by MARCO and DARPA.
 Kuc, A., N. Zibouche, and T. Heine, Phys. Rev. B, 83(24), 2011, 245213.
 Radisavljevic, Branimir, et al., Nature nanotech. 6(3), 2011, 147-150.
 Komsa, Hannu-Pekka, et al., Phys. Rev.Lett., 109(3), 2012, 035503.
 Dolui, Kapildeb, et al., Phys. Rev. B 88(7), 2013,075420.
 Zhao, Peida, et al., ACS nano (2014) DOI: 10.1021/nn5047844
 Mouri, Shinichiro, et al., Nano letters 13, no. 12 (2013): 5944-5948
 Choi, Min Sup, et al., ACS nano 8, no. 9 (2014): 9332-9340.
 Yang, Lingming, Kausik Majumdar, Han Liu et al., Nano letters (2014) DOI: 10.1021/nl502603d.
5:45 AM - AA3.04
Structural Semiconducting-to-Metallic Phase Transition in Monolayer Transition Metal Dichalcogenides Induced by Electrostatic Gating
Yao Li 1 Karel-Alexander Duerloo 1 Kerry Wauson 2 Evan J. Reed 1
1Stanford University Stanford United States2New Mexico State University Las Cruces United StatesShow Abstract
Dynamic electrical control of conductivity in two-dimensional (2D) materials is one of the most promising schemes for realizing energy-efficient electronic devices. Monolayer transition metal dichalcogenides (TMDs) are 2D materials that can exist in multiple crystal structures, each of different electrical conductivity. Using density functional approaches, we discover that a structural semiconducting-to-metallic phase transition in some monolayer TMDs can be driven by electrical stimuli, including change of charge density and bias voltage. We find that a bias voltage approximately 0.5~1 V can trigger the phase transition in MoTe2, while a larger voltage is required for the transition in other monolayer TMDs. The threshold bias voltage is strongly influenced by the substrate on which the monolayer is placed. Carefully choosing the substrate could greatly reduce the threshold bias voltage for the phase transition, and therefore consume much less energy, suggesting potential applications in electronics with very high energy efficiency. The dynamic control of this semiconducting-to-metallic phase transition can be achieved utilizing standard electronic devices like the electrostatic gating employed in a field-effect transistor. We have also calculated the phase boundary of a reported metallic-to-metallic phase transition in TaSe2 to compare with earlier STM experimental results and reasonable agreement is observed. Our findings open up the possibility of manufacturing ultrathin flexible two-dimensional phase change electronic devices with potential for higher energy efficiency than conventional electronic devices.
AA1: III-V Channels
Tuesday AM, April 07, 2015
Moscone West, Level 2, Room 2005
9:00 AM - AA1.01
Group III-Sb Metamorphic Buffer on Si for p-Channel all-III-V CMOS: Electrical Properties, Growth and Surface Defects
Shun Sasaki 1 2 Shailesh Madisetti 1 Vadim Tokranov 1 Michael Yakimov 1 Makoto Hirayama 1 Steven Bentley 3 Ajey P Jacob 3 Serge Oktyabrsky 1
1SUNY College of Nanoscale Science and Engineering Albany United States2SUMCO Corporation Tokyo Japan3Globalfoundries at Albany NanoTech Albany United StatesShow Abstract
Group III-Sb compound semiconductor is a promising material family for future transistors owing to their superior hole and electron transport properties for future CMOS and large controllable band offsets for high-performance TFETs. The heteroepitaxial growth of GaSb on Si substrate has significant advantage for volume fabrication of III-V ICs. High lattice mismatch between III-Sb&’s and Si results in 3D nucleation that is usually mitigated by incorporation of metamorphic nucleation layer (NL) with low adatom mobility, such as AlSb. We studied NL coverage rate and growth morphology of the AlSb NL grown by Migration-Enhanced molecular-beam Epitaxy (MEE) using in-situ Auger electron spectroscopy and AFM. The coverage kinetics was analyzed with Avrami&’s approach that allowed for accurate determination of nucleation density and evolution of the 3D islands. Effect of AlSb NL growth parameters and surface morphology on mobility and hole density in strained InGaSb quantum wells was studied. The optimum growth temperature of 300 0C is found for AlSb NL, resulting in room temperature Hall mobility of 660 cm2/V s at 3x1011 cm2 sheet hole density in the strained InGaSb QW p-channel. Using various designs of metamorphic superlattice buffers, thick GaSb layers were grown on Si(001) ,60 to  miscut Si(001), SOI (001) and GaAs (001) substrates by molecular beam epitaxy. Buffer design controls the defect density in GaSb that affects the electrical properties of the layers. Acceptor states related to the defects are quantified using differential Hall measurements in undoped progressively etched structures and TEM/AFM imaging. Optimized buffers allow to reduce defect density below 108 cm-2 that results in ~1x1017 cm-3 concentration of defect-related acceptors. The effect of growth-related defects (threading dislocations and microtwins) on hole concentration and mobility in strained InGaSb QWs is observed and quantified. The result on strained InGaSb p-MOSFETs grown on Al(Ga)Sb metamorphic buffers are summarized.
AA4: Poster Session
Tuesday PM, April 07, 2015
Marriott Marquis, Yerba Buena Level, Salon 7/8/9
9:00 AM - AA4.01
Investigation of Ferroelectric Polymer Langmuir Film Properties
Timothy J Reece 1 Wyatt Behn 1
1University of Nebraska at Kearney Kearney United StatesShow Abstract
Thin films of Polyvinylidene Fluoride (PVDF) copolymers have been incorporated within ferroelectric field effect transistors, all organic thin film transistor devices (OTFTs), piezoelectric actuators, and recently proposed as the ferroelectric layer in a promising multiferroic tunnel junction. The properties of most of these devices would benefit from reduced thickness and better thickness control of the ferroelectric layer during device processing.
A proven means of making ultrathin films of the PVDF copolymer is the Langmuir-Blodgett (LB) technique. This technique involves dissolving the polymer in a volatile solvent which is then dispersed dropwise onto a purified water subphase, leaving an ultrathin layer of the copolymer on the water surface. The ability to control the thickness on the molecular level is the most prominent feature of this technique.
In some early studies, the thickness was found to be about 5 Angstroms, or roughly the same thickness as the intermolecular spacing of the all-trans β phase for the ferroelectric polymers. Later studies have led to the fabrication of films composed of thicker transfer steps: ~ 1.8 nm per deposition. The discrepancy is likely explained by the nature of the VDF molecule: it is not an amphiphile.
In this study, we further investigate the properties of Langmuir films of ferroelectric copolymers using Brewster Angle Microscopy and discuss the observation of a film phase transition based on abrupt changes observed in the compressibility of the films. The main goal of this project is to discover the extent to which the device properties (like thickness) of PVDF films can be modified through processing conditions.
1. J. P. Velev, J. M. Lopez-Encarnacion, J. D. Burton, and E. Y. Tsymbal, “Multiferroic tunnel junctions with poly(vinylidene fluoride),” Phys. Rev. B, vol. 85, 125103 (2012).
2. A. V. Bune, V. M. Fridkin, S. Ducharme, L. M. Blinov, and S. P. Palto, “Two-dimensional ferroelectric films,” Nature (London), vol. 391, pp. 874-877, Feb. 1998.
3. M. Bai, A. V. Sorokin, D. W. Thompson, M. Poulsen, S. Ducharme, C. M. Herzinger, S. Palto, V. M. Fridkin, S. G. Yudin, V. E. Savchenko, and L. K. Gribova, “Determination of optical dispersion in ferroelectric vinylidene fluoride (70%)/trifluoroethylene (30%) copolymer langmuir-blodgett films,” J. Appl. Phys., vol. 95, no. 7, pp. 3372-3377, Apr. 2004.
9:00 AM - AA4.02
Effects of Heavy in-situ Phosphorus Doping on Si by Using Ultra-High Vacuum Chemical Vapor Deposition
Minhyeong Lee 1 Sangmo Koo 1 Eunjung Ko 1 Hyunchul Jang 1 Dae-Hong Ko 1
1Yonsei University Seoul Korea (the Republic of)Show Abstract
By reaching the limit of the scaling down, there are many attempts to overcome the physical problems. Among them, strain engineering has been used widely to enhance mobility of carriers effectively with doping process. However, in case of highly doping, it is known that several problems such as surface segregation, interface defects happen. To reduce these side effects, it is important to analyze the facet grown within epitaxial layer. In the study, after detecting (111) oriented stacking faults within the epitaxial layers, we attempted to find the critical moment that the defects are generated. And we investigated the optimized condition to minimize the generation of the defects.
In-situ P-doped epitaxial layers were grown by using ultra-high vacuum chemical vapor deposition (UHV-CVD) on the blanket bare and patterned Si wafers. The source gases are disilane (Si2H6) and phosphine (PH3, 1% in H2). The analysis of the microstructure and defects was conducted by high resolution transmission electron microscopy (HR-TEM), and the strain within the epitaxial layers was measured by high resolution x-ray diffraction (HR-XRD). The phosphorus concentrations were measured in secondary ion mass spectroscopy (SIMS) depth profile experiments.
9:00 AM - AA4.03
Computational Aspects of Molecular Spintronics
Mariana Hildebrand 1 Ariadna Blanca Romero 1 Michael Inkpen 1 Tim Albrecht 1 Nicholas Harrison 1
1Imperial College London United KingdomShow Abstract
The area of molecular spintronics became a subject of rising interest during the last few decades because it has the potential for devices in which information is stored and manipulated at the scale of a single molecule. In this work, electronic properties of different ferrocene containing cyclic molecules are studied within the Density Functional Theory (DFT) formalism as implemented in the Quantum espresso  and Turbomole  codes. Furthermore, trends for electron transport mechanisms of these molecules within molecular junctions shall be predicted theoretically with the use of maximally localised Wannier functions and the Landauer formalism. The motivation for this work is based on the experimental research of Tim Albrecht et al.  who examine molecular junctions by carrying out Scanning Tunnelling Microscopy (STM) to obtain single molecule conductance spectra.
 W. Haiss, T. Albrecht, H. van Zalinge, J. Phys. Chem., 111(24), 6703-6712, 2007
9:00 AM - AA4.04
Understanding Selectivity on Germanium/SiO2 Chemical Mechanical Planarization through Design of Experiments
Ayse Karagoz 2 James Mal 3 Bahar G. Basim 1
1Ozyegin Univ Istanbul Turkey2Ozyegin University Istanbul Turkey3Oregon State University Corvallis United StatesShow Abstract
The continuous trend of achieving more complex microelectronics with smaller nodes yet larger wafer sizes in microelectronics manufacturing lead to aggressive development requirements for chemical mechanical planarization (CMP) process. Reactive additives such as surfactants, oxidizers, and pH regulators are being used for the CMP slurry formulation to manipulate CMP selectivity by changing the chemical and physical properties of the first few atomic layers on the wafer surfaces. Most frequently the utilization of surface-active agents became a common practice to achieve selectivity as well as provide slurry particle stability for defectivity control [1-3].
There is an increased focus on germanium (Ge) and III-V semiconductors as potential channel materials for sub-22 nm devices, since both electron and hole mobilities in Ge are higher than those in silicon (Si). CMP is an enabler for integration of these materials into future device applications.
In this study, we implemented a design of experiment (DOE) methodology in order to understand the optimized CMP slurry parameters such as optimal concentration of surface active agent (sodium dodecyl sulfate-SDS), concentration of abrasive particles and pH from the viewpoint of high removal rate and selectivity while maintaining a defect free surface finish. The responses examined were particle size distribution (slurry stability), zeta potential, material removal rate (MRR) and the surface defectivity as a function of the selected design variables. The impact of fumed silica particle loadings, oxidizer (H2O2) concentration, SDS surfactant concentration and pH were analyzed on Ge/silica selectivity through material removal rate (MRR) surface roughness and defectivity analyses.
1. Basim G.B., Engineered Particulate Systems for Chemical Mechanical Planarization, Lambert Academic Publishing, ISBN 978-3-8433- 6346-4, 2011.
2. Vakarelski I. U., Brown, S.C, Basim G.B, Rabinovich, Y. I., and Moudgil B.M., "Tailoring Silica Nanotribology for CMP Slurry Optimization: Ca2+ Cation Competition in C12TAB Mediated Lubrication", ACS Applied Materials & Interfaces, Vol. 2, No 4, pp. 1228-1235, 2010.
3. Rosen, M. J., Surfactants and Interfacial Phenomena, ,Wiley, New York, p. 337, 1989.
9:00 AM - AA4.05
CMOS-Compatible Polymer-Based Memory Structures on Copper Substrates
Ehsan Tahmasebian 1 Onkar Singh 2 Michael Freund 2 Peter Gillingham 3
1University of Manitoba Winnipeg Canada2University of Manitoba Winnipeg Canada3Conversant Intellectual Property Management Ottawa CanadaShow Abstract
Complex fabrication process and poor signal scaling laws of the silicon based memory devices have increased the interest in perusing the fabrication of non-transistor based memory structures. Previously a redox-based memory system based on the variable doping has been demonstrated by our group1,2. This memory system consists of a solid-state junction between compensatively-doped polymer and undoped WO3 in a net low conductivity state formed by electrochemical deposition. In the presence of a sufficiently high electric field, dopant ions relocate into the metal oxide layer, resulting in an n-doped metal oxide and p-doped polymer and a net high conductivity state. This system is capable of producing transient current-voltage characteristics that can be controlled by electric field and act as a memory. As a non-transistor memory structure, this system has the potential to be integrated into standard CMOS technology. To do so, the junctions should be formed on metals commonly used in CMOS technology. In recent work, our group has focused on use of these metals including aluminum and copper as the top. Early tests on the aluminum contacts did not show promising results, however a deposition method on copper has been demonstrated3. The new system consists of an electrochemically deposited tungsten oxide film covered by electrophoretically deposited conducting polymer (poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS)) all formed at negative potentials on copper substrates. The electrical properties of these junctions demonstrate that they have the potential of creating CMOS-compatible polymer based memory devices. Current efforts are focused on demonstrating the similar electrical behavior on an array of small junctions. A crossbar structure of copper contacts has been fabricated to form a 10x10 array of these junctions. The resulting electrical properties of the memory array junctions, their current-voltage behavior has been used for modeling them as an element that can be used in CMOS device simulation tools, such as Hspice. The junction has been modeled as a voltage controlled current source and a piece-wise linear model has been developed to model the real current-voltage characteristics of the junction as the function between the voltage and current of this voltage controlled current source in the simulations. This model is currently under study for simulating and designing a complete CMOS chip with a deposited array of the polymer memory junctions on top which will work as a full memory system, capable of addressing, writing and reading operations on different bits of the memory.
 Rahman, et al. "Engineering dopable heterojunctions for modulating conductivity in the solid state" American Chemical Society.
 Kumar, et al. "Controlling volatility in solid-state redox-based memory devices" Chemical Communications.
 Yahyaie, et al. "Polymer-Based Memory Structures on Copper Substrates" Electrochemical Society.
9:00 AM - AA4.06
Computational Investigation of the Phase Stability and the Electronic Properties of Gd-Doped HfO$_2$
Ligen Wang 1
1General Research Institute for Nonferrous Metals Beijing ChinaShow Abstract
Rare earth doping is widely used to improve the properties of high-$k$ dielectric oxides. We have performed the density functional theory calculations for Gd doping in HfO$_2$. Our calculated results indicate that the tetragonal phase is more stable than the monoclinic phase when the Gd doping concentration is greater than 15.5\%, which is in a good agreement with the experimental observations. The dopant's geometric effect is mainly responsible for the phase stability. The Gd doping enlarges the band gap of the material. The dielectric constant for the Gd-doped HfO$_2$ is in the range of 20-30 that is suitable for high-k dielectric applications. Moreover, we have investigated the structural and electronic properties of the dopant-oxygen vacancy complexes in Gd-doped HfO$_2$. Our calculations indicate that the Gd dopants interacting with oxygen vacancies can substantially shift up the V$_O$ energy states towards the conduction band edge. This together with other effects, such as capturing the localized electrons at the oxygen vacancy by Gd dopants and suppressing the randomicity of oxygen vacancy formation, improves the reliability of the devices made from Gd-doped HfO$_2$. Based on the calculated results, we have presented an explanation for the experimentally observed decrease of the V$_O$-related photoluminescence intensities upon Gd doping in HfO$_2$.
9:00 AM - AA4.08
Highly Reduced Electroforming Voltage in Resistive Memories by Inserting Gold Nanoparticles Monolayer
Kai Qian 1 Pooi See Lee 1 Jiangxin Wang 1
1NTU Singapore Singapore SingaporeShow Abstract
Resistive random access memory (RRAM) which is a strong contender to replace charge-based memories (e.g. Flash memory, dynamic random access memory) has promising potential as the next generation nonvolatile memory owing to its excellent properties, such as extreme scalability, low power consumption and high write/erase speed. However, in order to initially activate the fresh memory cell into the switchable states, high electroforming voltage is required which consumes power and may cause permanent damage to the switching performance and lower the device yield.
In this work, the RRAM device (Ag/amorphous Si/Au NPs/Au) was fabricated by inserting a gold nanoparticles (Au NPs) mono-layer within the amorphous Si sandwiching between the active top and inert bottom electrodes. We demonstrate the Au NPs-interlayer amorphous Si memory devices deliver great improvements in lowering the electroforming voltage as well as enhancing the ON/OFF ratio, as compared to a pure amorphous Si memory structure. In addition,we also demonstrated that the low electroforming voltage can be realized by replacing the amorphous Si with zinc oxide layer in the similar configuration with Ag as the electrodes (Ag/ZnO/Au NPs/Au), whereas this does not happen in the Au/ZnO/Au NPs/Au memory structure with Au electrodes.From these observations, a possible switching mechanism is discussed based on the formation of Ag filaments around the tips of Au NPs, where the filaments can be nucleated and propagated easily and quickly. At the same time, the electroforming voltage can be tuned by changing the size of Au NPs. This fabrication approach offers a versatile structural platform for next-generation memory applications with enhancement of the switching properties.
9:00 AM - AA4.09
Analog Memristive and Memcapacitive Characteristics of Pt-Fe2O3 Core-Shell Nanoparticles Assembly on p+-Si Substrate
Young Jun Noh 1 Yoon-Jae Baek 1 Young Jin Choi 2 Chi Jung Kang 2 Hyun Ho Lee 3 Tae-Sik Yoon 1
1Myongji University Yongin-si Korea (the Republic of)2Myongji University Yongin-si Korea (the Republic of)3Myongji University Yongin-si Korea (the Republic of)Show Abstract
Analog memristive and memcapacitive switching characteristics were demonstrated in Pt-Fe2O3 core-shell nanoparticles (NPs) assembly on p+-Si substrate. Memristor having memristive characteristics, i.e. reversible resistance change with memory function, has been actively explored for a variety of device applications including a nonvolatile resistive random access memory (RRAM) with digital-type resistance change, analog switch, analog memory, and neuromorphic devices with analog-type resistance change. In particular, the analog memristor emulates the biological synaptic motion with varying synaptic weight, called potentiation and depression, so it is considered to be a good candidate device for synaptic element in neuromorphic device. Besides the memristor, the memcapacitive characteristics defined to show the capacitance change with memory function has been recently reported. In this study, we demonstrate the concurrent analog and polarity-dependent memristive and memcapacitive characteristics in the assembly of g-Fe2O3 NPs having Pt core (called Pt-Fe2O3 core-shell NPs) on p+-Si substrate, which can be potentially applied to neuromorphic and analog devices. These NPs have large surface and interfacial area that effectively provides trapping and hopping sites for charge transport and consequently influences on the resistance and capacitance change. Also, the applied electric field is concentrated in the metallic Pt cores inside the insulating Fe2O3 shell; therefore the memristive and memcapacitive characteristics associated with charge trapping is thought to be facilitated by using Pt-Fe2O3 core-shell NPs. The Ti/NPs/p+-Si structure exhibited the sequentially decreasing resistance and increasing capacitance as repeating the application of negative voltage at top Ti electrode. It is thought that the negative charging of the assembly increased free electron density in the assembly or reduced the Schottky barrier height, which increased the current and diffusion capacitance at n-NPs/p+-Si junction. On the other hand, the positive biasing increased the resistance and decreased the capacitance by reducing the free electron density and increasing depletion width at the junction. These concurrent analog memristive and memcapacitive characteristics emulated the biological synaptic potentiation and depression motions, which is indicative of potential application to neuromorphic devices as well as analog nonvolatile memory and circuits.
9:00 AM - AA4.10
Perpendicular Magnetization Switching via Current induced Spin-Orbit Torques on Flexible Substrate
OukJae Lee 1 Long You 1 JaeWon Jang 1 Vivek Subramanian 1 Sayeef Salahuddin 1
1UC Berkeley Berkeley United StatesShow Abstract
The electrical manipulation of ultra-thin magnets via strong spin-orbit coupling is currently the focus of strong research interest, because this phenomenon may offer significant advantages with respect to energy efficiency and high-speed operation in technological applications including non-volatile memory and logic devices. Very recently a new method for electrical control of magnetization has been demonstrated where spin-Hall induced spin torques from in-plane currents achieve deterministic magnetic reversal of a magnetic layer in multilayer NM/FM/MOx samples consisting of a nonmagnetic heavy metal (NM) adjacent to an ultra-thin ferromagnet (FM) that is capped with a thin metal oxide (MOx): for instance, Pt/Co(<1nm)/AlOx or Ta/CoFeB(~1nm)/MgO on rigid substrates. At the same time a magnetic system with a sufficient perpendicular magnetic anisotropy (PMA) offers superior areal densities and thermal stabilities than in-plane magnetic system. However such demonstrations utilizing spin-orbit torques have been performed on rigid substrates, while only in plane magnetized system have been studied on flexible substrates as far as we know. Implementation of perpendicularly magnetized thin films and of electrically functional devices on flexible substrates may offer new degree of freedom such as strain effect on the ultrathin magnetic films with a strong spin-orbit coupling. Moreover the flexibility has advantages in applications with bendable, stretchable and/or mobile environment.
In this talk we present the magnetic characteristics of ultrathin multilayers with a sufficient PMA that were grown on a flexible plastic substrate by dc/rf magnetron sputtering. In addition we fabricate cross-Hall bar devices and demonstrate fully deterministic magnetic reversal of perpendicularly magnetized square dots via in-plane dc and/or pulsed currents. We believe that integration of two emerging technologies promises new spintronic devices that can be utilized in arbitrary surface geometries and be worked in ultra small dimensions.
9:00 AM - AA4.11
Cleaning and ALD Nucleation on InN(0001) Surface
Sang Wook Park 1 2 Tobin Kaufman-Osborn 1 2 Kasra Sardashti 1 2 S.M. Moududul Islam 3 Debdeep Jena 3 Hyunwoong Kim 1 2 Andrew C. Kummel 1
1University of California San Diego La Jolla United States2University of California San Diego La Jolla United States3University of Notre Dame Notre Dame United StatesShow Abstract
Indium nitride (InN) has attracted much attention because of band offset to GaN and related materials. However, there has been difficulty in using InN as commercial devices due to the presence of electron accumulation at the surface. The electron accumulation layer is hypothesized to be due to an In-In double layer at the surface. To utilize InN in practical devices, it is critical to remove this In-In double layer and form a non-metallic surface. The atomic, elemental, and electric structure of InN(0001) surface before and after removal of the In-In double layer was investigated with using scanning tunneling microscopy (STM), x-ray photoelectron spectroscopy (XPS), and scanning tunneling spectroscopy (STS) under different cleaning and atomic layer deposition (ALD) methods.
(1) In-situ atomic hydrogen cleaning of InN(0001) surface was investigated since this process is successful on GaN(0001). STM images were consistent with rows of indium dimers due to the preferential nitrogen depletion resulting in high indium to nitrogen ratio. STS measurement showed that there was no band gap states, indicating metallic characteristics of InN surface consistent with an In-In double layer surface termination.
(2) ex-situ wet cleaning using HCl, NH4OH, and (NH4)2S solution was performed. After wet cleaning, STM images showed that the surface was smooth and uniform. XPS spectroscopy showed that the wet cleaned surface had less than 10% carbon and oxygen. STS spectroscopy showed a finite band gap of 0.7 eV with highly n-type characteristics consistent with strong intrinsic accumulation of electrons on the InN surface.
(3) O2 passivation of InN surface was performed to remove the In-In double layer. STM imaging showed that the oxidized surface was atomically flat and uniform. STM line traces illustrated that clusters were formed with step height of 3.5 angstrom which belongs to two monolayers of InOx. The band gap at O2 passivated InN surface was ~0.8 eV which is slightly larger than the wet cleaned surface of ~0.70 eV. Furthermore, the n-type characteristic was eliminated due to the formation of O-In-O layer which reduces accumulation of electrons on the InN surface The Fermi level lie in the center of the band gap . XPS showed oxidized InN surface has less than 5% carbon and provides high density of nucleation sites for trimethyl aluminum (TMA).
(4) ALD nucleation was studied using TMA pre-dosing and an additional 10 cycles of TMA and H2O dose on an O2 passivated InN substrate. After the 10 cycles of ALD, ratio of Al to O ratio was 2:3 corresponding to stoichiometric ratio of Al2O3. The ALD process broadened the band gap from ~0.8 eV to ~1 eV due to the formation of Al-O-Al bonding. A larger band gap than conventional InN surface is an ideal template for InN metal oxide semiconductor (MOS) capacitor fabrication. In sum, an unpinned non-metallic interface can be formed on InN using an oxidant to remove the In-In layer and a reductant to nucleation the ALD.
9:00 AM - AA4.12
P(VDF-TrFE)/PMMA Ferroelectric Films for Low Voltage Non-Volatile Polymer Memory Transistors
Deepa Singh 1 Deepak . 1 Ashish Garg 1
1Indian Institute of Technology Kanpur Kanpur IndiaShow Abstract
Non-volatile memory (NVM) devices based on ferroelectric thin films show bistable polarization at zero bias, designated as ‘0&’ and ‘1&’ logic states. Current emphasis on developing flexible and large area devices requires use of polymeric and organic materials which makes organic ferroelectric polymers such as P(VDF-TrFE) worth exploring due to their low temperature and solution processibility. The optimum performance of a ferroelectric NVM device needs a remnant polarization of over 4-5 mu;C/cm2, low operating voltage and low leakage current. To meet these requirements, we investigated the variation of process variables such as cooling time and electrode on the film formation and its electrical properties. We found that fast cooled samples possess higher β-phase fraction which characterizes the ferroelectric nature of P(VDF-TrFE), leading to an increased polarization by 30%, decreased coercivity by 60% and reduced electrical leakage in capacitive memory devices. These improvements in the ferroelectric characteristics are attributed to evolution of a favorable microstructure and crystallographic alignment. For further reduction of leakage characteristics of the P(VDF-TrFE) devices, we incorporated PMMA, a dielectric material, along with P(VDF-TrFE) with different amounts in three different configurations : in the form of blend, and two bilayer structures, one with PMMA films below P(VDF-TrFE) films and another with PMMA films on top of P(VDF-TrFE) films. We find that PMMA incorporation leads to nearly two orders of magnitude reduction in the electrical leakage rendering bilayer devices more suitable for device applications than P(VDF-TrFE) only devices: 60 nm PMMA led to a smother dielectric stack with remnant polarization between 4-6 µC/cm2. Organic ferroelectric field effect transistor (FeFET) fabricated by thermal evaporating pentacene on the smooth P(VDF-TrFE)/PMMA films showed enhanced electrical characteristics (large drain to source current at lower gate voltage) with promising non-volatile memory functionality with an order of magnitude improvement in Ion/Ioff ratio.
9:00 AM - AA4.13
Nano-Structured TiOx/TiO2 Layer Based Resistive Switching Memory Driven by Low Voltage using Rapid Thermal Annealing
Kwan-Jun Heo 1 Ju-Song Eom 1 Su Chang Yoo 1 Jae-Mun Oh 1 Byung-Do Yang 1 Sung-Jin Kim 1
1Chungbuk National University Cheongju Korea (the Republic of)Show Abstract
Resistive random access memory has engaged great attention because of superior characteristics, such as simple metal-insulator-metal structure, high density integration, fast write/erase/read operation and low-power consumption compared to Si-based nonvolatile memory.
Most of the active materials for those memory devices have relied mainly on perovskite and related compounds, for instance, SrZrO3 and metal oxides such as TiO2, NiO, CuxO [1-2]. One of these materials, titanium oxide (TiO2) exhibits promising oxide semiconductor for the application of nano-scale electronic behaviors such as resistive random access memory and switching of memristive devices. In particular, great interest has been engaged on TiO2 semiconductors as an active layer for memory devices due to their low cost, the abundance of Ti element, and their high transparency owing to a wide band gap.
Although the TiO2 active layer have been demonstrated by the several methods, such as solution-process, pulsed laser deposition, magnetron sputtering. The performances of these exhibited the relatively low electrical characteristic limiting the effects of process parameters. Furthermore, these methods can not to assure the deposited thickness of below 50 nm. To prepare high-performance and driven by low voltage TiO2 based memory, it is necessary that a well understanding of how the interface structure affect the memory performance and a comprehensive investigation of the optimization conditions.
In this presentation, we report on resistive switching behaviour in a memristor device composed of a bilayer TiOx/TiO2 fabricated with atomic layer deposition based on key process parameters, such as the rapid thermal annealing temperature. The oxygen-deficient TiOx active layer annealed at 600°C acted as a trap for electrons and contributed to the resistive switching. The proposed ultra-thin memristor exhibited nonvolatile memory characteristics, such as write-erase-read operation and repeatable hysteresis loops in I-V curves.
This work was supported by the Human Resources Development of the Korea Institute of Energy Technology Evaluation and Planning (KETEP) grant funded by the Korea government Ministry of Trade, industry & Energy (No. 20144030200450).
 A. Beck, J.G. Bednorz, C. gerber, C. Rossel, and D. Widmer, Appl. Phys. Lett., 77, 139, (2000)
 L.-E. Yu, S. Kim, M.-K. Ryu, S.-Y. Choi, and Y.-K. Choi, IEEE Electron Device Lett., 29, 331, (2008)
 S.-H. Kim, Y.-K. Choi, IEEE Electron Device, 56, 3049, (2009)
 P.-C. Yao, J.-L. Chiang, and M.-C. Lee, Solid State Sciences, 28, 47, (2014)
9:00 AM - AA4.14
Synergistic High Charge-Storage Capacitance of Flexible Organic Flash Memory
Minji Kang 1 Dongyoon Khim 2 Won-Tae Park 2 Rira Kang 1 Jun-Seok Yeo 1 Sehyun Lee 1 Yen-Sook Jung 1 Dae-Hee Lim 1 Yong-Young Noh 2 Kang-Jun Baeg 3 Dong-Yu Kim 1
1Gwangju Institute of Science and Technology Gwangju Korea (the Republic of)2Dongguk University Seoul Korea (the Republic of)3Korea Electrotechnology Research Institute Changwon Korea (the Republic of)Show Abstract
Electret and organic floating-gate memories are technologies of next-generation flash storage for printed organic nonvolatile memories. While each flash memory can be easily fabricated using solution processes on flexible plastic substrates, promising their potential for on-chip memory organization is limited by unreliable bit operation and high write loads. We here report that new architecture could improve the overall performance of organic memory, and especially meet high storage for multi-level operation. Our concept depends on synergistic effect of electrical characterization in combination with a polymer electret (poly(2-vinyl naphthalene) (PVN)) and metal nanoparticles (Copper). It is distinguished from mostly organic nano-floating-gate memories by using the electret dielectric instead of general tunneling dielectric for additional charge storage. The uniform stacking of organic layers including various dielectrics and poly(3-hexylthiophene) (P3HT) as an organic semiconductor, followed by thin-film coating using orthogonal solvents, greatly improve device precision despite easy and fast manufacture. P(VDF-TrFE) as high-k blocking dielectric also allows reduction of programming voltage. The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.
9:00 AM - AA4.15
Nonpolar Resistive Memory Switching in High-K Ternary Oxide Based Pt/LaHoO3/Pt Memory Devices
Yogesh Sharma 1 Shojan Pavunny 1 Ram S. Katiyar 1
1University of Puerto Rico San Juan United StatesShow Abstract
The nonpolar resistive switching (RS) exhibits both unipolar as well as bipolar switching characteristics which do not depends on the polarity of applied voltages. Such switching can be considered advantageous due to faster switching speed, better uniformity (features of bipolar switching), and high integration density (feature of unipolar switching), which can potentially serve the advanced application scopes of resistive random access memories (RRAMs). We investigated the nonvolatile resistive switching (RS) behaviour in pulsed laser deposited amorphous LaHoO3 thin films. Nonpolar RS was observed in Pt/ LaHoO3/Pt device with all four possible modes (I. Positive unipolar, II. Negative unipolar, III. Posive bipolar, and IV. Negative bipolar) with RON/ROFF ratio in the range of ~ 105-106. X-ray photoelectron spectroscopy studies combined with temperature dependent switching characteristics divulged the formation of mixed conductive nanofilaments consisting metallic Ho atoms and oxygen vacancies in the low resistance state (LRS). Detailed analysis of current-voltage relationship further confirmed the formation of conductive filaments on the basis of observed Ohmic conduction in ON-state. Simmons modified Schottky emission was ascribed to be the dominant conduction mechanism in OFF-state of the device. We will present the aforementioned properties of these memory cells and will discuss the intended nonvolatile memory applications of this novel high-k dielectric material in detail.
9:00 AM - AA4.16
Improved Resistive Switching Performance in Rare-Earths (Sm, Gd)-Modified HfO2 Thin Films Fabricated Using Sequential Pulsed Laser Deposition Technique
Yogesh Sharma 1 Shojan Pavunny 1 Ram S. Katiyar 1
1University of Puerto Rico San Juan United StatesShow Abstract
Transitional metal oxides (TMOs), such as HfO2, NiO, TiO2, ZrO2, CuxO, TaOx and ZnO are engendering great research interest as promising materials for resistive random access memories (RRAMs). Among different TMOs, HfO2 has paved the way as gate dielectric in complementary metal oxide semiconductor (CMOS) transistors due to its compatibility with the semiconductor fabrication process. First principles calculations [Appl. Phys. Lett. 96, 123502 (2010)] showed that the trivalent ion doping in HfO2/ZrO2 matrix can reduce oxygen vacancy formation energy (Ef,V) and consequently induced more oxygen vacancies (VO), which could be useful for localized growth of conductive filaments (CFs) depending on the dopants location. Under this context, we present experimental studies on the effect of trivalent rare-earth doping on improving the resistive switching performance of Sm/Gd-doped HfO2 thin films. Highly crystalline thin films were fabricated on Pt/TiO2/SiO2/Si substrate by sequential ablation of HfO2 and Sm2O3/Gd2O3 ceramic targets using pulsed laser deposition. The desired dopant concentrations were achieved in the film by controlling the ablation time of Sm2O3/Gd2O3 targets. X-ray diffraction analysis showed that 2% Sm/Gd-doped films have monoclinic structure, while stable tetragonal phase of HfO2 was observed in the films having 5 and 10% doping concentrations. Electroforming free non-volatile unipolar resistive switching behaviour was observed in all the doped films, where improved memory performances in terms of switching parameters were observed with the increase in Sm/Gd-doping concentrations. In 10% Gd/Sm-doped films, ON/OFF ratios were found to be three orders of magnitude higher (~ 106) and the SET/RESET voltages were observed to be almost one third (SET ~ 0.5 V and RESET ~ 1.5) as compared to the films having 2% doping. Improved switching performances with increase in doping concentration can be attributed to the easy formation of CFs due to the high concentration of oxygen vacancies, where Sm/Gd-doping further facilitate the localized growth of CFs and hence improved the switching parameters. Detailed analysis of current-voltage relationship confirmed the formation of CFs based on Ohmic conduction in ON-states. Our work provides a useful technique to design HfO2-based RRAM devices for improved performance.
9:00 AM - AA4.17
Nano-Floating Gate Memory Devices Using 3D Multi-Stacking Arrays with Densely Packed Hydrophobic Metal Nanoparticles for Charge Trapping Layers
Ikjun Cho 1 Dongyeeb Shin 1 Jinhan Cho 1
1Korea University Seoul Korea (the Republic of)Show Abstract
Organic field-effect transistor (OFET) memories have rapidly advanced from low-cost and flexible electronics with relatively low memory capacities to memory devices that require high-capacity memory such as smart memory cards or solid-state hard drives. To this end, various types of OFET memory devices have been designed, including ferroelectric, molecular gate storage, polymer electret, and nano-floating gate memory devices. The nano-floating gate memory (NFGM) devices with metal nanoparticles (NPs) embedded in the gate dielectric are advantageous over other types of OFET memory devices due to discrete and stable memory elements. Here, we report that the high-capacity NFGM based on the multi-stacking of densely packed hydrophobic metal NP layers in place of the traditional NFGM composed of a single charge trapping layer. We demonstrated that the number density of the charge trap sites, which has a decisive effect on the memory performance, can be easily modulated via the adsorption isotherm behavior, number of stacked layers of the charge trapping metal NPs and hydrophobicity of metal NPs. For this study, tetraoctylammonium (TOA)-stabilized Au nanoparticles (TOA-AuNPs) were consecutively layer-by-layer (LbL) assembled with an amine-functionalized poly(amidoamine) dendrimer (PAD) driven by the high affinity between the metal NPs and the amine groups. Notably, the hydrophobic TOA-AuNPs, which did not display inter-particle electrostatic repulsion, formed densely packed layers on the PAD layer in nonpolar solvents. This approach has an important advantage in that the number density of hydrophobic metal NPs (i.e., charge trap elements) can be remarkably increased, thereby forming the multi-stacked charge trapping layers (i.e., (PAD/TOA-AuNP)n multilayers). The formed (PAD/TOA-AuNP)n films which induced a memory effect by a charge trap/release mechanism were deposited at the interface between the tunneling dielectric layer and the SiO2 gate dielectric layer. When we increased charge trapping layers according to vertical dimension from a single layer to 4 layer stacks, the number density of TOA-AuNPs increased from 1.82 × 1012 to 7.54 × 1012 cm-2, the ΔVth of the AuNP-based NFGM devices increased from 97 to 146 V, yielding a P/E current ratio of approximately 106 after the application of a program/erase (P/E) bias of VG = ± 100 V. Additionally, the multi-layer stacked NFGM exhibited a fast switching speed and good electrical stability during operating the devices. The importance of this work lies in the fact that the memory performances of nano-floating gate memory devices can be notably improved through precise control over the charge trap densities in the vertical dimension as well as in the lateral dimensions. Compared with other fabrication techniques, our approach can significantly enhance the memory capacities of transistor memory devices simply by modulating the number of bilayers present and the packing density of charge trap elements.
9:00 AM - AA4.18
Density-Functional Theory Molecular Dynamics Simulations of High-K Dielectrics on SiGe and GaN Substrates
Evgueni Chagarov 1 Andrew C. Kummel 2
1UCSD La Jolla United States2University of California-San Diego La Jolla United StatesShow Abstract
Comprehensive density-functional theory molecular dynamics (DFT-MD) simulations of GaN and SiGe interfaces with a-Al2O3, a-HfO2 and a-TiO2 oxides were performed. Single and double amorphous oxide stacks of a-Al2O3 and a-HfO2 on GaN were simulated. The simulations used high-quality models of a-Al2O3, a-HfO2 and a-TiO2 oxides generated by multi-step melt-and-quench hybrid Classical-DFT MD simulations. The electronic structure of investigated stacks was calculated with higher-order HSE06 hybrid-functional, expanding band-gap to correct values and providing additional insight into electronic structure. While the GaN surface is dominated by either filled or empty dangling bonds, the SiGe surface is dominated by half-filled dangling bonds so the interaction with oxide is expected to be much stronger.
Due to its wide band-gap of 3.4 eV, gallium nitride (GaN) is a promising semiconductor for applications in optoelectronic, high-power and high-frequency devices. We have performed a large set of DFT-MD simulations of a-Al2O3 and a-HfO2 on GaN using various GaN surface terminations and passivating interlayers (a-AlN, a-Al5N3O3, O, O-Ga-O, O-Al/O-Ga-O, S, As, etc). In addition, double oxide stacks were simulated such as a-Al2O3/a-HfO2/GaN, a-HfO2/a-Al2O3/GaN, a-Al2O3/a-Al5N3O3/GaN, and a-Al2O3/a-AlN/GaN. The investigated stacks were DFT-MD annealed, cooled and relaxed. The HSE06 hybrid-functional DOS curves revealed that a-HfO2/a-Al2O3/GaN(0001) stack has better electronic structure with a slightly wider band gap than a-Al2O3/a-HfO2/GaN(0001) stack. The effect of interlayers on electronic structure was investigated by inserting a-AlN and a-Al5N3O3 between a-Al2O3 and GaN(0001) substrate. The DOS curves revealed midgap and band-edge states, caused by Al-Al bonds at the oxide/amorphous nitride interface, Ga-Al bonds at the amorphous nitride/GaN interface, and under-coordinated Ga atoms forming no bonds to the a-AlN oxide.
Much attention has been given to using SiGe as a channel material due to its high hole mobility and the facility to deposit films under tensile (Si-rich substrate) or compressive (Ge-rich substrate) stress thereby enhancing electron and hole mobility. We have performed a set of comprehensive DFT-MD simulations of SiGe using different surface terminations (Si or Ge) and various oxides (a-HfO2, a-Al2O3, a-TiO2) such as a-Al2O3/SiGe(Si-Term), a-Al2O3/SiGe(Ge-Term), a-Al2O3 /SiGe(110), a-HfO2/SiGe(Si-Term), a-HfO2/SiGe(Ge-Term), a-TiO2/SiGe(Si-Term), and a-TiO2/SiGe(Ge-Term) stacks. The simulated interfaces were analyzed to investigate structural and electronic properties. Band-decomposed charge density simulations were performed to localize sources of some midgap or band-edge states.
9:00 AM - AA4.19
Comparative Study of Carbon Nanotube Vias for End-of-Roadmap Technology Nodes
Anshul A Vyas 1 Changjian Zhou 2 Yusuke Abe 3 Phillip Wang 4 Mansun Chan 2 Cary Y. Yang 1
1Santa Clara Univ Santa Clara United States2Hong Kong University of Science and Technology Kowloon Hong Kong3Hitachi High-Tech Ibaraki Japan4Applied Materials Santa Clara United StatesShow Abstract
As silicon technology node continues to scale downwards aggressively in the sub-100 nm regime, increasing challenges emerge for both active and passive components on the chip. While the feature sizes of transistors and interconnects are scaled at every node, and the speed of transistors continues to increase, propagation delays due to increase in interconnect resistance have become the dominant chip performance-limiting factor . Further, the current interconnect materials, Cu and W, face reliability challenges resulting from electromigration at higher current densities . Several materials such as carbon nanotubes (CNTs), graphene, nanoribbons, and Ag nanowires are being considered as potential replacements for Cu and W in via interconnects, due to their superior electrical and mechanical properties . However, before they become truly viable replacement candidates, key roadblocks such as high contact resistance and high processing temperature must be addressed. In particular, CNT is most promising to replace Cu and W in vias due to its ultra-high current capacity and its filling ability in high aspect-ratio structures. While most of the research on study of CNTs has been focused on lowering the growth temperature for process integration  or finding a suitable metal for via top contact , there are limited reports on evaluating the performance of CNTs and comparing it with those of Cu and W as the feature size scales downwards in the sub-100 nm regime.
Based on our recent work on resistance measurements of CNT vias with widths ranging from 150 nm to 60 nm , we have compiled an extensive comparison of reported results. These results on CNT vias are also compared with their counterparts for Cu and W. We have demonstrated that CNT via performance is beginning to approach that of W, though more improvements in CNT growth and contact resistance are still needed to be truly competitive. The lowest measured resistance for a 60 nm-wide, 130 nm-high CNT via is 150 #8486;. Statistical analysis has been performed to yield a best projected resistance of 295 #8486; for a 30 nm-wide CNT via, five times its W counterpart. Such improvements will eventually enable functionalized CNT via interconnects for next-generation IC technology nodes to be within reach.
 International Technology Roadmap for Semiconductor 2013 Edition, available online at www.itrs.net
 Vollebregt et al "Carbon nanotube vias fabricated at back-end of line compatible temperature using a novel CoAl catalyst," IEEE Interconnect Technology Conference (IITC), 2013, pp.1,3,
 Chiodarelli et al., "Carbon nanotube interconnects: Electrical characterization of 150 nm CNT contacts with Cu damascene top contact,"IEEE Interconnect Technology Conference and 2011 Materials for Advanced Metallization (IITC/MAM), pp.1,3,
 C. Zhou, A.A. Vyas, P. Wilhite, P. Wang, M. Chan, and C.Y. Yang, “Resistance Determination for Sub-100nm Carbon Nanotube Vias,” submitted for publication.
9:00 AM - AA4.20
Sputtering Deposition of Pt/Co/CoFeB/MgO Heterostructure for Tilted Perpendicular Anisotropy
Long You 1 OukJae Lee 1 Haron Abdel-Raziq 1 Sayeef Salahuddin 1
1University of California at Berkeley Berkeley United StatesShow Abstract
Spin transfer torque random access memory (STT-RAM) is regarded as a promising non-volatile alternative to SRAM cache memory and DRAM, since STT-RAM warrants high density, high speed and ultimate scalability. However, the large current densities are required especially for high speed writing. In addition, erroneous writing by the reading current can also occur, as writing/reading currents share same path. Recently, the bipolar switching the magnetization of ferromagnet layer induced by an in plane current via spin orbit torque (SOT) provides an exciting approach to the development of low power dissipation memory and logic devices. Strong SOT can be generally afforded in the metal oxide/ferromagnet/heavy metal heterostructues with large perpendicular magnetic anisotropy (PMA), which is beneficial for high thermally stability. However, the main obstacle for practical implementations of perpendicular switching of magnets with such structures is the necessity to apply a magnetic field to assist SOT-driven switching, due to symmetry reasons. A tilted anisotropy breaks the symmetry of the problem and makes it possible to switch the magnet deterministically without external magnetic field[1,2]. Here we discuss how to precise control the anisotropy tilt angle, the method is to couple the perpendicular magnetic anisotropy (PMA) hard layer (Co/Pt) with an in-plane soft layer (IMA, CoFeB). Due to the competition between the PMA and IMA, the tilted angle can be tuned by varying thickness of IMA. The stack of Pt(5 nm)/Co (1 nm)/CoFeB ( x nm)/MgO (2nm) (x varied from 0 to 1 nm) was deposited by magneto-sputtering system. The magnetic properties were investigated by vibrating sample magnetometer (VSM). The electric transport of microscale devices comprised of that stack were also studied by our probe station with electromagnet.
 Kwaku Easona, Seng Ghee Tana, Mansoor Bin Abdul Jalil, Jun Yong Khoo, Bistable perpendicular switching with in-plane spin polarization and without external fields, Phys. Rev. A 377, 2403-2407 (2013)
 Long You, OukJae Lee, Debanjan Bhowmik, Dominic Labanowski, Jeongmin Hong, Jeffrey Bokor, Sayeef Salahuddin, Switching of perpendicular nanomagnets with spin orbit torque without an external magnetic field by engineering a tilted anisotropy, http://arxiv.org/abs/1409.0620ena.
9:00 AM - AA4.21
Oxygen-Driven Resistive Switching in Silicon-Rich Silica: The Physical Framework of Highly Efficient and Scalable Non-Volatile Memory
Mark Buckwell 1 Luca Montesi 1 Adnan Mehonic 1 Manveer Munde 1 Stephen Hudziak 1 Sarah Fearn 2 Richard Chater 2 David McPhail 2 Anthony Kenyon 1
1University College London London United Kingdom2Imperial College London London United KingdomShow Abstract
We present results from a resistive switching study of 30 - 40 nm thick layers of insulating silicon-rich silica sandwiched between conductive electrodes. A voltage applied across the switching layer drives the drift and diffusion of oxygen ions and, in turn, switches the material from a highly insulating state to a conductive state with a difference in resistance of up to three orders of magnitude. Device resistances may subsequently be read with a small bias voltage without inducing further changes. Due to the non-volatile nature and readability of these states, such devices may be used to store binary data. Additionally, the use of silica as a switching material provides a facile means of integration into existing CMOS infrastructures. The physical processes that occur during changes in resistance are highly dynamic, ranging from the movement of ions to measurable structural deformations. The collective result of such changes is the formation of a filament-like conductive pathway that bridges the switching layer. We use atomic force microscopy, x-ray photoelectron spectroscopy and secondary ion mass spectroscopy to characterise the conductive bridge formation. From these measurements we propose a model for filamentary switching that allows us to better understand the requirements for integrating this technology into consumer devices.
9:00 AM - AA4.22
MOCVD Epitaxy and Characterization of III-As and III-P Thin Layers on 300mm Silicon Substrate
Mickael Martin 1 Romain Cipro 1 Mathilde Billaud 1 Jeremy Moeyaert 1 Franck Bassani 1 Sandrine Arnaud 1 Sylvain David 1 Viktoriia Gorbenko 2 Jean-Paul Barnes 3 Herve Boutry 3 Julien Duvernay 3 Mikael Casse 3 Yann Bogumilowicz 3 Nevine Rochas 3 Nicolas Chauvin 4 Xinyu Bao 5 Zhiyuan Ye 5 Jean-Baptiste Pin 5 Errol Sanchez 5 Thierry Baron 1
1CNRS Grenoble France2CNRS-LTM Grenoble France3CEA-LETI Grenoble France4INL Lyon France5Applied Materials Santa Clara United StatesShow Abstract
The last few years have seen a growing interest for monolithic integration of III-V materials within a silicon platform. Electrical and optical properties of III-V materials (high carrier mobility, direct gaphellip;) could be combined with the existing knowledge in silicon technologies to increase the integrate circuits performances. In nano-electronics, this could lead to an alternative for building low power MOS transistor channels. Other applications in opto-electronics could create new features by integrating high efficiency light transmitters and receivers. Integration of III -V materials on silicon could be obtained by two ways. In the first one, the layers or devices are fabricated on a III-V substrates and then transfer on a Si substrate. In the second one, hetero-epitaxy of III -V materials on silicon is proposed it presents many technological challenges. High density of crystalline defects (dislocations, antiphase domains, twins, and stacking faults) due to the difference in lattice parameter and polar / non-polar interface between the two materials, are issues that need to be addressed.
We present a study on the nucleation and growth of GaAs, GaP, epitaxially grown on Si 300 mm substrate by MOCVD on an Applied Materials tool. The results obtained on nominal and offcut wafers will be shown. Then InGaAs quantum wells are grown between AlGaAs barriers. The morphology of the layers is characterized by SEM and AFM and the abruptness of the junctions is addressed by SIMS. The physical properties of the InGaAs quantum wells are characterized by photoluminescence and cathodoluminescence. They are compared with the one obtained by direct epitaxy on GaAs or InP substrates. At the end, high k dielectric is deposited on top of the InGaAs layers and capacitors are fabricated. The first electrical characterizations show a Dit of around 1012 cm-2.
9:00 AM - AA4.24
Material Characterization of Tantalum Oxide Resistive Memory Devices for Radiation Resistant Non-Volatile Memory
Joshua Holt 2 Karsten Beckmann 1 Sarah Lombardo 2 Jean Yang-Scharlotta 3 Nathaniel Cady 2
1SUNY Polytechnic Institute Albany United States2SUNY Polytechnic Institute Albany United States3Jet Propulsion Laboratory Pasadena United StatesShow Abstract
Ionizing radiation in space can damage electronic equipment, corrupting data and even disabling computers. Radiation resistant (rad hard) strategies must be employed to prolong the usefulness of electronics in space. Currently, several strategies are used to improve radiation resistance in circuits. Devices can be designed to minimize radiation effects through the use of silicon-on-insulator (SOI) processing, or thin oxides in the case of CMOS transistors. Protection diodes and clamping circuits can be used to cap the effect of an ionizing event. Finally, redundant wiring and error correction circuits can be used to bypass or mitigate damage. However, most of these strategies do not affect the memory cell itself, which must also be radiation tolerant. Resistive memory is a promising new form of memory that appears to be resistant to radiation. Hafnium oxide-based resistive memory (ReRAM) has been shown to have some degree of resistance to radiation damage. However, multiple ReRAM materials must be tested to determine the general rad-hard properties of ReRAM. Tantalum oxide is a leading ReRAM material, but has not been thoroughly investigated for radiation resistance. Therefore, this work will eventually result in a comprehensive study of the radiation resistance of tantalum oxide ReRAM.
This study serves as a foundation for future radiation experiments, investigating the mechanism of radiation damage and resistance in ReRAM devices. Fabrication of tantalum oxide films and devices was performed in a Kurt Lesker PVD75 sputtering system, by reactive RF sputtering. Oxide composition was controlled by varying the oxygen concentration in an Ar atmosphere during sputtering. Our system is capable of varying oxygen concentration during deposition, yielding a gradient of oxide composition in our devices. X-ray photoelectron spectroscopy (XPS) was used to confirm the formation of a sub-stoichiometric tantalum oxide (TaOx). Additionally, the effect of oxygen getter layers was investigated (Ti, Hf, Ta, Al). Ongoing electrical testing shows distinct forming and repeatable switching of these devices. In addition, ellipsometry (150nm to 1700nm) was performed to investigate film thickness, surface roughness, bandgap, and optical properties of the films. Rutherford backscattering (RBS) was used in conjunction with XPS to attempt to identify different sub-oxides within the films (TaO2, Ta2O3, etc.). Finally, X-ray diffraction was performed to investigate the crystallinity of the films. The effect of these properties on switching performance is the subject of ongoing investigation. This comprehensive study of TaOx devices, and the effect of the stoichiometric composition of the oxide, is a crucial step toward understanding the effects of radiation on ReRAM devices. Additionally, our results correlating material properties to switching characteristics will be of use in future tantalum oxide studies, and to further understand switching properties of ReRAM in general.
9:00 AM - AA4.25
Air Stability of Two-Dimensional Transition Metal Dichalcogenide Surfaces
Santosh KC 1 Rafik Addou 1 Diego Barrera 1 2 Roberto C. Longo 1 Julia W. P. Hsu 1 Robert M. Wallace 1 Kyeongjae Cho 1
1Univ of Texas-Dallas Richardson United States2Centro de Investigacioacute;n en Materiales Avanzados, S.C. (CIMAV) Unidad Monterrey MexicoShow Abstract
Layered transition metal dichalcogenides (TMDs) have emerged as a potential alternative channel material for ultra-thin and low power nanoelectronics. Highly tunable and unique electronic properties of TMDs made them promising novel materials for various other applications as well. However, in order to realize the superior performance of TMD based devices, the physical and chemical properties need to be understood, in particular their stability under different chemical environments. A detailed comparative analysis of the air stability (i.e., oxygen interaction) of different TMDs is still lacking. We have examined various TMD stabilities in air and found them different from graphene which is stable in air. The changes in the electronic properties with air exposure were studied using density functional theory (DFT), Kelvin probe, and photoelectron emission in air. The results reveal that transition metal sulfides are kinetically more stable than selenides in air, but all TMDs are thermodynamically unstable against oxidation. Furthermore, it is shown that TMD surface defects function as facile oxidation sites impacting their air stabilities. These findings provide helpful guidance to controlled exfoliation and device fabrication processes.
This work was supported in part by the Center for Low Energy Systems Technology (LEAST), one of six centers of STARnet, a Semiconductor Research Corporation program sponsored by MARCO and DARPA. It was also supported partially by National Council of Science and Technology, Mexico (CONACyT), project NL-2010-C33-149216 and Southwest Academy of Nanoelectronics (SWAN) center. DFT calculations were performed using Texas Advanced Computing Center (TACC).
AA1: III-V Channels
Tuesday AM, April 07, 2015
Moscone West, Level 2, Room 2005
9:15 AM - AA1.02
Kinetics and Structure of Nickelide Contact Formation to InGaAs Fin Channels
Renjie Chen 1 Shadi A. Dayeh 1
1University of California, San Diego La Jolla United StatesShow Abstract
The InGaAs high mobility channels are vowed as serious candidates for alternative channel materials for sub-10 nm technology nodes urging studies for analogous contacts to the dominant silicide contacts in the Si technology mainstream. The Ni-InGaAs (nickelide) contact technology has been demonstrated as a suitable self-aligned contact technology for InGaAs channels with record small specific contact resistivity. However, the majority studies on nickelide contact formation were conducted on planar InGaAs films and little studies focused on the contact metallurgy specific in nanoscale InGaAs nanowire or Fin channels. Here, we utilized a novel wafer bonding technique to transfer thin (50 nm) In0.53Ga0.47As layers onto SiO2/Si substrates and Si transmission electron microscopy (TEM) frames. InGaAs Fins with variable widths, lengths, and orientations were fabricated through a combination of electron-beam lithography and top-down dry etching steps, followed by Ni contact deposition. Rapid thermal annealing and in-situ TEM thermal heating cycles were conducted to react Ni with the InGaAs channel and deduce the reaction kinetics, dynamics, and resultant nickelide and interface structures. The nickelide phase was found to gradually extend into the InGaAs fin channels, introducing a 32% ± 7% height increase to the channels with negligible lateral expansion. The morphology of formed nickelide phase strongly depended on the orientation of fin structures, as we observed sharp and abrupt nickelide-InGaAs interfaces for <110> oriented fin channels, while rough interfaces with multiple facets in <100> oriented ones. Systematical measurements of the length of nickelide segments according to different annealing times, temperatures, and fin widths, revealed a Ni diffusion limited kinetic growth process, which agrees well with the derived equations from a kinetic competition model. A transition from surface diffusion limited kinetic process to volume diffusion limited one was reported for the first time, related to the increase of InGaAs fin widths. We extracted a surface diffusion coefficient of 1.3x10-15 ~ 1.5x10-15m2/s at a reaction temperature of 250 °C, which is ~5 times larger than the extracted volume diffusion coefficient. The crystalline structure analysis with TEM revealed a hexagonal lattice of formed nickelide phase, adopting a NiAs (B8) structure. Cross-sectional TEM measurements were achieved by focus ion beam (FIB) cut along the fin channels, showing a slanted nickelide-InGaAs interfaces towards the base, which is possibly induced by the stress from underneath dielectric layers. These results contrasted with the conventional contact metallurgy studies in nanowires with free surface, and the detailed structure, interface and reaction dynamics will be discussed.
9:30 AM - *AA1.03
Low-Frequent Noise and RTN on Near-Ballistic III-V GAA Nanowire MOSFETs
Peide Ye 1
1Purdue University West Lafayette United StatesShow Abstract
In this talk, we report the observation of RTN on top-down fabricated highly scaled InGaAs GAA MOSFETs. RTN and low frequency noise were systematically studied on InGaAs GAA MOSFET with various gate dielectrics, channel lengths and nanowire sizes. Mobility fluctuation is confirmed to be the source of low frequency noise, showing 1/f characteristics. Low frequency noise was found to decrease as channel length scaling down from 80 nm to 20 nm, indicating the near-ballistic transport property of highly scaled InGaAs GAA MOSFET.
10:00 AM - *AA1.04
Recent Progress in Understanding the Electrical Reliability of GaN High-Electron Mobility Transistors
Jesus A. del Alamo 1
1MIT Cambridge United StatesShow Abstract
GaN High-Electron Mobility Transistors (HEMTs) are well on their way to revolutionizing RF, microwave and millimeter-wave communications and radar systems. GaN FETs are also uniquely poised to have a disruptive impact in electrical power management. In all these applications, device reliability remains a significant concern. As the field has expanded, great progress has recently taken place in understanding GaN transistor degradation, especially under high-voltage stress. Detailed electrical studies coupled with comprehensive failure analysis involving a variety of techniques have revealed a rich picture of degradation. Early studies showed that high voltage degradation of GaN HEMTs was characterized by a critical voltage (Vcrit) at which the device gate current abruptly increases. For stress voltage beyond Vcrit, prominent degradation was observed in the drain current and other electrical parameters of the device. More recently, it has been shown that degradation in the gate current can occur for voltages below the critical voltage suggesting that stress time is a key variable in degradation. Cross-section TEM and planar imaging techniques have shown that high-voltage stress induces prominent structural defects such as grooves, pits and cracks in the GaN cap and AlGaN barrier at the edge of the gate. The evolution of these defects correlates well with that of electrical degradation. Recently, a similar pattern of degradation has been observed under high-power DC and RF stress, although not in a consistent way. A significant recent finding is the role that moisture plays in the formation of these structural defects. This suggests a path for mitigation. Separately from device degradation, a significant anomaly affecting GaN transistors is electron trapping which can severely upset device operation on a wide time domain. This talk will review recent research on the electrical reliability and trapping of GaN HEMTs.
10:30 AM - AA1.05
Efficacy of Ge Passivation with Metal-Interlayer-Semiconductor Structure on III-V FET Source/Drain Contact Resistance Reduction
Kim Seung-Hwan 1 Jeong-Kyu Kim 1 Gwang-Sik Kim 1 Chang-Hwan Choi 2 Hyun-Yong Yu 1
1Korea University Seoul Korea (the Republic of)2Hanyang University Seoul Korea (the Republic of)Show Abstract
As silicon-based complementary metal-oxide-semiconductor (CMOS) technology obviously approaches its physical limits, a need for its replacement with other materials such as GaAs and InxGa1-xAs for high mobility and scalable logic devices has emerged. However, large source/drain (S/D) spacing induced by annealing process to make ohmic contacts obstructed the scaling of III-V devices. Also, Fermi level pinning at metal/semiconductor interfaces caused by metal-induced gap states (MIGS) leads to high contact resistivity. The metal-interlayer-semiconductor (MIS) structure in order to prevent MIGS can&’t settle the Fermi level pinning perfectly by reason of high interface state density at the interlayer-GaAs substrate interfaces. Therefore, GaAs surfaces need to be passivated for Fermi level unpinning.
Sulfur passivation, which has been used widely, can suppress oxidation and passivate dangling bonds on the GaAs surface, but it cannot completely decrease interface states between the interlayer and the semiconductor for MIS structure. Germanium is greatly suitable for GaAs surface passivation because not only can it suppress surface defects of GaAs substrate, but also has similar lattice constant and thermal expansion coefficient to GaAs. Furthermore, we can unpin the GaAs Fermi level by inserting Ge interfacial passivation layer. To investigate Ge passivation effect, we designed samples of three different structures: Ti/ZnO/Ge/GaAs, Ti/ZnO/GaAs, and Ti/Ge/GaAs, all GaAs (~2×1018 cm-3) substrates having been passivated by (NH4)2S.
All samples resulted in lower contact resistance than that of Ti/GaAs with the Ti/ZnO/Ge/GaAs sample having the lowest contact resistance. The Ge passivation only cannot block the MIGS, and the ZnO interlayer only cannot prevent surface defects. However, the MIS structure with Ge passivation can effectively reduce both MIGS effect and interface state density, achieving ~300 × reduction in contact resistivity compared to the Ti/GaAs sample. As a result, the effect of Ge passivation on contact resistance reduction for MIS structure is well demonstrated.
10:45 AM - AA1.06
Low Leakage and Trap State Densities of Extremely High-K/InGaAs Gate Stacks
Varistha Chobpattana 1 Evgeny Mikheev 1 Jack Zhang 1 Thomas E. Mates 1 Susanne Stemmer 1
1University of California Santa Barbara United StatesShow Abstract
III-V semiconductors are promising candidates to replace Si channels in future high performance MOS devices. High quality gate dielectrics on III-V materials must have a high dielectric constant, sufficient band offset for low leakage current, and low interface trap state density (Dit). Achieving low Dit has been a major challenge for high-k/III-V interfaces. We have recently shown that in-situ plasma-based surface preparation treatments in atomic layer deposition (ALD) can achieve Dit in the low 1012 cm-2 eV-1 range for gate stacks with high-k HfO2 and ZrO2 dielectrics on In0.53Ga0.47As [1,2]. Such gate stacks can be scaled to achieve accumulation capacitance densities exceeding 3.5 mu;F/cm2 at 1 MHz (~ 3 nm physical thickness). Further scaling has proven difficult, due to high leakage currents and the presence of an Al-oxide interface layer with a low dielectric constant. Here we report on the use of higher-k Ti-oxides to replace the low-k Al-oxide interface layer. Such layers are obtained by a pre-deposition cleaning process that consists of cycles of nitrogen plasma and tetrakis(dimethylamino)titanium pulses . In combination with ZrO2 and/or HfO2 ALD gate dielectrics, this process gives rise to extremely scaled gate stacks with accumulation capacitance densities of more than 5 mu;F/cm2 at 1 MHz, low frequency dispersion in capacitance vs. voltage curves, low Dit, and low leakage currents. The chemical, physical, and electrical properties of Ti-oxide based interfacial layer are discussed. We also discuss the mechanisms by which low leakage is obtained despite the small band gap and conduction band offset between the Ti-oxide interface layer and the channel, and the role of interface dipoles in determining the properties of the gate stacks. Results for both n- and p-type In0.53Ga0.47As channels will be presented.
V. Chobpattana, T. E. Mates, W. J. Mitchell, J. Y. Zhang, and S. Stemmer, J. Appl. Phys. 114, 154108 (2013).
V. Chobpattana, T. E. Mates, J. Y. Zhang, and S. Stemmer, Appl. Phys. Lett. 104, 182912 (2014).
V. Chobpattana, E. Mikheev, J. Y. Zhang, T. E. Mates, and S. Stemmer, J. Appl. Phys. 116, 124104 (2014).
11:30 AM - *AA1.07
Time-Resolved X-Ray Photoemission Spectroscopy of the III-V/Oxide Interface during the ALD Process
Rainer Timm 1
1Lund University Lund SwedenShow Abstract
Atomic layer deposition (ALD) has been established as the main technique for creating MOS structures based on III-V semiconductors, which are highly promising both in planar and in nanowire geometry . In order to achieve superior device performance, a precise control and profound knowledge of the semiconductor/oxide interface is crucial, but not fully reached yet. One of the great challenges is to characterize the chemical reactions taking place at the interface between the III-V semiconductor, its native oxide, and the high-k dielectric material during the ALD process. X-ray photoemission spectroscopy (XPS) has successfully been used to investigate this interface before and after individual steps of the ALD reaction [2,3], but was until now limited to ultrahigh vacuum conditions.
Here I present ambient pressure XPS studies of the atomic layer deposition of HfO2 on InAs, using tetrakis(dimethylamino)hafnium (TDMA-Hf) and water precursors: By performing subsequent half-cycle steps of the ALD process within the reaction cell of an ambient pressure XPS system , we were able to monitor the slowed down ALD reaction by XPS and thus obtain fully in-situ and real-time XPS measurements of the high-k deposition on III-V semiconductors.
From the time-resolved investigation of the self-cleaning effect during ALD, we reveal several subsequent steps in the removal of different native As-oxides and the reduction of In-oxides. Furthermore, based on the observations during initial TDMA-Hf deposition, I will discuss separate phases of precursor chemisorption followed by precursor dissociation and ligand exchange reaction, which also depend on sample temperature. Accordingly, the surface chemistry of the ALD process seems to be more complex than previously expected.
 Johansson et al., IEEE EDL 35, 518 (2014)
 Timm et al., Appl. Phys. Lett. 97, 132904 (2010)
 Timm et al., Appl. Phys. Lett. 99, 222907 (2011)
 Schnadt et al. J. Synchrotron Radiat. 19, 701 (2012)
12:00 PM - AA1.08
Al Nitride for Improved Interface Passivation of III-V - Oxide Interfaces
Yuzheng Guo 1 John Robertson 1
1University of Cambridge Cambridge United KingdomShow Abstract
III-V semiconductor channels are one way to continue CMOS scaling to higher mobility substrates. The problem has been to passivate their interfaces effectively. Progress followed in-situ XPS studies of ALD growth of oxides [1,2], and a better understanding of the nature of interface defects . Al2O3 based gate oxides gave good performance, partly due to their diffusion barrier properties and partly because trivalent oxides allow valence matching across the III-V interface . However, Heyns  noted that Al2O3/III-V stacks have a lower overall reliability, due to more border traps. Various groups [5-7] found that nitridation of Al2O3 gate oxides would reduce Dit values. Here we study the origin of this effect.
Lin  found that for GaAs/oxide interfaces the As-As bond gave states in the upper gap and As dangling bonds gave states near the valence band maximum (VBM). We find that for AlN interfacial monolayers, any N-N bonds would spontaneously break, leaving only N dangling bonds (DBs). Nitrogen DBs give states at least 2 eV below the VBM, well away from the gap. These calculations are repeated for each III-V material, including pFET antimonides. Nitrogen states always lie well below VBM.
We find that the advantage of AlN interlayers is that they have a lower density of border traps. We find that O vacancies in Al2O3 can give 4 transition states across its band gap, some lying within the III-V gap. In contrast, the N vacancy in AlN gives no states within the III-V gap. Thus AlN will give lower trap densities. AlN also retains the diffusion barrier properties of Al2O3. AlN has fewer defect levels because its anion site, N vs O has higher symmetry. N has a tetrahedral site, so that its vacancy has only A1 and triply degenerate T2 levels with a wide separation between them, with the T2 state above the III-V conduction band edge. On the other hand, the O site in theta;-Al2O3 has a low symmetry. This breaks the T2 state into 3 separate defect states, some lying in the III-V gap.
1 M L Huang, et al, APL 87 252104 (2005)
2 C L Hinkle et al, APL 92 071901 (2008)
3 L Lin, J Robertson, APL 98 082903 (2011)
4 M Heyns, MRS Spring (2014)
5 V Chobpattana, et al, APL 102 022907 (2013)
6 T Aoki, et al, APL 105 03513 (2014)
7 Y Guo, L Lin, J Robertson, APL 102 091606 (2013)
12:15 PM - AA1.09
Self-Limiting CVD and ALD of An Electrically Passivating Silicon Seed Layer on InGaAs(001)-(2x4)
Mary E. Edmonds 1 Tyler Kent 1 Mei Chang 2 Jessica Kachian 2 Ravi Droopad 3 Evgueni Chagarov 4 Andrew C. Kummel 4
1University of California, San Diego La Jolla United States2Applied Materials Sunnyvale United States3Texas State University San Marcos United States4University of California, San Diego La Jolla United StatesShow Abstract
A broader range of MOSFET channel materials allowing better carrier confinement and mobility could be employed if a universal control monolayer (UCM) could be self-limiting CVD or ALD deposited on multiple materials and crystallographic faces. Si-OH is a leading candidate for use as the UCM because silicon uniquely bonds strongly to all crystallographic faces of InxGa1-xAs, InxGa1-xSb, InxGa1-xN, SiGe, and Ge. The Si-OH monolayer could be formed by self-limiting CVD or ALD deposition of an Si-H layer which can be functionalized with an oxidant to create the UCM Si-OH layer. The Si-H or Si-OH monolayer would be electrically passive if the bonding structure results in a charge balanced surface (i.e. obeys the electron counting model) because the Si-H or Si-OH monolayer would remove all dangling and dimer bonds. This study focuses on depositing a saturated Si-H monolayer via two separate self-limiting processes on InGaAs(001)-(2x4). XPS in combination with STS/STM were employed to characterize the electrical surface properties of the saturated Si-H layers on InGaAs(001)-(2x4). Density Functional Theory (DFT) modeling indicates missing dimer and ideal unit cells of the InGaAs (001)-(2x4) surface are electrically passivated by Si-Hx.
Self limiting CVD is a self limiting dose of the reducing ALD precursor; it is self limiting since reductants do not react with substrate back bonds. For the 375°C self-limiting CVD process, a decapped In0.53Ga0.47As(001)-(2x4) surface was dosed with 300 MegaLangmuir Si3H8 at 375°C. STM images of the (2x4) surface following the saturated Si3H8 dose at 375°C shows Si-Hx absorbs in a commensurate structure with average row spacing nearly identical to the (2x4) surface at 1.5 nm, consistent with III-V dangling bond elimination. A second process was tested using an ALD method. In this second process, the (2x4) surface was dosed with 21 MegaLangmuir Si2Cl6 at 400°C. The surface is terminated by SiClx and 500 Langmuir of atomic hydrogen is pulsed at 400°C to remove -Cl and terminate the surface with SiHx. For both processes, the XPS spectra following the saturated Si3H8 or Si2Cl6 dose shows the increase of the silicon 2p peak and decrease in the gallium 3p substrate peak, indicative of saturating coverage. Complete saturation is determined to occur once further dosing with Si3H8 or Si2Cl6 leads to no further increase in the silicon 2p or decrease in gallium 3p peak areas. Both processes employ high pressure pulses which protect from surface carbon and oxygen contamination. The Si-Hx surfaces achieved by both processes show identical STS results with the surface Fermi level (EF) shifting from the valence to the conduction band for p-type vs n-type samples consistent with an unpinned EF. DFT simulations are in direct agreement with STS results showing the surface EF remains unpinned, as the modeling indicates there is charge neutrality found in both the missing dimer and ideal (2x4) unit cells passivated by Si-Hx.
12:30 PM - AA1.10
The Effect of ALD Temperature on Border Traps in Al2O3 InGaAs Gate Stacks
Kechao Tang 1 Muhammad Adi Negara 1 Ravi Droopad 2 Paul C. McIntyre 3
1Stanford University Stanford United States2Texas State Univ San Marcos United States3Stanford Univ Stanford United StatesShow Abstract
For future high performance III-V n-channel MOS devices, In0.53Ga0.47As is a promising material for the channel due to its high electron mobility. Atomic layer deposited (ALD) Al2O3 has a large conduction band offset to InGaAs and can form a low defect-density interface with InGaAs.1 Therefore, Al2O3 has received attention as either a candidate dielectric layer for InGaAs nMOSFETs, or as a large band-offset interface layer interposed between the InGaAs channel and a higher-k dielectric such as HfO2.2 Apart from the well-known oxide/InGaAs interface charge traps that may pin the Fermi level of the channel, traps in the oxide layer, called border traps, may also reduce the charge in the channel and thus degrade the on-state performance of InGaAs MOSFET devices. In this presentation, we study the effects of various approaches to reduce the border trap density, such as variation of ALD temperature, post-gate metal forming gas (5% H2/95% N2) anneals (FGA).
Experimental methods employed include quantitative interface trap and oxide trap modeling3, 4 of MOS capacitor data obtained over a range of frequencies and temperatures. With the application of these models, we find that MOS capacitors fabricated using trimethylaluminum (TMA)/H2O at an ALD temperature of 120°C have a considerably lower border trap density (Nbt) while maintaining a similarly low interface trap density (Dit) compared to samples prepared with a more standard 270°C Al2O3 ALD temperature. Large-dose TMA exposure (pre-dosing) of the InGaAs(100) surface prior to Al2O3 ALD is also found to be an important step to guarantee stable electrical quality of the low temperature-deposited samples. To understand the nature of this ALD temperature effect, composition and bonding characterization methods such as XPS and SIMS are employed to probe the origin of the Nbt variation as a function of the structure of the Al2O3 layer. Besides altering the ALD temperature, the impact of other treatment methods on the Nbt, such as variations of H2/N2 forming gas anneal time and temperature, and application of bias-temperature stress, will also be discussed.
1. J. Ahn, T. Kent, E. Chagarov, K. Tang, A.C. Kummel, and P.C. McIntyre, Applied Physics Letters 103, 071602 (2013).
2. V. Chobpattana, T.E. Mates, W.J. Mitchell, J.Y. Zhang, and S. Stemmer, Journal of Applied Physics 114, 154108 (2013).
3. H. Chen, Y. Yuan, B. Yu, J. Ahn, P.C. Mcintyre, P.M. Asbeck, M.J.W. Rodwell, and Y. Taur, IEEE Transactions on Electron Devices 59, 2383 (2012).
4. Y. Yuan, B. Yu, J. Ahn, P.C. Mcintyre, P.M. Asbeck, M.J.W. Rodwell, and Y. Taur, IEEE Transactions on Electron Devices 59, 2100 (2012).
12:45 PM - AA1.11
Physical Properties Investigation of Arsenic Based III-V Materials Grown on Nanopatterned Si(100) Substrates
Romain Cipro 1 Mickael Martin