2025 MRS Spring Meeting & Exhibit

Workshop on Materials Opportunities in Microelectronics Packaging and Heterogeneous Integration

Monday, April 7
9:45 am – 5:00 pm
Summit, Level 3, Room 328

This one-day workshop aims to bring together leaders and practitioners from microelectronics packaging to discuss their perspectives on heterogeneous integration, with a focus on materials science. Following speaker tutorials and presentations, ask your questions to a panel of experts and conclude the day chatting with peers at a networking reception.

Heterogeneous integration (HI) involves combining chiplets using package-level interconnects. Unlike traditional system-on-chip (SoC) designs, which consolidate functions onto a single silicon chip, HI disaggregates these functions into smaller chiplets, which are then assembled using wires, solder bumps, micropillars and PCBs. This approach introduces materials such as metals, polymers and composites that are typically outside the fabrication facilities. As monolithic SoCs have grown larger, their yield rates have decreased due to manufacturing defects, leading to a trend toward integrating smaller chiplets through innovative packaging solutions.

The workshop will focus on identifying materials science challenges and opportunities within this new paradigm. For instance, thermal and latency issues may need to be managed over a significantly larger scale—10 to 100 times that of SoCs. Additionally, the diversity of materials and interfaces involved in product realization will increase. These factors will create new process–structure–property relationships, including defectivity, which will impact yield, throughput and reliability.

The networking reception is open to workshop attendees. 

Sponsored by: Applied Materials, Inc.

Secure Your Seat

Thank You to our Sponsors

Reception Sponsor

 

 

Workshop Sponsor

 

 

Workshop Sponsor

Start 

Title

Speaker 

Affiliation 

9:45 am

Advanced Packaging for Heterogeneous Integration

Ravi Mahajan

Intel Corporation

10:30 am 

Materials for Electrical and Optical Interconnects Toward Panel Scale 

Ning Li

The Pennsylvania State University

11:15 amMaterial and Process Challenges for Automotive Chiplet SystemsTanja BraunFraunhofer IZM

12:00 pm 

Break

1:30 pm

Materials Reliability in Power Electronic Packaging

F. Patrick McCluskey 

University of Maryland

2:15 pm

Advancing Packaging Technologies for Soft Electronics 

Seung-Kyun Kang

Seoul National University

2:40 pm 

Break

2:50 pm

Cryogenic Wiring Infrastructure for Quantum Systems 

Michael Beckley 

IBM Research 

3:15 pm

Thermal Metrology and Subsurface Evaluation of Heterogeneously Integrated Microelectronics

Amun Jarzembski 

Sandia National Laboratories 

3:40 pm

Break 

3:50 pm

Panel: Ravi Mahajan, Intel Corporation, Erik Hadland, Semiconductor Industry Association, Steven Verhaverbeke, Applied Materials, Inc., Nirmal Shankar Sigamani, Lam Research Corporation  

5:00 pm

Networking Reception sponsored by AMAT. Summit, Level 5, Overlook

Speakers

Ravi Mahajan

Intel Corporation

Ravi Mahajan is an Intel Fellow responsible for Assembly and Packaging Technology Pathfinding.  He also represents Intel in academia through research advisory boards, conference leadership and participation in various student initiatives. He has led Pathfinding efforts to define Package Architectures, Technologies and Assembly Processes for multiple Intel silicon nodes including 90 nm, 65 nm, 45 nm, 32 nm, 22 nm and 7 nm silicon. Mahajan joined Intel in 1992 after earning his PhD degree in mechanical engineering from Lehigh University. He holds the original patents for silicon bridges that became the foundation for Intel’s EMIB technology. His early insights have led to high-performance, cost-effective cooling solutions for high-end microprocessors and the proliferation of photomechanics techniques for thermomechanical stress model validation. His contributions during his Intel career have earned him numerous industry honors, including Semiconductor Research Corporation's 2015 Mahboob Khan Outstanding Industry Liaison Award, the 2016 THERMI Award from SEMITHERM, the 2016 Allan Kraus Thermal Management Medal and the 2018 InterPACK Achievement Award from The American Society of Mechanical Engineers (ASME), the 2019 “Outstanding Service and Leadership to the IEEE” Awards from the Institute of Electrical and Electronics Engineers (IEEE) Phoenix Section and Region 6, the 2020 Richard Chu ITherm Award and the 2020 ASME Electronic and Photonic Packaging Division (EPPD) Excellence in Mechanics Award. He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and currently Vice President of Publications and Managing Editor-in-Chief of the IEEE Transactions on Components, Packging and Manufacturing Technology.. He has long been associated with ASME’s InterPACK conference and was co-chair of the 2017 conference. Majahan is a Fellow of two leading societies, ASME and IEEE.  He was elected to the National Academy of Engineering in 2022 for contributions to advanced microelectronics packaging architectures and their thermal management.

Ning Li

The Pennsylvania State University

Ning Li is an associate professor in the Department of Electrical Engineering and Materials Research Institute at The Pennsylvania State University. He was a research staff member at IBM T.J. Watson Research Center from 2010 to 2022. His research experience includes nonvolatile memory devices for in-memory computing, optoelectronic devices for communications and interconnects, advanced packaging and heterogeneous integration, and high-frequency high-power devices. Li was awarded more than 250 U.S. patents, many High Value Patent Awards, and multiple Master Inventor Awards.  He has published in scientific journals and conferences including Nature Photonics, Nature Communications, Advanced Materials, Optical Fiber Communication (OFC), etc. His work has been featured on Nature Research Highlights, Semiconductor Today, etc. He received his BS and MS degrees from Tsinghua University in electronics engineering, and his PhD degree from The University of Texas at Austin in electrical and computer engineering.

Tanja Braun

Fraunhofer Institute for Reliability and Microintegration

Tanja Braun studied mechanical engineering at Technische Universität Berlin with a focus on polymers and micro systems, and joined the Fraunhofer Institute for Reliability and Microintegration (Fraunhofer IZM) in 1999. In 2013, she received her Dr-Ing degree from Technische Universität Berlin. Braun is Head of the System Integration and Interconnection Technologies Department. Recent research is focused on Fan-out Wafer and Panel Level Packaging technologies. In 2021, she received the Exceptional Technical Achievement Award from the Institute of Electrical and Electronics Engineers (IEEE) Electronics Packaging Society (EPS), and the International Microelectronics Assembly and Packaging Society (IMAPS) Sidney J. Stein Award for her work in the field of Fan-out Wafer and Panel Level Packaging. Braun is an active member of IEEE. She is member of the IEEE EPS Board of Governors (BOG) and is the IEEE EPS Vice President of Conferences.

F. Patrick McCluskey

University of Maryland

F. Patrick McCluskey is a professor of mechanical engineering at the University of Maryland and the Department’s Director of Undergraduate Studies. He has over 25 years of research experience in the areas of thermal management, reliability, materials and packaging of electronic systems. McCluskey has co-authored three books, five U.S. patents and nearly 200 peer-reviewed technical articles with over 4900 citations. He is a member of the Board of Governors of the IEEE Electronic Packaging Society, a Fellow of the International Microelectronics Assembly and Packaging Society (IMAPS), and a member of The American Society of Mechanical Engineers (ASME), American Society for Engineering Education (ASEE), and The Minerals, Metals & Materials Society (TMS). McCluskey is the principal investigator for an Advanced Research Projects Agency-Energy (ARPA-E) COOLERCHIPS project on the development of co-simulation software for the design of high-performance computing data centers, and directs the universities' NASA Parts program and SCALE radiation hardness workforce development efforts.

Michael Beckley

IBM Research

Michael Beckley is currently a senior hardware engineer for IBM Research, New York. He holds an MS and BS degrees in chemical engineering from the University of Rochester.  His work focuses on signal delivery and packaging for superconducting quantum computing hardware. His background also includes thin-film development, semiconductor integration, cryogenics and microwave engineering.

Seung-Kyun Kang

Seoul National University

Seung-Kyun Kang is an associate professor in the Department of Materials Science and Engineering at Seoul National University (SNU) and Head of the Materials Analysis Center at the Research Institute of Advanced Materials. He earned his BS (2006) and PhD degrees (2012) from SNU, specializing in mechanical properties of multiscale materials. He conducted postdoctoral research on bioelectronics under Prof. John A. Rogers at the University of Illinois at Urbana-Champaign (UIUC) and Northwestern University. Before joining SNU in 2019, he was an assistant professor at the Korea Advanced Institute of Science and Technology (KAIST). Kang has published over 80 peer-reviewed papers in Nature, Science Advances, and Advanced Materials. His research spans materials science, electronics, mechanics and bioengineering, focusing on wearable, implantable and bioresorbable medical devices, neuromorphic devices and soft robotics. Beyond applications, he investigates mechanical failure analysis, corrosion, degradation and mechanical testing of advanced materials.

Erik Hadland

Semiconductor Industry Association

Erik Hadland is the Director of Technology Policy at the Semiconductor Industry Association (SIA), where he is responsible for the association’s research, development and technology activities as well as its education and workforce development efforts. Prior to SIA, Hadland was an American Association for the Advancement of Science (AAAS) Science and Technology Policy Fellow at the U.S. Department of Energy (DOE), where he served as Advisor to the Director of the Office of Science. In this capacity, he project managed briefings to Congress on critical and emergent technologies, advised on matters of place-based innovation and technology transfer, and co-facilitated the Department’s Microelectronics Working Group. Prior to the DOE, Hadland was a senior logic technology development engineer at Intel, piloting first-of-a-kind annealing modules and processing conditions for Intel’s next-generation logic products. He earned his PhD degree in solid state chemistry from the University of Oregon, where he studied novel synthesis schemes for metastable 2D semiconductor compounds.

Amun Jarzembski

Sandia National Laboratories

Amun Jarzembski started as a staff scientist at Sandia National Laboratories in 2021 after completing a PhD degree in mechanical engineering at The University of Utah and a postdoctoral appointment at Sandia under Thomas Beechem. Part of Jarzembski's research portfolio includes novel optothermal metrology techniques, focusing on thermal property extraction of subsurface materials/features.

Steven Verhaverbeke

Applied Materials, Inc.

Steven Verhaverbeke is currently Managing Director at Applied Materials, Inc.. He leads the Wafer Level Substrate activities in Applied Materials’ CTO Office and is the Principal Investigator on the National Advanced Packaging Manufacturing (Si-Core Substrates) Program (NAPMP). Prior to joining Applied Materials in 2000, he was a director at CFM Technologies, a semiconductor Cleans Equipment maker. Verhaverbeke received his PhD degree from KU Leuven after which he did a postdoc at Tohoku University.

Nirmal Shankar Sigamani

Lam Research Corporation

Nirmal Shankar Sigamani is a process development manager of the Sabre 3D product line at Lam Research Corporation. He earned his PhD degree in mechanical engineering, specializing in materials research, from The Pennsylvania State University before joining Lam Research in 2015. Leading a team focused on advancing semiconductor wafer fabrication processes, Sigamani plays a key role in enhancing wafer-level packaging (WLP) applications. His work primarily impacts copper pillar, redistribution layers (RDLs), underbump metallization (UBM), lead-free C4 bumping, Cu/SnAg and Ni/Au microbumps, high-density fan-out (HDFO) applications (megapillar, RDL, 2-in-1 via, micropillars). He has been spearheading WLP applications with a strong focus on high bandwidth memory (HBM), a critical component in AI computing. With expertise in addressing challenges in metal electrochemical deposition (Cu, Ni, SnAg and Au), Sigamani also identifies opportunities for future industrial advancements including reducing cost of ownership, minimizing defects and achieving reliable and void-free microbumps and solder joints.

Organizers

Stanley S. Chou

Sandia National Laboratories

Stanley S. Chou is a senior scientist at Sandia National Laboratories (SNL) and the Domain Chief Engineer for Microsystems Engineering, Science, and Applications (MESA) Post-Fab Technologies. In this role, he is responsible for the Laboratory's microelectronic packaging and assembly for National Security, ensuring that critical technologies are reliable and effective. Chou's interests include exploring new materials, synthesis, integration and reliability in real-world environments. He enjoys collaborating with teams in the laboratory, as well as with industry and academia, to address critical scientific and engineering gaps essential to the Laboratory's mission. Chou received his PhD degree in materials science and engineering from Northwestern University.

Subhash L. Shinde

Bio coming soon