Spin-transfer torque random access memory (STT-RAM) is an emerging memory technology that possesses a unique combination of density, speed, endurance, and non-volatility. It was recognized very early on that a free layer with perpendicular magnetic anisotropy (PMA) would greatly reduce the switching voltage, compared to an in-plane magnetic free layer with the same thermal stability. However, only recently were PMA materials successfully incorporated into STT devices. This talk will give a brief overview of STT-RAM utilizing perpendicular magnetic materials and then describe work at IBM in this field.
The PMA materials we used included a bottom CoFeB free layer with interfacial PMA and top reference layer with Co|Pd based multilayer. Tunneling magneto-resistance (TMR) ratio up to 98% was achieved in these PMA stacks, when a thin Ta spacer layer was incorporated between the CoFeB interfacial layer and the Co|Pd multilayer reference layer. X-ray diffraction measurements showed that the Ta spacer layer promotes the CoFeB interfacial layer to crystallize into (001) texture during annealing. Electron energy loss spectra suggested that the Ta spacer layer provided a very effective diffusion barrier during annealing to inhibit Pd diffusion to the CoFeB|MgO interface. Both factors were known to be critical to achieve high TMR. On the patterned device level, magnetic tunnel junctions of ~ 100 nm diameter showed strong perpendicular magnetization, two remnant states, and good spin torque switching with good thermal stability. In particular, the switching speed was shown to be 8x faster than for in-plane magnetized devices [1]. Deeply scaled devices with size down to 20nm were also fabricated and characterized. The switching current decreased with device size as expected, down to 30 uA for a 20 nm device. A very high spin torque efficiency (~1 kBT/µA), defined as the ratio of activation energy to switching current, was observed in 20nm devices, approaching the macrospin model spin torque efficiency limit [2].
[1] D. C. Worledge et al. APL 98 022501 (2011)
[2] M Gajek et al. APL 100 132408 (2012)

Magnetization reversal using circularly polarized light provides a way to control magnetization without any external magnetic field and has the potential to revolutionize magnetic data storage [1]. So far, optical magnetization reversal has been demonstrated only for GdFeCo, a rare earth-transition metal alloy with modest perpendicular magnetic anisotropy [1-3]. Crucially, for ultra-high density data storage, optically recordable magnetic materials exhibiting larger perpendicular magnetic anisotropy are needed. Staying in the class of rare earth- transition metal alloys, the most straightforward solution would be to replace Gd with Tb, since Tb has a significant orbital momentum. Indeed, ferrimagnetic Tb_xCo_1-x alloy films exhibit strong perpendicular magnetic anisotropy and have been already used in conventional magneto-optical recording. Here, we study the feasibility of all-optical switching on Tb_xCo_1-x films which exhibit a strong perpendicular magnetic anisotropy, varying the Tb composition from x=12% to x=34%. We evidence all-optical magnetization switching for different Tb_xCo_1-x ferrimagnetic alloy compositions using femtosecond- and picosecond-laser pulses and demonstrate all-optical switching for films with anisotropy fields reaching 6T corresponding to anisotropy constants of 3x10⁶ ergs/cm³ [4]. Our results show that all-optical switching depends on both the Tb concentration and the properties of the exciting laser pulse. Moreover, optical magnetization switching is observed only for alloy compositions where the compensation temperature can be reached through sample heating. These experiments demonstrate the potential of the use of circularly polarized light for magnetic data storage technology and provide a crucial piece of information for understanding the physics of optical switching.
[1] C.D. Stanciu, F. Hansteen, A.V. Kimel, A. Kirilyuk, A. Tsukamoto, A. Itoh,and T. Rasing, Phys. Rev. Lett. 99, 047601 (2007)
[2] D. Steil, S. Alebrand, A. Hassdenteufel, M. Cinchetti, and M. Aeschlimann, Phys. Rev. B 84, 224408 (2011)
[3] S. Alebrand, A. Hassdenteufel, D. Steil, M. Cinchetti, and M. Aeschlimann, Phys. Rev. B 85, 092401 (2012)
[4] S. Alebrand, M. Gottwald, M. Hehn, D. Steil, M. Cinchetti, D. Lacour, E. E. Fullerton, M. Aeschlimann, and S. Mangin, Appl. Phys. Lett. 101, 162408 (2012)

There is widespread interest in exploring new chalcogenide materials with low-dimensional and flexible crystal structure. Such compounds are attractive platforms for the integration within a single material, of multifunctionalities such as ferromagnetism and semiconducting or metallic conductivity, two properties that are generally difficult or impossible to combine in a conventional inorganic solid. The ability to develop such bi-functionality within a single material is of tremendous fundamental importance and could impact next-generation technologies such as spintronics, thermoelectrics, sensors. Growing interest in the development of spintronic technologies- which utilize both the charge and spin of electrons - has been revitalized by the discovery of ferromagnetism in Mn-doped GaAs [1]. However, the realization of practical devices based on Ga1-xMnxAs or other dilute magnetic semiconductors has been inhibited by their low ferromagnetic transition temperature (Tc). Enhancing ferromagnetism in the cubic Ga1-xMnxAs for example, requires the ability to control the distribution of Mn atoms in the GaAs structure, which is difficult to achieve the high symmetry cubic structure of GaAs. This makes it difficult to independently control the ferromagnetism, carrier type, carrier density and mobility in the materials and therefore, severely impedes our ability to study and understand the mechanism of carrier-mediated ferromagnetism necessary for efficient spintronic materials. Multinary metal chalcogenides such as Pb4Sb4Se10, Pb4Sb6Se13 and Pb6Sb6Se17 because of their low symmetry as well as the diversity and flexibility of their framework structures (dimensionality varies from 1D to 3D), are very attractive platform for the design and manipulation of new low - dimensional high Tc ferromagnetic semiconductors through selective substitution of some Pb atoms by magnetic transition metal elements such as Mn, and Fe. We will discuss some of our recent findings in the (Fe,Mn)/Pb/Sb(Bi)/Se systems. Emphasis will be placed on structure - composition - property relationships in FexPb4-xSb4Se10 [2], FeSb2-ySnySe4 [3], and FeBi2-ySnySe4 phases.
[1] H. Ohno et al. Appl. Phys. Lett. 69, 363 - 365 (1996).
[2] P. F. P. Poudeu; et al. J. Am. Chem. Soc., 132, 5751 - 5760 (2010).
[3] H. Djieutedjeu et al. Angew. Chem. Int. Ed. 49, 9977 - 9981 (2010).
* [email protected] (PFPP)

Zinc Oxide (ZnO) nanowire (NW) field effect transistors (FETs) have been increasingly popular recently as promising building blocks for nanotechnology. ZnO NWs have a relatively good metal electrode-semiconductor ohmic contact, which results in a high device fabrication yield. Currently, organic field effect transistors (OTFTs) with ferroelectric materials have been researched extensively owing to their nonvolatile memory and nondestructive readout and flexible application [1]. In particular, ferroelectric memory NW FETs is still very rare [2], while their thin film counterparts are relatively widespread [3].
This work demonstrates the feasibility of flexible and conventional nonvolatile memories based on a ZnO NW FET configuration. Single NW and network NW FET configurations have been compared in terms of their associated ferroelectric memory properties.
Hereby, ZnO NWs have been grown via chemical vapor transport with their dimensions ranging from 100-200 nm in diameter and up to 10 um in length. Our conventional ZnO NW FETs on highly doped thermally oxidized silicon substrates show a high on to off current ratio of up to 106-107 with an anticlockwise hysteresis loop present on the transfer curve. With ferroelectric material, the device showed at least 5 volts memory window and can be tuned by varying the gate voltage sweep range. Flexible substrates with high temperature and solvent exposure tolerance have been utilized for fabrication of ZnO NW FETs with a 200 nm thick PVDF-TrFE ferroelectric material. The top-gate configurations have been prepared by spin coating a 5 wt% solution of PDVF-TrFE powder (70/30 molar ratio) in cyclohexane. After spin coating, the ZnO NW FETs with PVDF-TrFE thin films have been thermally cured in a vacuum oven at 160°C for 2 hours. Memory effect of flexible device was verified by the counterclockwise direction of the transfer curve hysteresis of the devices. The role of flexible substrate treatment and memory characteristic damage on bending behavior will be discussed.
[1] T. Sekitani et al., Science, Vol. 326, 1516, (2009)
[2] D. Yeom et al., Nanotechnology, 19, 395204, (2008)
[3] K.H. Lee et al., Adv. Mater., 21, 4287, (2009)

Ferroelectric control of ferromagnetism is a highly attractive device concept with potential applications in data storage and spintronic logic elements. Of particular interest are hetero-layered ferroelectric/ferromagnetic systems with charge-mediated coupling with FET architecture.
Further to our proof-of-concept results showing ferroelectric control of ferromagnetic Curie temperature in magnetic semiconductors here we show a variety of non-volatile effects associated with multiferroic coupling. One of the most spectacular manifestations of this coupling is a ferroelectric control of magnetic domain propagation. Both magnetotransport and magnetooptical experiments clearly demonstrate that ferroelectric polarization domains strongly influence ferromagnetic domain nucleation and kinetics resulting in superimposed ferroic patterns strongly coupled by electric field.
In alternative approach we show a deterministic ferroelectric switching of the magnetotransport anisotropy in magnetic semiconductor (Ga,Mn)(As,P) channels. The persistent field effect is shown to be capable of strongly modulating the AMR magnitude. Furthermore, ferroelectric gate switching has a profound impact on the nature of AMR, changing the symmetry of the effect and enhancing/suppressing the crystalline component of AMR.
Recent progress in ferroelectric control of ferromagnetism in metals at room temperature suggests that our results are highly relevant to multiferroic non-volatile memory devices.

Nonvolatile programmable-logic array using a complementary atom switch (CAS) has been demonstrated on a 65-nm-node test chip. The CAS consists of two two-terminal atom-switches connected in series with opposite direction. To achieve a high OFF-state reliability, the programming voltage is required to be high for conventional two-terminal switch. The CAS improves the OFF-state reliability while reducing the programming voltage. Since two-terminal atom switch has a bipolar current-voltage characteristics, either of two switches in CAS is highly durable against a stress voltage biasing during OFF-state. Each switch element is sequentially programmed by applying a voltage between two terminals.
The function block in CAS-based programmable logic array consists of two 4-input LUTs (look-up tables) and flip-flops. The cell has two routing wire segments of length 2 for each direction, and 19x16 crossbar switch is used for connecting between the function block and wire segment. Totally, 368-b CAS per cell was used for the crossbar switch and also data memory of LUT. Various logics were realized by synthesizing RTL codes and mapping the configurations into CAS-based programmable cell array. The configuration data was obtained from arbitrary RTL description utilizing in-house cluster packing and placement/routing tool chain. 2-bit full adder and 4-bit synchronous counter were synthesized and configured. The expected pattern was generated from the test-bench code in RTL source and the correct output pattern was successfully confirmed by comparing to expected pattern. We also confirmed that the programmed bits in the crossbar and the LUT were in ON-state without write disturb, whereas the all CAS have high resistive state in the initial state.
CAS is a promising candidate to realize a nonvolatile programmable logic with low power consumption and high performance. Dynamic power is critical issue for the conventional programmable logic. The CAS, which has a low input capacitance and small footprint, has reduced the dynamic power.
This work is supported by the Ministry of Economy, Trade and Industry (METI) and New Energy and Industrial Technology Development Organization (NEDO) in Japan. A part of the device processing was operated by Innovation Center for Advanced Nanodevices (ICAN), National Institute of Advanced Industrial Science and Technology (AIST), Japan.

The development of artificial neural networks (ANNs) based on emerging non-volatile memory, such as metal oxide memristors, has attracted an increasing interest recently. In the simplest form of such ANNs, the neurons are implemented with conventional (complementary metal-oxide-semiconductor) technology and interconnected by memristors functioning as artificial synapses. While there are number of recent proof-of-concept demonstration for synaptic operation by single memristive devices, demonstration of even simple functionality memristor-based ANN remains challenging and have yet to be reported. Here, we demonstrate pattern classification by a single-layer perceptron network implemented with hybrid crossbar circuits. 20 synaptic weights, which are realized by Pt/TiO2-x/Pt memristive devices with sub-20-nm-scale active region are successfully trained by ex-situ and in-situ method. In the first case, the appropriate conductance of each memristor is calculated on the precursor software-based network and then imported sequentially to the crossbar circuits using variation-tolerant programming algorithm. In the second case, the weights are adjusted in parallel following perceptron learning rule by applying voltage pulses from pre-synaptic and post-synaptic neurons. Both ex-situ and in-situ methods work satisfactory despite significant variations in switching behavior of memristive devices as well as half-select and leakage problems in crossbar circuits. The demonstrated results give hope for much anticipated efficient implementation of ANNs and pave the way towards extremely dense and high performance information processing systems.

Reversible memristive switching phenomena have been extensively studied by many groups in a variety of materials systems for possible applications including nonvolatile memory, logic circuits and neuromorphic computing. Almost all of the anion-based resistive switching materials reported so far have been insulating/semiconducting metal oxides because of the wide range of their electrical properties and their exquisite dependence on doping concentrations. However, non-oxide ionic insulators/semiconductors that may also exhibit memristive switching behavior can be made from a much larger material pool that, with the exception of the chalcogenides, has not been extensively explored. Obvious examples are semiconducting nitrides, which have been intensively studied for photonics applications but not much for memristive phenomena.
Here, we demonstrate resistive switching in nitride memristors in a manner similar to the oxides. The switching material is an AlN film, deposited by plasma enhanced atomic layer deposition, and the electrodes can be TiN, Pt or Al. The Al-N system has a very simple phase diagram, which is considered to contribute to the high switching endurance displayed by the Ta-O and Hf-O oxides that posses similar phase diagrams. A variety of materials characterizations were performed to determine the structure, composition and impurities of the AlN films and ensure that the observed switching did not arise from inadvertent oxide contamination and to shed light on the mechanism of nitride switching. We have been successfully measured ultra-high switching speed in these nitride memristors, where voltage pulse of sub- 100 ps duration switches the AlN memristor ON and OFF with opposite voltage polarities. The scalability of nitride memristors is demonstrated at 50nm scale. Detailed switching mechanisms will be discussed. The demonstration of ionic switching behavior in nitrides could open up an entirely new area in resistance switches with significant opportunities.

In several correlated-electron materials, there are microscopic interactions among degrees of freedom including lattice, charge, orbital and spin, which show up as phase transition through various external stimuli. VO2, in particular, undergoes a first order Mott transition at about 340K because of both, on-site and lattice Coulomb repulsion, accompanied by a Peierls structural phase transformation from a monoclinic insulator to a half filled rutile metal. The transformation has been shown to be driven by temperature, pressure or strain on the lattice, charge induction and optical excitation; while the transition temperature can be controlled by doping, electric field and post annealing. A Mott memristor is a two terminal device in which such a Mott transition material is interposed between two metallic electrodes and is distinguished by its volatile switching behavior. Mott memristors have gained interest recently because of applications in computing and non-volatile memory including the neuristor: an electronic analog of an axon used to provide a lossless signal transmission and universal computation.
In electrical devices made of VO2 there have been many efforts to distinguish the contributions of Joule heating and electric field to drive the switching and to distinguish the occurrences of the electrical switching and structural transition. There have been several reports in recent literature on the switching being driven predominantly by electric field, and not Joule heating, when the field is in the order of 10^5 - 10^6 V/m, using a wide range of indirect evidence. Here, we show direct evidence to the contrary in planar devices of similar geometry, where we observe switching driven exclusively by Joule heating and eliminate all effects of electric field in switching for electric fields in an identical range. This is achieved by imaging the blackbody emission from the devices throughout the switching process and by studying the temperature-dependent current-voltage characteristics. We quantitatively reproduce these results with numerical finite-element simulations that accounts for Joule-heating.
We study the associated Peierls transformation in the crystal structure with in-situ X-ray absorption spectroscopy and Scanning Transmission X-ray Microscopy. Using these, we show filamentary structural transformation coincident with the localized Joule-heating-driven temperature observed with blackbody emission mapping. We also observe a hysteresis in the structural transition with temperature, on a uniformly heated film, and correlate it to the resistance-temperature data.

Among the resistance switching materials studied so far, tantalum oxide—when grown in the proper materials stack, composition, and structure—shows favorable characteristics from the standpoint of technological use. Several research groups have studied this system and reported demonstrations of high endurance, high speed with low energy switching, multi-level analog states, threshold switching to reduce sneak paths in crossbars, and long retention time. Meanwhile, our physical characterization of these devices showed the development of localized conductance channels, within which the switching material remains amorphous, but undergoes modifications of the Ta:O ratio [1]. We have showed [2] that the transport in the films can vary from metallic to variable range hopping to insulating as the oxygen percentage increases, and have argued that this provides the state variable and operating principle for tantalum oxide devices.
Leveraging the microphysical picture, we developed a compact, predictive (SPICE) model for the electrical behavior and response of the devices. To derive this, we performed an ensemble of switching measurements, including time dynamics across nine decades in order to deduce the underlying state equations describing the switching in Pt/TaOx/Ta memristors. Compact equations were found which provided good agreement to the measured data across several devices studied. The resulting model, while being predominantly phenomenological, nonetheless adds some insight into the underlying physical processes in operation during the switching, and shows an interplay between voltage (field) and heating (power) which is asymmetric for ON versus OFF switching. Finally, the implications for read and write circuitry is evaluated in light of the model, and the expected trajectory for performance in terms of switching times and energy consumption is also discussed.
[1] F. Miao, et al., Adv. Mater. 23, 5633 (2011).
[2] I. Goldfarb, et al., Appl. Phys. A 107, 1 (2012).

Compared with the un-doped HfO2, the Zr-doped HfO2 (ZrHfO) is a more suitable
high-k gate dielectric material for the nano-size MOSFET because of its lower equivalent oxide thickness, lower interface state density, and higher amorphous to crystalline transition temperature [1]. The ZrHfO high-k film can also replace the SiO2 as the tunnel and control oxide layers in the nonvolatile memory devices because of the above advantages. CdSe, which is a n-type semiconductor, can be embedded into the ZrHfO dielectric as the charge trapping medium because of its large work function, i.e., 4.8 to 5 eV [2]. In this paper, the CdSe embedded ZrHfO MOS capacitors were prepared on the p-type Si wafer using the one pumpdown sputtering process followed by the 800C post deposition annealing step. The crystalline CdSe in the sample was confirmed from the XPS spectrum, i.e., Cd 3d5/2 at BE 405.1 eV, Cd 3d3/2 at BE 411.9 eV, and Se 3d at BE 53.7 eV [3]. The nonvolatile memory characteristics were demonstrated from the C-V and J-V hysteresis curves. When the gate voltage was sweep range of -6V to +6V to -6V, a large flat band voltage of 0.96 V was obtained while a small value of 0.04 V was detected in the control sample, i.e., ZrHfO without the embedded CdSe. Both electrons and holes could be trapped by the embedded CdSe site depending on the polarity of the stress voltage. The J-V curve showed two peaks corresponding to the flat band voltage location and the Coulomb blockade phenomenon [4]. The control sample did not show these two peaks. More than 56% of the trapped charges were retained after 10 years at room temperature. A detailed study on the charge location and the temperature effect on the retention characteristics will be included in this paper. In summary, the CdSe embedded ZrHfO film can trap a large number of charges and retain them for a long period, which makes it a suitable gate dielectric material for the nonvolatile memory device.
This research was supported by NSF CMMI 0926379 project.
1. J. Yan, Y. Kuo, and J. Lu, Electrochem. Solid-State Lett., 10, H8199 (2007).
2. N. I. Dovgoshei, M. V. Shtilikha, and D. V. Chepur, Izvestiya VUZ. Fizika, vol. 11, p. 132, 1968.
3. X. S. Peng, J. Zhang, X. F. Wang, Y. W. Wang, L. X. Zhao, G. W. Meng, L. D. Zhang, Chem. Phys. Lett. vol. 343 p. 470, 2001.
4. Xi Liu, C. H. Yang, Y. Kuo, and T. Yuan, Electrochem. Solid-State Lett., 15, H1 (2012).

The charge transport behavior in ZnO nanowires (NWs) with Pt-Fe2O3 core-shell nanoparticles (NPs) was investigated. The ZnO NWs with the diameter of ~30 nm and the length of ~5 µm were synthesized via a template-less and surfactant free hydrothermal method. The Pt-Fe2O3 core-shell NPs were chemical synthesized through the preferential oxidation of Fe and subsequent piled-up of Pt into the core in the colloidal solution. The NPs have a diameter of ~ 15 nm with the core of ~3 nm. The NPs were attached on the ZnO NWs by repeating dip-coating processes during which the NPs adsorbed on the NWs&’ surface through van der Waals interaction. The charge transport behavior was examined in metal/NPs-attached NWs/metal and thin film transistor structures with NWs channel, where the conductivity of NWs changes due to the presence of NPs through the effects of electrical charging, local resistance change, and so on. In this presentation, the detailed electrical charge transport behaviors in NPs-attached ZnO NWs and the potential application to nonvolatile memory devices will be discussed.

Multi-bit operation in Non-Volatile Memory (NVM) Metal Oxide Semiconductor capacitors (MOSCAP) is feasible by controlled charging of multiple Floating Gates with defined Gate voltage bias ranges. We demonstrated controlled charging over double layer Pt nanoparticle (NP) floating gate devices resulting in a multi-step programming. Pt NPs were fabricated using a unique tilted target sputter deposition method where the incident inflight metal atom density is varied by changing the target angle of the sputtering system. Due to this change in inflight metal atom density, the thermalization effects are modified to get a wide range of control over the size and inter-particle distance of the Pt NPs with a near homogenous size distribution. Two layers of this ultra-fine Pt NP with different size configurations in the sub-2 nm regime were sandwiched between different thicknesses of Al2O3 tunneling and separation layer. Optimum size and inter-particle distance of Pt NP were varied control the self-capacitance of the NP and their associated Coulomb charging energy. The tunneling and separation layer thicknesses were also varied to controllably tunnel electrons out from the first Pt NP layer to the second Pt NP layer demonstrating a highly controllable and efficient charging phenomenon. The best configuration of controlled charging behavior and observation of multi-step programming effect in the memory window was attained for devices with 3 nm Al2O3 tunneling, 0.54 ± 0.16 nm Pt NP with 4.65 ± 2.09 nm inter-particle distance (first layer Pt NP), 3 nm Al2O3 separation and 1.08 ± 0.22 nm Pt NP with 2.75 ± 1.05 nm inter-particle distance (second layer Pt NP). For this configuration, the memory window saturated for the first Pt NP layer over a programming bias range of 7 V to 14 V. Beyond 14 V the second Pt NP layer starts charging accounting for an increase in memory window exhibiting a multi-step memory window. We also demonstrated reliable charge retention properties for these devices in par with industry standards. This dependable and controllable layer-by-layer charging behavior suggests possible integration with CMOS based devices, may be even for the 25 nm transistor technology.

Traditionally, bulk nanocomposites of electrically conducting particles and insulating polymers are categorized as either insulating or conducting when the nanoparticle concentration is below or above the percolation threshold, respectively. We recently presented the first examples of reversible resistive switching in bulk, glassy polymer nanocomposites.[1, 2] At compositions near the electrical percolation threshold, silver nanowire-polystyrene nanocomposites demonstrate reversible resistive switching upon increase voltage at room temperature. We proposed that resistive switching in these materials is the result of the field-induced formation of silver filaments that bridge adjacent nanowire clusters, extending the percolation network and decreasing the sample's bulk resistivity. This hypothesis is further supported by our temperature-dependent studies wherein the filaments persist below 100K. In order to further understand the resistive switching mechanism in these systems and explore possible applications, we have designed and fabricated single-gap nanowire devices comprised of lithographically-defined metal lines separated by polymer-filled nano-gaps. Using these devices, the complexity of the bulk device is significantly reduced as the switching mechanism between a single polymer-mediated metal-nanowire junction is isolated. Moreover, the sample geometry enables imaging. We have successfully demonstrated reversible resistive switching in our nano-gap Ag/PS devices when the gap size is 20 - 100nm, observing highly reversible switching behaviors in some samples with high on/off ratios (>10^3) for over 50 cycles. These preliminary results demonstrate that the resistive switching observed in our bulk Ag nanowire/polystyrene nanocomposites is achieved in a single isolated nanowire-nanowire polymer mediated junction. In addition, preliminary ex-situ high resolution imaging of the devices shows significant gap remodeling after a switching event, implying that the switching mechanism is linked to some form of electromigration of Ag electrodes. This finding is consistent with the filamentary conduction hypothesis proposed in the bulk case. Additional ex- and in-situ characterization studies to elucidate observed trends in the nano-gap devices are in progress.
References:
[1] White, S. I.; Vora, P. M.; Kikkawa, J. M.; Fischer, J. E.; Winey, K. I. Advanced Functional Materials. 2011, 21,233-240.
[2] White, S. I.; Vora, P. M.; Kikkawa, J. M.; Fischer, J. E.; Winey, K. I. Journal of Physical Chemistry C. 2010, 114, 22106-22112.

Organic field-effect transistor (OFET)-based memory is considered as promising candidate for realizing the ultimate goal of organic flash memory because of its nondestructive read-out, complementary integrated circuit architectural compatibility, and simple transistor realization. In this study, we demonstrate air-stable low voltage flexible nonvolatile memory transistors by embedding gold nanoparticles (Au NPs) in poly(methyl methacrylate) (PMMA) as charge storage element. The solution processability of the nanocomposite is suitable for low-cost large area processing on flexible substrates. The memory transistor exhibits a memory window of 2.1 V, long retention time with low operating voltage (le; 5 V). The memory behavior has been tuned via varying the composition of the fillers (Au NPs), which offers relatively easy processability for different flexible electronics application. The electrical properties of the memory devices are found to be stable under bending. These findings will be of value for low cost and low voltage advanced flexible electronics.

During the last years, a big variety of memory concepts have been presented. Resistive switching based memory is doubtless one of the most promising emerging non-volatile memory technologies. In particular using organic semiconductors (OSC) as active memory material opens up the possibility for low-cost, large-scale and high-throughput fabrication processes such as ink-jet printing. Moreover, excellent performance parameters (on/off-ratios, cyclability and retention times) are already reported.
While for many OSC based devices, such as organic light emitting diodes (OLEDs) or organic photovoltaic devices (OPVs), the operation mechanism is well understood and the technology is on or even beyond the step to commercialization, there are still open questions in the field of resistive memory devices based on OSCs.
Apart from the most simple OSC memory device architecture - an electrode/OSC/electrode ‘sandwich&’ structure - also electrode/OSC nanoparticle blend/electrode and electrode/OSC/metal/OSC/electrode multilayer structures can be found in literature, mostly exhibiting similar current-voltage characteristics (i.e. unipolar resistance switching, N-shaped IV-curve with a broad region of negative differential resistance and the presence of a distinct threshold voltage).
The origin of the electrical bistability in this kind of assemblies is intensely debated in the community. Mechanisms like charging/de-charging of the embedded metal particles, charge transfers in donor-acceptor complexes and the formation/rupture of conducting filaments are currently under consideration to explain the switching behaviour.
In this contribution, we present a set of experimental results obtained for single layer, multilayer and blend devices, employing molecular n and p conducting materials and different metal nanoparticles. In particular, the response of the memory device to additional excitation with light of different intensities and wavelength was investigated and gives new insight into the working mechanism of the presented devices.

Spin coated poly(N-vinylcarbazole) (PVK) sandwiched between thermal evaporated Aluminium electrodes on a glass substrate showed Write Once Read Many times (WORM) characteristics. The pristine devices were in the low resistance ON state exhibiting ohmic behavior and at a voltage near 2V, they switched abruptly to the high resistance OFF state showing space charge limited current (SCLC) with shallow traps. We suggest that the rupturing of metallic filaments due to Joule heating may explain the effect. The ON/OFF ratio was 108 and the states endured for 1000s, demonstrating the possibility of high performance, low cost WORM memory devices using PVK.

In recent years, fabrication of non-volatile memory devices using a combination of inorganic/organic materials has attracted a great deal of interest in the scientific community. Among different possible structures, resistive memories are particularly promising and interesting, thanks to some advantages such as low operation voltages and simple processing.
In this work, the performance of hybrid organic/inorganic resistive non-volatile memories prepared using various methods and materials have been investigated. Each memory element is a two-terminal structure, obtained by sandwiching a metal nanoparticles (NPs) interlayer between two organic semiconductor layers. The two semiconductor layers are contacted by means of two metal electrodes. Different material combinations were tested. In particular, electrodes were fabricated using inorganic materials like aluminum, gold or ITO. Two different types of organic semiconductors, such as N1400 (Polyera, deposited both by vapor or liquid phase) and Poly(N-vinylcarbazole) (PVK) (deposited by liquid phase), were tested. Finally, different metals, as gold and aluminum, were employed for defining NPs layer in the sandwiched structures. In particular, various growth rates were tested for NPs deposition.
Interestingly, all the tested configurations showed a bistable behavior: the devices typically start from a high resistive state and can be switched to a low resistive state by applying a proper switching voltage that generally ranges between 2.5 and 3.5 V. On/off current ratios in the range of 10^2 (recorded at 1 V), with typical retention times ranging from 10^4 to 10^5 seconds, were obtained.
Moreover, for understanding the conduction mechanisms of the devices, their electrical performances were related to the material morphology, structural and chemical properties. In particular, the metal NPs interlayer was characterized by High Resolution X-ray Photoemission Spectroscopy (HR-XPS), which allowed determining the metal content, studying the metal-organic interface and characterizing the metal NPs oxidation shell. HR-XPS depth profiling was also applied to characterize the NPs diffusion and cycling effects in the memory elements. The structure of the organic film, the metal clusters layer, and the thin films morphology were studied by X-ray specular reflectivity (XSR), Grazing Incidence Small Angle Scattering (GISAXS), and Atomic Force Microscopic (AFM). For Al NPs, with Al layer nominal thickness 15 nm, average cluster-to-cluster distances of 80 nm, independent on the Al growth rate, were observed. The size and distance of Al clusters film is mainly determined by the morphology of the underlying organic layer. The relationship between the memory elements performances and the detailed morphological/structural properties of the active layer will be provided.

This paper will contain a short review of NAND and DRAM scaling limitations. It will examine the technical and economic capabilities that an emerging memory must achieve to displace mainstream memories. The major focus of the paper will be to development technical metrics that can be used to benchmark emerging memories. Multiple metrics will be developed across several technical categories including: scaling, energy density, number of particles, noise, etc. The relationships between the metrics will be examined. NAND will be used as a case study for these metrics. The metrics will be used to attempt to compare the major emerging memories including RRAM, CBRAM, STRAM, Ferroelectrics, phase change, etc. The paper will conclude with a prognosis on the suitability of the majors emerging memories for future mainstream applications.

Reliability issues appear even more predominant with the downsizing of critical dimensions of non-volatile memory (NVM) devices relying on charge storage. NVM integrating a “nanofloating” gate in the form of semiconducting nanocrystals is considered as an emerging solution which consists in embedding Si nanocrystals within SiO2 matrix: the Si nanodots are thus used as discrete traps for injected charges in replacement of the continuous polycrystalline Si floating gate. This charge trapping into individual dots limits the leakage current through defects created within the tunnel oxide beneath Si nanodots. However, despite a higher robustness against leakage, it is of primary importance apprehending the failure mechanisms of this discrete charge trap memories and uncovering the origin of nanoscale defects responsible for electrical degradation.
The aim of this study is to establish correlations between the stress-induced failure and the nanostructural defects at the origin of the local electrical breakdown. To reach this goal the experimental protocol (including accurate defect localization, FIB cutting and TEM observation) successfully developed on standard EEPROM memories was deployed on Si-nanodots capacitors. A peculiar attention was turned toward the removal of artifacts induced by ions and electrons used for FIB preparation and TEM observation. Besides, the protocol was carefully optimized for enabling TEM over the area potentially degraded during the electrical stress.
Encouraging results were obtained on two different sets of samples: either Si-nanodots memory cells or Si-dots grown on blanket substrate (Si-nanodots/oxide/Si substrate stack). On Si-nanodot memory cells, constant current stress was first applied to determine the breakdown voltage (VBD); the devices were then stressed under a constant voltage stress close to VBD. After an EMMI location of defects, thin lamellas were cut by FIB and observed by TEM. On the other hand, for Si-nanodots/oxide/Si substrate stack, localized breakdown was achieved by using a Conductive-AFM tip as already demonstrated on thin oxide layers: a bias voltage (+10 V) was applied to the substrate (grounded tip) to induce local electrical breakdown with a subsequent formation of hillocks observed by topographic AFM. Thanks to an accurate location of damaged area, an iterative method (progressive FIB thinning / TEM observation) was applied to uncover the origin of defects generated at nanoscale during the electrical stress.
The generation of nanostructural defects is shown to be linked to the nature of applied electrical stresses and compared to those evidenced in either thin oxide layers or EEPROM devices. Finally, this study brings to light the dielectric breakdown in silicon nanocrystal NVM and gives a better understanding of failure mechanisms.

The concept of complementing field effect transistors (FETs) with two-terminal hysteretic resistive switches has recently attracted a great interest in implementing and scaling novel nonvolatile resistive memories for ultrahigh density memory storage and logic applications. Notably, previous existing non-volatile resistive memories are all based on electrically switchable resistance change in various oxides and ionic conductors. These devices are electrically programmed and they are not suitable for direct interfacing with actuation/triggering other than electrical inputs. For applications such as human-computer interfacing, sensing/actuating in nanorobotics, and smart MEMS/NEMS, a direct interfacing of electronics with mechanical actions is required. Here we present the first piezoelectrically-modulated resistive switching device based on piezotronic ZnO nanowire (NW), through which the write/read access of the memory cell is programmed via electromechanical modulation. Adjusted by the strain-induced polarization charges created at the semiconductor/metal interface under externally applied deformation by the piezoelectric effect, the resistive switching characteristics of the cell can be modulated in a controlled manner, and the logic levels of the strain stored in the cell can be recorded and read out, which has the potential for integrating with NEMS technology to achieve micro/nano-systems capable for intelligent and self-sufficient multi-dimensional operations.

Resistive random access memory (RRAM) has been examined extensively as a promising candidate for next generation nonvolatile memory due to the scaling limitations facing Flash memory. Compared to conventional charge-trapping nonvolatile memory, RRAM device exhibits lower operation voltage and higher access speed; it also has advantages of low power consumption, superior data retention, high-density capacity and CMOS-compatibility.
In order to realize high density memory array, crosstalk between adjacent cells must be avoided. RRAM cell in one-transistor one-resistor (1T1R) configuration has been reported with planar transistor. However, the minimum cell size demonstrated for planar transistor structure is 6F2, where F stands for the minimum feature size. In 2010, RRAM cell integrated with three-dimensional (3D) vertical bipolar junction transistor (BJT) was demonstrated to have 4F2 footprint, although BJT has high leakage current and it may also increase process complexity if implemented along with CMOS logic circuit. A more direct method to achieve 4F2 cell size is to integrate RRAM cell with vertical nanopillar gate-all-around (GAA) transistor. Vertical nanopillar GAA transistor based on nanowire architecture has been demonstrated to be a viable candidate for 15nm and beyond technology nodes.
In this talk, we demonstrate the integration of vertical nanopillar GAA transistor with transition oxide based RRAM cell to achieve 4F2 footprint and systematically investigate 1T1R architecture in nanometer scale.

Organic resistive memory structures are generally formed by interposing thin layers of organic molecules between two electrodes. The cross-point (or crossed-bar) architecture permits the closest packing of bit-cells, with each occupying an area of 4F², where F is the minimum feature size (the line-width and spacing of the electrodes). A very wide range of organic materials that exhibit resistive switching has been reported. The film thicknesses are generally less than 1 mu;m and the phenomena are observed in different types of material (inorganic compounds, such as silicon dioxide and metal oxides, and organic compounds, such as polymers and charge-transfer complexes). Furthermore, the thin films have been formed using a variety of techniques (e.g. spin-coating, thermal evaporation). The only experimental parameter that is common to all the structures studied is the presence of metallic electrodes (e.g. Al) below and on top of the thin film.
Despite the impressive progress on developing the technology (e.g. 3-d structures), there is no agreement on how resistive thin film memories operate. Explanations generally fall into two distinct categories: (i) the injection and storage of charge in the thin film; and (ii) metallic filament formation. In previous work, we have reported on bistable switching phenomena in electroactive organic compounds based on ambipolar compounds, containing both electron and hole transporting groups [1,2]. Here, we review the published experimental data on organic resistive memories and report switching and negative differential resistance phenomena in a new ambipolar compound. Cross-sections of the devices have been imaged by electron microscopy both before and after applying a voltage. The micrographs indicate the growth of filaments, with diameters of 50 - 100 nm, on the metal cathode. We propose that the filaments are formed by the drift of aluminium ions from the anode that these are responsible for the observed switching and negative resistance phenomena in the memory devices.
References
1 C. Pearson, J. H. Ahn, M. F. Mabrook, D. A. Zeze, M. C. Petty, K. T. Kamtekar, C. Wang, M. R. Bryce, P. Dimitrakis, D. Tsoukalas, Appl. Phys. Lett., 2007, 91, 123506.
2 P. Dimitrakis, P. Normand, D. Tsoukalas, C. Pearson, J. H. Ahn, M. F. Mabrook, D. Zeze, M. C. Petty, K. T. Kamtekar, C. Wang, M. R. Bryce, M. Green, J. Appl. Phys., 2008, 104, 044510.

Self-assembled monolayers (SAMs) such as silanes, carboxylic acids (CAs) or phosphonic acids (PAs) provide a wide range of applications in the field of organic electronics and are well established as insulators in hybrid organic-inorganic dielectrics of low voltage organic thin film transistors (OTFTs) [1]. Organic thin film memory transistors (OTFMTs) with the possibility to operate as switch and non-volatile memory device at the same time bear another potential application. Integration of additional layers such as floating gates [2] or incorporation of nanoparticles acting as charge traps enable the control of hysteresis and consequently two different conducting states at a certain gate-source voltage (V_GS).
Our approach for the fabrication of OTFMTs without adding further layers for charge storage is the use of a functional hybrid dielectric of O₂-plasma fabricated AlO_x and a mixed SAM consisting of alkyl-PAs and C₆₀ functionalized PAs that are known to be excellent electron acceptors and thus acting as charge traps to enable the memory effect. The deposition of the redox active C₆₀-PAs is performed simultaneously with the insulating alkyl-PAs from mixed (SAM) solutions via self-assembly. Several ratios of C₆₀-PA to n-alkyl-PA were chosen for the preparation of mixed SAMs. The position of embedded C₆₀ moieties in the monolayer was investigated by means of X-ray reflectivity measurements (ID10, ESRF, Grenoble, France). In order to compare the charge retention and the memory ratio of OTFMTs depending on the distance of C₆₀ moieties to the organic semiconductor in the stack, various chain lengths of insulating n-alkyl-PAs were chosen. In particular embedding of C₆₀-PAs between long chained n-alkyl-PAs has shown to be a successful way to ensure an increased isolation of the C₆₀ moieties by the longer alkyl-PAs and to decrease charge leakage. These devices exhibited improved retention times to OTFMTs with non-isolated C₆₀ moieties.
For further investigation of the leakage behavior α,α'-dialkyl-oligothiophene semiconductor materials with different side chain lengths were used to modify the distance to C₆₀ functional groups of the hybrid dielectric.
XRR provided information about the molecular arrangement [3] and thereby led to an adaptation of device structure and improvement of device performance.
The results of this novel approach for OTFMTs with C₆₀ charge storage units were significantly encouraged by X-ray reflectivity experiments and molecular dynamics simulations.
References
[1] a) Halik, M., Klauk, H. et al. (2004), Nature 431(7011): 963.
b) Klauk, H., Zschieschang, U. et al. (2007), Nature 445(7129): 745.
c) DiBenedetto, S. A., Facchetti, A. et al. (2009), Advanced Materials 21(14-15): 1407.
[2] Sekitani,T., Yokota, T., Zschieschang, U., Klauk, H. et al. (2009), Science 326 (5959), 1516
[3] Amin, A., Khassanov, A., Halik, M. et al. (2012) JACS 134 (40), 16548

Due to the presence of two stable polarization states, ferroelectric polymers are attractive for use in non-volatile random-access memories. These polarization states can be easily switched by the application of an electric field. Among ferroelectric polymer materials, poly(vinylidene fluoride) (PVDF) and its copolymers with trifluoroethylene (TrFE) are particularly attractive for nonvolatile memory applications due to their large polarization and excellent switching characteristics. Recently, we reported the use of nano-imprint lithography (NIL) to fabricate high-density arrays of ferroelectric polymer cells [1]. NIL is a hot-melt embossing process where the mold is placed in contact with a spin-coated film of P(VDF-TrFE). In this former study, the orientation of the chain axis (or c-axis) was aligned parallel to the substrate, easing the switching of the polarization and decreasing the coercive field by a factor of up to ten.
In this communication, we report on the development and use of piezoresponse force microscopy (PFM) to study the ferroelectric properties of imprinted P(VDF-TrFE) arrays. PFM and other spectroscopic techniques are used to investigate the effect of imprinting processing conditions, and of the size of the cavities of the mold, on the crystal orientation and the ferroelectric properties of the resulting nanostructures. We show that the decrease of the coercive field only occurs when the polymer is crystallized in conditions of spatial confinement. In addition, we study the thermal stability of imprinted samples by PFM, up on heating initially poled samples, and compare this with the thermal stability of the bulk ferroelectric P(VDF-TrFE) copolymer as probed by differential scanning calorimetry. Down to 200x200 nm² imprinting sizes, the thermal stability is found to be identical to the one of the bulk polymer.
[1] Z. Hu, M.Tian, B. Nysten and A. M. Jonas, Nature Materials. 2009; 8:62-67.

Organic Thin Film Transistor-based memories have been fabricated on highly flexible plastic substrates by using a very simple approach.
The device structure consists in an aluminum gate electrode on which an ultrathin oxide layer, nominal thickness of 5 nm, is grown by means of UV-Ozone treatment. At the top of this structure, a second ultrathin insulating layer (thickness of 25 nm), made out of Parylene C, is deposited from vapor phase, and on top of it, metal source and drain electrodes have been patterned by means of photolithography or by inkjet printing. In all cases, TIPS-penatcene was employed as organic semiconductor. Thanks to the high capacitance coupling induced by the ultrathin double-layer insulating film, such devices can be operated at ultralow voltages, as low as 1V, showing mobility up to 0.1 cm2/Vs, Ion/Ioff up to 10^5 and remarkably low leakage currents (100 pA), with a typical breakdown field higher that 5MV/cm.
Interestingly, thanks to the particular double-layer structure employed as the gate dielectric, it is possible to operate these devices also as non-volatile memory elements. It was found that by applying a pulsed gate voltage, possibly slightly higher than the nominal breakdown voltage, it is possible to induce a pronounced threshold voltage shift in the transistor behavior. Such a shift seems to be related to the trapping of charges coming from the active channel within the gate dielectric. It is noteworthy that the presence of a double layer structure strongly increases the retention time of the trapped charges, allowing these devices to be employed for practical applications.
In particular, it was found that applying a gate voltage pulse of -20V for 10 ms usually gives rise to a threshold voltage shift higher than 1.5V in the same verse of the applied field. In other words, the device is strongly driven to its off state. We have observed a remarkably high Ion/Ioff ratio, usually in the range of 10^4/10^5, measured at -1V, and retention times higher that 10^5 s are typically obtained. The device can be easily reset to its previous state by applying a slightly positive gate voltage pulse (+5V for 10ms).
A study of the influence of the polarization parameters, such as applied gate field, pulse duration, and number of applied pulses, on the main parameters of the fabricated memory elements (i.e. Ion/Ioff and retention time) will be discussed as well as the physical principle behind the observed behavior.
The flexibility of the proposed structure and the simplicity of the employed fabrication procedure make this approach very interesting for practical applications.

Resistive Random Access Memory (RRAM) devices are currently being extensively investigated by many research groups. Organic RRAMs, in particular polymer-based systems, are attractive as they lend themselves easily to printed electronics circuit fabrication with comparable performance to conventional oxide/metal devices.
We have fabricated non-volatile, bistable, resistive memory devices on flexible substrates using a single polymer. The device stack consists of solvent-doped, spun-cast, highly conducting polymer thin films as the bottom electrode, a semiconducting layer of the undoped polymer and an inkjet-printed highly conducting polymer as the top electrode. These devices reproducibly exhibit a Write-Once Read -Many times (WORM) memory behavior, useful for reliably and permanently storing archival standards, digital video images and non-editable databases with massive amount of information over a long period of time. The fresh devices with polymer bottom electrodes show an irreversible ON (low resistance) to OFF state (high resistance) transition. For comparison, fresh devices with metal bottom electrodes exhibit an OFF to ON transition, indicating a bottom-electrode dependent switching behavior in these devices. We believe this can be attributed to the difference in morphology of polymer growth on different substrates. The electrical characterization of all-polymer devices shows an on/off ratio >1000, low write/read voltages and excellent retention capabilities maintained over 10000 sec.
We believe that our simple and unique device structure, comparable performance and improved retention characteristics over metal electrodes is ideal for large-area flexible organic electronics.
*Author to whom correspondence should be addressed.
Email address: [email protected]

A range of metal oxide systems exist in which ionic transport and redox reactions on the nanoscale provide the essential mechanisms for resistive switching, which may lead to non-volatile resistive memories (ReRAM) and neuromorphic logic devices. An important class (the valence change memory, VCM) operates through the migration of anions, typically oxygen ions, towards the anode, and the reduction of the cation sublattice in the layer locally providing metallically or semiconducting phases. The electrochemical nature of these so-called memristive effects triggers a bipolar memory operation. In another class, the thermochemical effects dominate over the electrochemical effects in transition metal oxides which leads to a unipolar switching as known from the phase-change memory. In all systems, the defect structure turns out to be crucial for the switching process. Neuronal networks offer a large variety of applications, but implementation in CMOS-only circuits is very complex. Therefore, hybrid CMOS/nanocrossbar arrays are an interesting option to achieve high density circuits, and to allow for large synaptic connectivity. In crossbar arrays, synapses are represented by resistive switches, i. e. ReRAM cells, which are located at each cross-point. The synaptic weight, i.e. the resistance, can be adapted during a learning process; to predict proper synaptic behavior practical models are required.

Resistive random access memory (RRAM) has attracted significant attention as a candidate for next generation non-volatile memory due to its low energy consumption, high switching speed, excellent scalability and low operation voltage. Here we discuss noise analysis on metal-oxide based RRAM devices using Pd/TaOx/Ta2O5/Pd structure where the TaOx/Ta2O5 bilayer oxide serves as the functional layer. Reliable bipolar switching with write voltage of -0.7V and erase voltage of 1.2V was obtained from the devices after forming. Significantly, the filament conduction can be affected by electron trapping and detrapping near the filament and can exhibit pronounced random telegraph noise (RTN) in both the high-resistance (HRS) and the low-resistance state (LRS). Noise can cause errors during array operation, particularly for devices in HRS. However, analysis of the RTN and the associated low frequency noise (LFN) also helps us understand the switching mechanism and provide insight into methods to mitigate effects of the noise. Specifically, we found that both the amplitude and the time constants of the RTN can change after every write/erase process even under identical programming conditions, suggesting different defects are involved and new conduction paths are created during each write/erase process. LFN analysis also showed that the noise significantly deviates from conventional 1/f noise. Additionally, we found that the noise time constants are affected by the electric field polarity. Under negative voltage, the current fluctuations are caused by both electron trapping/detrapping events as well as read disturb. Under positive voltage, the current fluctuations are caused mainly by electron trapping/detrapping near the filaments. Differences between these two mechanisms were systematically studied by analyzing the RTN time constants at different bias conditions. The resistive switching mechanism was further studied by analyzing noise with partially programmed filaments using lower current compliance. Finally, correlation of results obtained from the LFN noise analysis with the RTN analysis will be discussed for both the LRS and the HRS state.

Resistive switching memory (RRAM) based on metal oxides is attracting a growing interest as low-power, scalable technology in the post-Flash scenario [1]. The RRAM resistance states are controlled by a conductive filament (CF) in both unipolar [2] and bipolar switching devices [3]. Since reliability and scaling are dictated by the stability of the CF, a physics-based understanding of the filament nature and morphology is needed. Also, new approaches to multilevel storage must be demonstrated to allow 2- and 3-bit per cell operation [4,5].
This work discusses a multilevel concept through the control of size and direction of the CF in RRAM. As in previous approaches, the CF size is controlled by the current compliance Ic during the set transition [3-5]: as Ic is increased, the CF size increases thus controlling the device resistance according to RIc = Vc = 0.4 V [3]. For any CF size, two states are achieved by opposite orientations of the CF, obtained by opposite voltage polarity during set transition. For instance, a ‘positive CF&’, obtained by a positive voltage at the top electrode during the set transition, has a conical shape with the tip directed toward the bottom electrode, coherent with the ion-migration flow. On the other hand, a ‘negative CF&’, obtained by a negative voltage at the bottom electrode during set transition, has the tip directed to the top electrode. This approach allows encoding two logic states per each R value, e.g. enabling 3 bit-cell operation with only 4 resistance levels. This is a key advantage in view of the limited resistance window (reset/set ratio = 10) of bipolar RRAM [6].
To determine the CF direction, the complementary switching (CS) effect is exploited [7]. For a negative CF, application of a positive read voltage simply results in the CF-tip retraction to the bottom electrode and a consequent R increase. For a positive CF, instead, positive read voltage induces CS, where the CF size further increases leading to a R decrease. Based on the different responses to the applied positive voltage, the direction of the CF can be determined, thus enabling multilevel read. Simulations of ion migration by a numerical model [8] allows to visualize the nanoscale defect distribution in CF with different shapes and directions. The combined experimental/numerical approach enables RRAM design with controllable multilevel read/write and accurate reliability prediction.
[1] H.-S. P. Wong, et al., Proc. IEEE 100, 1951 (2012).
[2] U. Russo, et al., IEEE Trans. Electron Devices 56, 186 (2009).
[3] F. Nardi, et al., IEEE Trans. Electron Devices 59, 2461 (2012).
[4] H. Y. Lee, et al., IEDM Tech. Dig. 297 (2008).
[5] U. Russo, et al., IEEE Trans. Electron Devices 56,1040 (2009).
[6] M.-J. Lee, et al., Nat. Mater. 10, 625, (2011).
[7] F. Nardi, et al., IEDM Tech. Dig. 709 (2011).
[8] S. Larentis, et al., IEEE Trans. Electron Devices 59, 2468 (2012).

Conductive Bridge Random Access Memory (CBRAM) is one of the emerging technologies for sub-20 nm nonvolatile memory devices. This device consists of an active metal electrode, an insulating solid electrolyte, and an inert metal electrode. When a positive voltage is applied to the active electrode, the metal ions dissolve and migrate in the solid electrolyte. The metal ions are reduced on the inert electrode, nucleate and form a nanobridge. When the nanobridge is long enough to connect both electrodes, the device transitions, in so-called SET operation, from the high resistance state (HRS) to the low resistance state (LRS). A high current flowing through the nanobridge generates substantial local Joule heating. The heat can rupture the nanobridge leading to the transition from LRS to HRS. This operation is called RESET. The SET-RESET cycle is named resistive switching. During the SET operation, the compliance current (Icc) is applied to the device by the external circuit to limit the power consumption. One observes that the nanobridge resistance is inversely proportional to the compliance current. This relation enables the multi-level cell capability. The geometrical shape of nanobridge has been assumed to be a truncated conical shape filament. The radial growth of nanobridge determines the memory resistance level. The larger nanobridge radii result in the lower device resistance. In this work we propose a model for the radial growth of the nanobridge. The model is based on the ion hopping flux from the active electrode to the surface of nanobridge. In the electric field, the metal ions hop towards the nanobridge and accumulate to increase the local radius. The conical shape nanobridge has a small top on the active electrode and broad base on the inert electrode. Due to the geometrical effect, the radial growth rates at the cone top and bottom are different. Since the positive voltage is applied to the active electrode, the top of nanobridge is exposed to higher electric field than the bottom. This electric field distribution leads to higher radial growth rate at the tip top than at the bottom of nanobridge. Because of the fast growth of the small tip, the final geometry of nanobridge is more or less a cylinder. Due to the hopping mechanism, the growth rate follows exponential law with the applied voltage in the empirical models. The growth happens in very short time duration after the SET voltage has been reached, usually on a time scale smaller than the voltage ramp. The resistance of nanobridge keeps decreasing until the current reaches the compliance. After that the geometry of the nanobridge is more or less fixed and the resistance does not change appreciably under the electrical stress because the voltage drop on the nanobridge is relatively small. With this model, we can match Ron-Icc experimental results, if one excludes data of Ron>50 kOhm, with a reasonable time scale for lateral growth and reasonable nanobridge geometry.

Conductive Bridge Random Access Memory (CBRAM) is an emerging technology for nonvolatile memory cells. A conventional resistive switch, such as Pt/TaOx/Cu, consists of an active metal bulk electrode (Cu), a dielectric (TaOx), and an inert metal electrode (Pt). In order to shed light on the mechanisms of creation and rupture of conductive nanofilaments (CF), a Pt/TaOx/δ-Cu/Pt device with limited supply of active electrode metal (δ-Cu layer) has been manufactured and characterized. The thicknesses of the layers of the switch are respectively: bottom Pt 80nm, TaOx 32nm, δ-Cu 6nm and 12nm, and top Pt 80nm. Key observations of the characteristics of the limited source devices are:
1) initially for several switching cycles the limited source device behaves like a conventional Pt/TaOx/Cu switch [1]. For a device with Tδ-Cu=12nm, we find Vform=3.5V-4.0V, Vset=2.5V-3.0V and Vreset=(-0.9)- (-1.5V). 2) After several switching cycles (15-20 for Tδ-Cu=12nm and 5-8 for Tδ-Cu=6nm) a pulsating behavior sets in: the device turns on and off repeatedly with increasing voltage. Formation of a 1st Cu-CF, its subsequent rupture, and subsequent setting of a new Cu-CF explain this behavior. The CF has high resistance because of a limited supply of Cu ions; hence a suppressed lateral growth [2] of the CF. 3) A formation and rupture of multiple CFs is observed: formation and rupture of several CFs is observed and Ron value of the individual CF is extracted from I-V characteristics. The limited source switch is conducive to multiple CF formation than a conventional device [3]. 4) After many switching cycles the switch begins to display similar (i.e. symmetric) switching characteristics on the positive and negative voltage bias; Cu-CF bridges can be formed under both polarities. The reason for this is that the device after several switching cycles becomes physically symmetrical; the original δ-Cu layer is redistributed into rough δ1-Cu and δ2-Cu layers on both sides of the dielectric resulting in Pt/δ1-Cu/TaOx/δ2-Cu/Pt structure. Cu-CFs are now being formed from both sides under the respective bias leveraging the fact that both electrodes have similar stopping power. In some cases, volatile switching behavior [4] is observed. 5) For devices with different Cu supplies, it is found that Tδ-Cu=6nm devices higher average Ron=460Omega; than Tδ-Cu=12nm devices (Ron=230Omega;) under Icc=100mu;A. The latter observation is explained by the more limited supply of Cu atoms for Tδ-Cu=6nm than for Tδ-Cu=12nm. During its switching history a CBRAM device even with a bulk electrode undergoes irreversible structural change.
[1] T. Liu, M. Verma, Y. Kang, and M. Orlowski, ECS Solid State Letters, 1 (2012) Q11-Q13
[2] T. Liu, Y. Kang, S. El-Helw, T. Potnis, M. Orlowski, submitted to this conference
[3] Y. Kang, M. Verma, T. Liu, and M. Orlowski, ECS Solid State Letters, 1 (5) Q48-Q50 (2012) [4] T. Liu, M. Verma, Y. Kang, and M. Orlowski: Appl. Phys. Lett. 101, 073510 (2012)

Although the flash memory device has scaled to 20 nm for high-density sub-Tb array, the degraded retention and endurance are the fundamental challenges to further scale down into deep 1X generation, according to International Technology Roadmap for Semiconductors. The degraded memory device performance is due to the smaller number of electrons stored in the 0.5X smaller cell size for every technology generation. To address these challenges, resistive RAM (RRAM) has been proposed for non-volatile memory (NVM) application, which does not require charge storage in continuously scaled cell size. By applying thermal energy to form the different resistance state between crystalline and amorphous phases, the phase-change RAM (PRAM) has demonstrated a large 8 Gb array with fast bandwidth. Nevertheless, the relatively high switching power and thermal cross-talk are the concerns for this technology. Alternative RRAM using metal-oxide and conductive filament mechanism were also proposed. However, the high switching current is the bottleneck for large density array; the large resistance variation and required forming process are other challenges for this type RRAM. In this talk, we report an novel oxide-based RRAM, where low set/reset current of ~mu;A, fast switching speed of 20~100 ns, low switching power of mu;W to sub-mu;W, good retention at 85~125C, and excellent endurance of 1 million to 10 G cycles were achieved simultaneously. These excellent performances are possible by using a stacked semiconductor-oxide/metal-oxide with different work-function top and bottom electrodes. The low switching energy of pJ to fJ is among the lowest reported data of RRAM and close to the existing flash memory. Besides, significantly better resistance distribution is obtained and attributed to the bulk-conductive property that was verified by both experiment and theoretical simulation.

In this study the doping of resistive switching oxides has been investigated. Three resistive switching oxides: titanium dioxide, hafnium dioxide and tantalum oxide were investigated with regard to the effect on their conductivity due to Al, Ta, Ti doping. Films of TiO2 and HfO2 were deposited with 100nm thickness using oxygen plasma Atomic Layer Deposition (ALD). The tantalum oxide was deposited using RF sputtering from an oxide target in an Ar ambient (no oxygen added to the sputtering gas). The doping was achieved by depositing films of Ta, Ti and Al of various thicknesses on top of the oxide films and then annealing it at ~ 1000 K for times between 10 and 40 min at 8x10-8 torr. During this anneal process, the metal layers act as limited diffusion sources. Thus, for each resistive switching oxide (TiO2, HfO2, TaOx), three metals (Ta, Ti, Al) were investigated as being dopants to alter the resistivity of the films. Different dosages of these metal diffusion sources was achieved by varying the thickness of the Ta, Ti and Al metal layers. After annealing, the top surface of the composite stack was milled through, exposing the doped oxide beneath. This milling was designed to remove residual metal on the oxide surface. Following the surface treatment, inter-digitated electrodes were deposited on the oxide films to allow the measurement of film conductivity. The electrodes were sized to provide measurement capabilities down to 10-8 S/m. The as-deposited films were found to have conductivities of ~ 3x10-7 S/m for TiO2 and HfO2 and ~ 4x10-6 S/m for TaOx. The doping treatment raised the conductivity of all three films by 7-8 orders of magnitude when taken to completion. More specifically, it was found that conductivity increase caused by Al doping required the smallest annealing times, with the effect reaching completion within 20 min, while the Ta doping required the greatest amount of annealing, requiring 40 min to reach completion. Additionally, Al produced the largest increase in conductivity for a given metal film thickness, followed by Ti and then Ta. This was followed by a study of switching behavior of these films for all the diffusion process conditions. The resistive switching devices were fabricated using the same process except Pt top and bottom electrodes were deposited to provide contacts. The switching ability of the devices was studied for each doping combination and the doping level that allows switchable devices was demarcated in each type of oxide. It was found that the highly doped HfO2 and TaOx films doped to conductivity levels above 5x10-2 S/m and 0.5 S/m, respectively, did not show resistive switching. However, the TiO2 films retained switching behavior for all doping conditions examined, up to maximum conductivities observed of 12 S/m.

Resistive switching memory (RRAM) has wildly considered as one of the most promising candidates for next generation nonvolatile memories (NVM). The CMOS compatibility is one of the crucial properties for RRAM to be applied to mass production. WOx-based resistive switching cells have good CMOS compatible fabrication process. However large forming voltage and high reset current become obstacles for WOx based RRAM to have wide applications.
In this study, AlOx/WOx bilayer based RRAM cells are fabricated in a standard 0.18mu;m CMOS process with only one extra mask and three additional fabrication steps: 1). Rapid thermal oxidation (RTO) to produce WOx layer after chemical mechanical polishing (CMP) of W-plug; 2). Dry etch to clean the oxidized W-plug in via area where metal connection is needed; 3). Rapid thermal annealing (RTA) process after the deposition of Al top metal (TE) to form a thin uniform AlOx layer. Those RRAM cells are in cross-bar pattern. All process steps are finished in a commercial CMOS foundry. The AlOx/WOx bilayer RRAM cell shows excellent electrical performance with very low power consumption. Low operation voltages (Forming voltage <1.5V, SET voltage < 1.5V, RESET voltage < 1.3V) are achieved; also RESET current is lower than 1mu;A. Considering this RRAM cell has the 0.3mu;m×0.3mu;m area, the current density is below 1.1×10³A/cm² which is much lower than that reported in previous literatures.
Our study showed the appropriate selected RTO and RTA conditions and precise controlled thickness of each layer are very important to the performance of RRAM cells, such as switching uniformity, operation current, endurance and retention properties. The microstructure and thickness were examined by filed-emission transmission electron microscopy (TEM). The X-ray photoelectron spectroscopy (XPS) depth profile technique was applied to confirm the compositions and chemical state of each layer and, more importantly, the interface region. Additionally, current-voltage (I-V) and capacitance-voltage (C-V) tests were also carried out to investigate the switching behaviors. By summarizing the physical and electrical characteristics, a metallic filament formation and rupture in AlOx layer is proposed to explain the switching behavior of the AlOx/WOx bilayer RRAM.

Redox based resistively switching memory cells (ReRAM) are one of the most promising alternatives to state-of-the-art DRAM and FLASH memories offering new options in terms of scalability, operation speed and power efficiency [1]. Electrochemical metallization memory cells based on GeS_x are a class of ReRAMs using cation-conducting solids as electrolyte and appear to be the most promising material in the field of ECM memory cell application [2-4].
In this contribution we report on electrical measurements of GeS_x-based micro-crossbar memory cells. The Ag/GeS_x/Pt cell stack was fabricated by RF sputtering and integrated into micro-crossbar structures with a cross-section of 2 µm x 2 µm. The micro-crossbar cells exhibit excellent quasi-static I-V characteristics and fast switching times in the 100 ns regime. We investigated the switching kinetics in the SET as well as in the RESET operation and confirmed the existence of quantized conduction levels in GeS_x-based ECM memory cells.
Potential future applications of resistively switching memory cells are passive crossbar arrays. The CRS concept with an anti-serial connection of two bipolar resistive switches offers an option to overcome array size limitations due to sneak path problems [5]. The CRS cells used in this work consist of two Ag/GeS_x/Pt planar micro-crossbars with a common Ag electrode. We present the electrical behaviour of this ECM-type CRS memory cells in quasi-static I-V measurements and pulsed measurements. We are able to prove the proper bipolar operation of each element and thus, full functionality of ECM-based CRS cells by observing the voltage at the accessible Ag middle electrode. Moreover, we demonstrate switch-over times in the 20 ns regime and therefore confirm the practicability of a spike read scheme [6] in CRS memory cells.
[1] R. Waser and M. Aono, Nanoionics-based resistive switching memories, Nat. Mater. 6, 833-840 (2007)
[2] M.N. Kozicki, M. Balakrishnan, C. Gopalan, C. Ratnakumar, and M. Mitkova, Programmable metallization cell memory based on Ag-Ge-S and Cu-Ge-S solid electrolytes, Proceedings of NVMTS, 83-89 (2005)
[3] M. Kund, G. Beitel, C. U. Pinnow, T. Roehr, J. Schumann, R. Symanczyk, K. D. Ufert, and G. Mueller, Conductive bridging RAM (CBRAM): an emerging non-volatile memory technology scalable to sub 20nm, IEDM Tech. Dig., 754 - 757 (2005)
[4] I. Valov, R. Waser, J. R. Jameson, and M. N. Kozicki, Electrochemical metallization memories-fundamentals, applications, prospects, Nanotechnology 22, 254003/1-22 (2011)
[5] E. Linn, R. Rosezin, C. Kügeler, and R. Waser, Complementary Resistive Switches for Passive Nanocrossbar Memories, Nat. Mater. 9, 403-406 (2010)
[6] E. Linn, R. Rosezin, S. Tappertzhofen, U. Böttger, and R. Waser, Beyond von Neumann—logic operations in passive crossbar arrays alongside memory operations, Nanotechnology 23, 305205/1-6 (2012)

The scaling limitations of memories relying on electronic charge storage have led to the emergence of new memory concepts of which, in particular, information storage via two different resistive states, is a very promising approach. Consequently, resistive memories have been considered for next generation non-volatile memories. Among them, Conductive Bridge Random Access Memories (CBRAMs), relying on a bipolar electrochemical mechanism (ECM), attract great interest from both an academic and an industrial point of view.
The basic structure of a CBRAM consists of a solid electrolyte of high ionic conductivity embedded between two electrodes: an active anode, acting as a cation supplier, and a passive cathode. The ECM relies on the migration of the metallic cations through the solid electrolyte under an electrical field and their subsequent reaction at the inert counter-electrode leading to the growth of highly conductive filaments within the solid electrolyte. These filaments set the memory element into a low resistance state. By reversing the polarity, electrochemical dissolution of these filaments takes place, resetting the system into the high resistance state.
Although successful integration of CBRAMs with standard BEOL logic processes has been demonstrated, this technology still suffers from relatively poor cycling endurance and data retention.
In order to overcome these issues, current research focuses on material optimization and the successful development of this new technology depends essentially on the progress in the understanding of the switching mechanism. In this framework, we studied a doped GeS2 solid electrolyte with an Ag active electrode. This work is focused on the electrolyte properties and Ag migration depending on its composition and doping (Sb). In particular, we used synchrotron radiation facilities with Hard X-ray PhotoElectron Spectroscopy (HAXPES) and Grazing-Incidence Small-Angle X-Ray Scattering (GISAXS) in order to investigate, in the bulk, the electrolyte w/wo additional doping elements (Sb). These techniques allow obtaining respectively, the chemical bonding states of Ge, S and Ag with enhanced depth sensitivity and high energy resolution, and structural information on the possible presence of nanophases. We show that the presence of Sb has a strong impact on the chemical bonding in the chalcogenide thin films. All the results are discussed in the frame of the commonly accepted picture involving the formation of Ag2S clusters in a GeS2-based matrix. Finally, the results of the material and electrical characterizations are combined and correlated to evidence the details of the switching mechanism. It is shown that the use of Sb doping allows improving significantly the CBRAM electrical performances (30 ns program at 2.2V, 10 years retention at 125°C and > 10e5 cycling).
Acknowledgement: the authors would like to thank F. Dahmani from Altis Semiconductor for the fruitful discussions.

Recently, electroresistance (ER) effect of ferroelectric tunnel junctions (FTJs) has been predicted theoretically and FTJs have been realized experimentally using perovskite ferroelectrics. On the other hand, Mn-based hexagonal ferroelectric materials, such as YMnO₃, have attracted much attention as single-phase multiferroic materials, where electron and spin transport can be controlled by magnetic or electric fields. Given that YMnO₃ is thought to have semiconducting ER effect, this material can expand the functionality of conventional tunnel junctions. In this presentation, we show ER effect and conductance control by domain engineering in hexagonal ferroelectric thin films with piezoresponse force microscopy and conductive atomic force microscopy. We observed conductivity of the 180° domain walls separating anti-parallel polarizations, while it is reported that only domain walls of the head-to-head or tail-to-tail configurations are conductive. We discuss physics of conductance change in hexagonal ferroelectric thin films and feasibility of multifunctional ferroelectric tunnel junctions with a hexagonal ferroelectric barrier.

Although the technological impact of spintronics, and DMS (dilute magnetic semiconductors) is beyond question, the origin of RTFM (room temperature ferromagnetism) in DMS is still under debate due to the discrepancy in the reported results.1,2 Observations of RTFM even in intrinsic oxide compounds at reduced scale raise the fundamental question on the origin of RTFM in this class of materials.3 In the case of intrinsic oxide compounds, independent theoretical studies on the wurtzite structured ZnO, and rock-salt structured CaO and MgO suggest on cation vacancy induced magnetism, wherein a magnetic moment is believed to occur due to the coupling between 2p states of the oxygen atoms surrounding a cation vacancy site.4 Whereas e.g. the Zener, mean field Zener, and bound magnetic polaron models have been applied to explain the same in the doped oxide compounds.5
We present here a comprehensive study on the electronic and magnetic properties of intrinsic and Fe doped MgO thin films by means of synchrotron based soft x-ray technique. A distinct shoulder feature on the O K absorption edge reflecting the unoccupied oxygen 2p states is evident in the intrinsic thin films. And this feature diminishes upon Fe doping, while a pre-edge absorption feature (reflecting the O 2p-Fe 3d acceptor state) evolves with the same. Our experimental findings demonstrate the reduction in the intrinsic holes as a result of charge-transfer hole doping, and correlate well to the variation in the magnetic properties with the same (acquired using a SQUID magnetometer).
Reference
1. Z. Zhang et al., J. Appl. Phys. 100 043909 (2006)
2. S. Ghoshal and P. S. A. Kumar, J. Phys.: Condens Matter 20 192201(2008)
3.M. Kapilashrami et al., Appl. Phys. Lett. 95 033104 (2009)
4. I. S. Elfimov et al.,Phys. Rev. Lett. 89 21(2002)
5. A. J. Behan et al., Phys. Rev. Lett. 100 047206 (2008)

Ferromagnetic nanorings have attracted extensive research interest both in fundamental studies of magnetism and for their potential application in data storage. Due to the ring geometry, the magnetization displays vortex and onion states in the M-H loop. Previous research has focused on nanoring fabrication by planar patterning processes such as optical lithography, electron beam lithography, nanosphere lithography etc. These techniques either impose limitations on the nanoring dimension, cost effectiveness or long-range order. Here we present a low-cost versatile method for fabrication of large-scale highly ordered Ni₈₀Fe₂₀ nanoring arrays patterned using interference lithography.
Interference lithography is used to pattern a diperiodic array of holes in a negative photoresist and anti-reflective coating stack spin-coated on a silicon wafer. The pattern is then transferred to the silicon substrate using reactive ion etching. Subsequently, Ni₈₀Fe₂₀ is deposited on the sidewall of the holes with the substrate tilted at angle with respect to the flux during evaporation. A final lift-off process leads to arrays of Ni₈₀Fe₂₀ nanostructures. This method is highly versatile in the dimension, geometry of the nanostructures and the periods achievable. The width of nanorings ranges from 25nm down to 10nm, and height varies from 50nm to 30nm, which is difficult to achieve by conventional methods. Depending on the geometry of the template and tilt angle, the final nanostructure can be nanoring, 3D nanoring or nanocup. The effect of dimension and geometry of these nanostructures on their magnetization reversal processes will be discussed and correlated with micromagnetic simulations using the Object Oriented MicroMagnetic Framework (OOMMF) software package.

Close-packed GMR arrays have recently drawn great attention because of their potential use in applications like magnetic and spin torque random access memories (MRAM and ST-RAM). Here, Co(10nm)/Cu(tCu) multilayered nanowires with 100nm diameters were electrodeposited into anodic aluminum oxide templates. Spin transfer torque (STT) switching of these multilayered nanowires was observed under zero external fields with switching current densities less than 107 A/cm2 and MR ratios as high as 30%. It was seen for small Cu spacer thicknesses that both switching currents (antiparallel to parallel AP-P and parallel to antiparallel P-AP) were negative, which is completely unwanted if these structures are to be used as storage elements. This is because the high or low resistance state (1 or 0) will not be stable at zero current. Traditionally, this can be solved by applying an external magnetic field where the switching loop can shift left or right depending on the direction of the applied field. In our work, shifting of the loop was successfully achieved by varying the nonmagnetic layer thickness (tCu). It was found that increasing the Cu thickness from 3nm to 20nm changed the critical JcP-AP switching current density from being negative to positive. In the latter structure, at zero current the desired state (1 or 0) will be stable, all without the need for external fields. Although increasing the Cu thickness resulted in ideal switching curves, the critical current density for the antiparallel-parallel switch (JcAP-P) increased slightly. To gain control on the switching behavior of these structures, the switching current densities (JcAP-P and JcP-AP) as functions of tCu were explained by exploring both the spin relaxation effect and the effective demagnetizing field effect. Based on these phenomena, one can pre-design the structure to achieve not only ideal switching curves (bipolar switching currents), but also the smallest possible switching current densities (as low as 106 A/cm2).

Currently, flash memory is the most prosperous technology for non-volatile random access memory even though it possesses significant scaling challenges. Among the new generation of non volatile memories that overcomes the scaling issue Contact Bridge Redox Memory (CBRM) has emerged as a promising candidate for future high density, high performance memory and logic applications. In CBRM resistance change occurs in response to a voltage flux across it by building up or dissolving a conductive molecular bridge between two electrodes. An array of these devices can be formed by making a nano-wire over the inert electrode with chalcogenide (ChG) film as a dielectric medium between the two electrodes. This structure offers high device density with simplest of configuration and allows access to each nano CBRM devices.
In this work a high density contact bridge redox memristor array is demonstrated on thin films metal/insulator/metal (MIM) stack which results in high yield with good reproducibility. The memristor array was formed by sputtering Tungsten (W), thermally evaporating the ChG film and confining the devices by bombardment of Argon (Ar⁺⁸) ions using a shadow mask with no lithographic step. To analyze the influence of the ion bombardment on chemical structure, surface topography and composition of the materials in the device active area; Raman Spectroscopy, Atomic Force Microscopy (AFM) and Energy Dispersive X-Ray Spectroscopy (EDS) studies were performed. Specific attention was paid to the surface roughness in these areas as it plays an important role in the growth of conductive molecular bridge. Calculations were carried out for evaluation of the nucleation and growth of the conductive bridge. The devices were electrically tested to show the usability of the process for fabrication of CBRM array. It was found that variations in ion accelerating voltage resulted in different surface conditions which played an important role in device switching performance. The array structure offers excellent yield, stable ON/OFF ratio and uniformity. This demonstration, along with success already achieved at the single cell level suggests that CBRM memristor is well placed for ultra high performance memory and logic applications.

Recently, a current-driven manipulation of domain wall (DW) in magnetic nanostripe is one of the most prominent candidates for future high-performance, solid-state storage and operation technologies [1]. However, one of the biggest difficulties to realize a practical domain-wall-based device is their speed limit known as Walker&’s breakdown; the wall velocity initially increases with current, but above a certain criterion it suddenly decreases due to periodic change of the domain wall structure.[2] To overcome this hurdle, various methods including applying transverse fields [3] or using edge roughness[4], comb structures [5], a perpendicularly magnetized underlayer [6] have been proposed. However, these approaches are not easy to adopt in practical devices.
In this presentation, we report on the results of a micromagnetic simulation study on transverse wall-type DW motions driven by currents. As a model system, we chose a Permalloy (Py) nanostripe of 18 um length, 84 nm width, and various thickness ranging from 2 to 20 nm, where a head-to-head TW-type DW was placed at the center position. From previous studies, it is known that the Walker breakdown of Py nanostripe occurs about 500 m/s and thus the speed limit of DW motion is about 500 m/s. Surprisingly, we have found that, by just decreasing the thickness of nanostripe without any additional external fields or modification of shapes, the speed limit increases up to 1 km/s. This can be understood from the origin of the Walker breakdown, the gyrotropic field and their thickness dependence [7]. Details on this physical understanding will be given in this presentation. The results provide a simple and efficient means for an information transfer through a current-driven DW motion as fast as 1 km/s.
This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2012R1A1A1041922)
References
* corresponding author, [email protected]
[1] S.S.P. Parkin et al., Science 320, 190 (2008).
[2] J.-Y. Lee et al., Phys. Rev. B 76, 184408 (2007).
[3] M. T. Bryan et al. J. Appl. Phys. 103, 073906 (2008).
[4] Nakatani et al., Nature Mater. 2, 521 (2003).
[5] E. R. Lewis et al., Nature Mater. 9, 980 (2010).
[6] J.-Y. Lee et al., Appl. Phys. Lett. 91, 122513 (2007).
[7] K.-S. Lee, et al., Phys. Rev. Lett. 106, 147201 (2011)

The relaxor ferroelectric (1-x)Pb(Mg1/3Nb2/3)O3-xPbTiO3(PMN-PT) has been widely used in transducers due to its excellent piezoelectric properties. Here we propose a new device concept of voltage-controlled magnetoresistive random access memory (MRAM) by integrating PMN-PT with anisotropic magnetoresistive (AMR) element, based on the bistable piezostrain-controlled magnetization switching in the NiFe thin film sputtered on (110)-oriented PMN-PT single crystal. The most remarkable feature of this device is the ultra-low power consumption due to its ideally zero current in the writing process. By applying a DC voltage perpendicularly to the PMN-PT crystal surface, two bistable piezostrain states can be produced. Such elastic strains can be passed to the top NiFe film and would lead to a bistable in-plane magnetization switching of around 30 degree in the latter via magnetoelastic coupling, as demonstrated by our in-situ AMR test. The proposed NiFe/PMN-PT bilayer memory device should provide a simple and new pathway towards high-performance storage devices.

The main bottlenecks limiting the practical applications of current magnetoresistive random access memory (MRAM) technology are its low storage density and high writing energy consumption. Although a number of proposals have been reported for voltage-controlled memory device in recent years, none of them simultaneously satisfy the important device attributes: high storage capacity, low power consumption, and room temperature operation. Here we present, using phase-field simulations, a simple and new pathway towards high performance MRAMs that displays significant improvements over existing MRAM technologies or proposed concepts. The proposed nanoscale MRAM device simultaneously exhibits ultrahigh storage capacity of up to 88 Gb/in2, ultralow power dissipation as low as 0.16 fJ/bit, and room-temperature high-speed operation below 10 ns.

In July 2012 a milestone has been put in the history of semiconductor based non-volatile memories. For the first time a 1 Gigabit product, based on 45 nm technology, has been put on the market in volume production by Micron. The stand-alone memory chip, released for wireless applications, will be included in mobile phone and will offer better performance and lower cost with respect to the state of the art conventional architectures. Aim of the talk is to describe the main technology features focusing on chip architecture, process challenges and specifically developed innovative devices. The developed chip is compatible with the NOR specification enabling the random access to the memory with a reduced latency time of 85 ns, increased read and program throughput with respect to the conventional NOR based solutions. To achieve the goal an innovative bipolar selector has been fabricated, coupled with the so called “wall” cell architecture for the chalcogenide based storage element. The developed cell architecture allows to properly tune the programming current of the cell thanks to the self-aligned heater that enables a reduced active volume involved in the phase transition. An outlook to the future will be also given: a possible path for scaling of the PCM will be illustrated. Chalcogenide material engineering will be presented as a viable way to improve chip performance and enlarge the application spectrum of PCM enabling new products. Finally innovative concept such as the chalcogenide superlattice, will be also discussed as a possible solution to overcome specific PCM limitations that would enable PCM as a “universal memory”.

Phase change memory (PCM) strongly entered the market of high density, fast and non-volatile memory and is expected to replace the current memory technologies. Ge₂Sb₂Te₅ (GST) is the most commonly studied phase change material due to the high resistance contrast between the amorphous and crystalline phases. PCM devices are resistive memory elements where the crystalline (set) and amorphous (reset) states typically have up to four orders of magnitude difference in resistance values. The transitions between these states are achieved through localized self heating with large current densities. Scaling device dimensions improves packing density, speed as well as peak current, power, and total energy requirements for switching. Recent experimental studies have shown that the current confinement can further be enhanced by integrating a thin oxide atop the heater, where the oxide layer is ruptured with application of an initialization pulse, forming a narrow filament in the oxide. This nano-scale filament can be smaller than what is lithographically achievable; resulting in reduced reset current due to smaller active region size and better heat confinement.
In this work, 2D rotational symmetric simulations using COMSOL Multiphysics are utilized to assess the rupture oxide cell with an nFET access device. The joule heating and electric current modules were coupled such that the current continuity and heat transport equations are solved self-consistently. The rupture oxide is modeled as a 3 nm thick SiO2 layer separating the TiN bottom contact and the GST film with a filament in the center with electrical and thermal properties of TiN. The filaments&’ diameter, the width of the transistor, and the supply and gate voltages were varied to study the cell performance.
Rupture oxide cells require less operating power and smaller transistor width compared to the conventional mushroom cells. The behavior of the rupture oxide cell significantly depends on the diameter and resistivity of the filaments formed by the rupturing process.

Phase change material is the heart of phase-change memory (PCM) technology. The development of phase-change materials for PCM has relied on materials originally developed for phase-change rewritable optical storage in the past two decades. Today almost all phase change memory IC&’s still use Ge2Sb2Te5 (GST-225) inherited from optical disk technology, even though high reset current and poor data retention at elevated temperature make it difficult for new applications such as automotive. Many material modifications were made trying to solve these issues however, conflicting material properties between switching speed and thermal stability still persisted. In addition, large programming current is also a key issue that limits the adoption of PCM for advanced applications. In this study, we will discuss how materials engineering and electrode architecture can help make high performance PCM possible.
Firstly, we introduce a special group of Ge1SbxTe1 (GST-1x1) materials located along an isoelectronic tie line with equal amounts of Ge and Te. We selected the best compromise material (GST-212) on the isoelectronic tie line and further enhanced its high temperature stability by moving along a second tie line between Ge and Sb2Te3, taking advantage of the assumption that higher Ge concentration should increase the thermal stability. The “golden” composition was successfully found by maneuvering between these two tie-lines and the promising properties of this new material are demonstrated both at wafer level and in packaged chips [1].
Next, the Ge/N concentration of the “golden” composition is further engineered to meet requirements for automotive application. A laser melt-quenching method is adopted that provides fast turn around retention data on blanket films which are highly predictive for device results. The optimized material demonstrated excellent retention in a 256 Mb test chip with projected 10-year retention at 120 oC, suitable for industrial and some automotive (in-cabin) application [2].
Finally, bottom electrode (BE) engineering for better power efficiency is adopted. The new thermally confined electrode with TaN/TiN/TaN BE has demonstrated 30 uA reset current, representing a 90% reduction compared with solid TiN electrode. The low reset current also improves the reliability and cycling endurance. This dramatic reduction in switching power enables the scaling of the selection device, which in turn allows the scaling of the cell size.
References
[1] H. Y. Cheng, T. H. Hsu, S. Raoux, J.Y. Wu, P. Y. Du, M. BrightSky, Y. Zhu, E. K. Lai, E. Joseph, S. Mittal, R. Cheek, A. Schrott, S. C. Lai, H. L. Lung and C. H. Lam, Tech. Dig.- Int. Electron Devices Meet., 3.4 (2011).
[2] H. Y. Cheng, J. Y. Wu, R. Cheek, S. Raoux, M. BrightSky, D. Garbin, S. Kim, T. H. Hsu, Y. Zhu, E. K. Lai, E. Joseph, A. Schrott, S. C. Lai, A. Ray, H. L. Lung and C.H. Lam, Tech. Dig.- Int. Electron Devices Meet., 31.1 (2012).

Phase change materials (PCMs) are being studied for non-volatile memory applications due to their scalability, fast switching and low power at small dimensions [1]. Recently, performance of nanoscale PCM devices has been examined by confining their bit either as nanowires, or by contacting the PCM with carbon nanotube electrodes [2]. While such structures are useful for scalability and performance analysis, their large-scale integration remains challenging.
In this work, we present the first study of low-power PCM devices with patterned graphene electrodes for wafer-scale integration. The thin structure of these devices (with thin PCM and graphene layers) makes them ideal for flexible and transparent electronics which have strict low-power requirements. In addition, graphene interconnects can also be integrated with conventional CMOS substrates. Our devices switch at threshold voltages as low as ~3 V with low programming currents (<1 mu;A set, <10 mu;A reset) and excellent on/off ratios (>100), enabled by the sharp contact area with their atomically thin graphene electrodes.
Graphene was grown by chemical vapor deposition (CVD) on copper and then transferred to SiO₂/Si substrates [3]. We demonstrate how interconnects ranging from monolayer to several graphene layers can be integrated in this way, depending on circuit requirements. Graphene ribbon electrodes are shaped by lithography and O₂ plasma etching, contacted by Au/Ti metal pads for testing. Memory bits are then defined by e-beam lithography, Ge₂Sb₂Te₅ (GST) sputtering and lift-off. Devices were encapsulated by thin SiO₂ (~10 nm) for stability during testing. GST bit dimensions range from 20-100 nm long and wide by ~10 nm thick.
Electrical measurements, atomic force microscopy and Raman spectroscopy confirm good quality and uniformity of the graphene electrodes. Estimated minimum contact resistivities between graphene and GST in the amorphous and crystalline states are 50 and 0.2 kOmega;mu;m² respectively, comparable to values reported for other GST contacts (e.g. with TiW [4]). Our comprehensive analysis of the first GST-based memories with graphene electrodes is important for future large-scale integration of very low power memory devices. In addition, the techniques demonstrated can also be used for fabrication of other types of memories (e.g. resistive random access memory) with graphene electrodes.
[1] H.-S. P. Wong, et al., Proc. IEEE 98, 2201 (2010); D. Loke, et al., Science 336, 1566 (2012).
[2] F. Xiong, et al., Science 98, 206805 (2011); D. Yu, et al., Nano Lett. 8, 3429 (2008).
[3] A. Behnam, et al., Nano Lett. 12, 4424 (2012).
[4] D. Roy, et al., IEEE Electron Dev. Lett. 31, 1293 (2010); E.K. Chua, et al., Appl. Phys. Lett. 101, 012107 (2012).

The doping of crystalline semiconductors, in particular Si, has proven to be the key technological step that underpins the majority of today&’s electronic technologies. Of all the effects observed, the ability to control the electronic properties of these materials, providing n-type, p-type conducting and insulating regions via ion-implantation, has revolutionised manufacturing and enabled Moore&’s law to continue to be held. Ion-implantation continues to provide new opportunities for technological advances in microelectronics, for example, such methods can also be used to stabilize or activate specific interactions within the materials within localized regions.
Historically, the use of ion-implantation into chalcogenides has been focused on the formation of optical waveguides, rare-earth doping, and the formation of metal (nano) colloids as a means of increasing the non-linear optical response. It is also well established that high-dose ion implantation can be used to form nanoclusters in amorphous materials. The introduction of such clusters has been utilised in ReRAM devices, most notably the metal-chalcogenide memristors take advantage of metal ions through the chalcogenide glass lattice.
In this work, we report first on ion implantation of a broad range of elements into chalcogenide thin films spanning s sulphides, selenides and tellurides. The properties of these films are investigated pre and post implantation. Second, targeting the most promising dopants and chalcogenide compounds, we describe the design, fabrication and characterisation of a series of ion implanted amorphous devices in the Ge:Se family of glasses. The diodes produced show good rectification while at higher electric field exhibiting memory switching behaviour. This suggests the possibility of unique devices exhibit, rectification along with a controlled asymmetric polarity dependant behaviour, which shows great promise in realising next generation synaptic devices.
We believe that through the ion implantation process, in selected chalcogenide materials, a low cost production line method of producing integrated diode/memory cells with next generation cognitive information processing capability can be realised for use in future cross bar array architectures.

The phase change material (PCM) based device is promising to become next-generation main-stream non-volatile memory technology. But its ultimate scaling limit is still unknown. Recent experiments have proven that sub-2 nm PCM nanostructures still keep phase change properties, making the write operations possible in ultra-scaled dimension. However, until now it is still an open question that how small the PCM nanostructures can be scaled, yet still retain adequate ON/OFF ratio for read operations.
State-of-art scaling experiments have shown that 2 orders of magnitude ON/OFF ratio can be maintained if the PCM ultrathin films is scaled down to 6 nm. While sub-6 nm experimental data is not available, here we compute it using purely ab initio simulations. In the simulations, ab initio molecular dynamics, density functional theory, and Green&’s function algorithms are applied. The crystalline GeTe (c-GeTe) and amorphous GeTe (a-GeTe) ultrathin films are sandwiched by the TiN electrodes. Based on the simulation results we point out, for the first time according to our knowledge, that the aggressive scaling might be limited by the loss of adequate ON/OFF ratio, which makes it difficult to reliably perform read operation.
We observed that that the a-GeTe ultrathin films scaled down to about 38 Å (12 atomic layers) still show band gaps and the electrical conductance is mainly due to the electron transport via intra-gap states. If the ultrathin films are further scaled, the a-GeTe band gap disappears due to overlap of the two metal induced gap states (MIGS) regions near the TiN electrodes, leading to sharp increase of a-GeTe conductance and significant decrease of c-GeTe/a-GeTe conductance contrast (i.e. ON/OFF ratio). As a result, the ON/OFF ratio drops below ten if the ultrathin films are scaled below about 33 Å, making it difficult to reliably perform read operations. This sets up an ultimate scaling limit of phase change memory technology. Our results suggest that this ultimate scaling limit can be pushed to even smaller size, by using PCM with larger amorphous phase band gap than a-GeTe.
Reference:
[1]. Jie Liu and M. P. Anantram, “Low-bias electron transport properties of germanium telluride ultrathin films”, (submitted to Phys. Rev. B) http://www.ee.washington.edu/faculty/anant/publications/JieLiuPaper.pdf
[2]. G. E. Ghezzi, “Effect of carbon doping on the structure of amorphous GeTe phase change material”, Appl. Phys. Lett. 99, 151906 (2011).
[3]. L. L. Chang, P. J. Stiles, and L. Esaki, “Electron Barriers in Al-Al2O3-SnTe and Al-Al2O3-GeTe Tunnel Junctions”, IBM J. of Res. and Dev. 10, 484 (1966).

A range of material systems exist in which nanoscale ionic transport and redox reactions provide the essential for switching as platform for reconfigurable electronic devices and biological like computing. One class relies on mobile cations, which are easily created by electrochemical oxidation of the corresponding electrode metal, transported in the insulating layer, and reduced at the inert counter electrode. These devices are termed electrochemical metallization memories (EMC) or conductive bridge random access memories [1]. The material candidates for electrolytes in such devides have been recently studied. They are amorphous chalcogenides [2, 3] and also oxides (SiO2, WO3, TiO2 and others [1]) containing metal elements (Ag, Cu) or their compounds (Ag2S, CuS) and gaining some portion of ionic conductivity and becoming mixed ionic-electronic conductors [3-7].
The aim of this work is to present our current results on syntesis and resistive switching of chalcogenide based nanowire array cells.
The authors thanks to project CZ.1.07/2.3.00/20.00254 “Research Team for Advanced Non-crystalline Materials" realized by European Social Fund and Ministry of Education, Youth and Sports of The Czech Republic within The Education for Competitiveness Operational Programme for financial support.
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[3] M. Frumar, B. Frumarova, T. Wágner, Amorphous and Glassy Semiconducting Chalcogenides. In: Bhattacharya P, Fornari R, and Kamimura H, (eds.), Comprehensive Semiconductor Science and Technology, volume 4, pp. 206-261 (2011)Amsterdam: Elsevier.
[4] S. Stehlík, J. Kolár, M. Bartoscaron;, Mil.Vl#269;ek, M. Frumar, V. Zima, T. Wágner, Sol.
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[6] I. Kaban, P. Joacute;vári, T. Wágner, M. Bartoscaron;, M. Frumar, B. Beuneu, W. Hoyer, N.
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Current Status of NAND Memory
Recently, as NAND memories achieve small cell size, high-speed programming and low Power operation, NAND memories success to replace a part of market of Floppy Disk, DVD, HDD, and recently make many new business markets such as MP3 Player and mobile tablet, etc.
However, the scaling of NAND memories becomes to be difficult by interference phenomena. Moreover, process cost of smaller cell fabrication becomes very expensive and the number of endurance cycles decreases from 1000000 times to 1000 times. Therefore, it is very difficult to replace high volume HDD by current NAND memories, as scaling speed of NAND memories saturate. Moreover, as the scaling speed of NAND memories is faster than the developing speed of lithography, the scaling of NAND memories is limited with lithography trend at 1X nm generation.
3D NAND Technology
- Stacked Vertical NAND Memory -
From viewpoints of overcoming the above issues of conventional NAND memories, stacked vertical NAND memories [1-6] had been proposed. Its cell array structure is three-dimensional (3D) memory array architecture [1]-[3]. The proposed architecture can use all 3D space sufficiently without scaling technology. The structure of the proposed cell arranges bit line contact, first select gate, 2 Vertical type memory cells, second select gate and source line in series vertically in one silicon pillar. The Vertical type memory cell is structured that floating gate and control gate surround the silicon pillar. All devices for the proposed cell are vertically stacked in one silicon pillar, therefore, the stacked vertical structured cell does not need additional area such as bit line contact, 2 select gates and source line, while conventional NAND structured cell needs this additional area. As the number (N) of stacked memory cells in one silicon-pillar increases, the stacked vertical structured cell can reduce to cell area per bit in proportion to 1/N. As a result, the stacked vertical structured cell can realize a drastically smaller cell area per bit than the smallest reported NAND structured cell. The stacked vertical structured cell consisting of 2 stacked memory cells is fabricated. As recently, many type memory cell based on our stacked vertical structured cell technology has been proposed such as BiCS [7] and TCAT [8] with charge trap type cell. Moreover, for realizing high reliable stacked vertical cell, ESCG [9], DC-SF [10], S-SCG [11] and SCP [12] with floating gate type cell was proposed.
From all, 3D NAND memories with the stacked vertical structured cell technology become main technology in future nano-generation high density nonvolatile memory.
[1]T.Endoh, et al. IEICE Trans. Vol.E81-C, No.9, pp.1491, 1998.
[2]T.Endoh,et al. IEEE J. Solid-State Circuits,Vol.34,No.4, 1999.
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[4]T. Endoh, et al, IEDM, pp33-36, 2001
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[6]T.Endoh, et al. 2006 IWDTF, pp. 115 - 116, Nov.8-9, 2006
[7] H. Tanaka, et al, VLSI Symp., pp14-15, 2007
[8] J.H. Jang, et al, VLSI Symp., pp192-193, 2009
[9] M.S. Seo and T.Endoh, IMW, pp146-149, 2010
[10] S.J. Whang, et al., IEDM, pp668-671, 2010
[11] M.S. Seo and T.Endoh, IMW, pp61-64, 2011
[12] M.S. Seo and T.Endoh, IMW, S2-5, 2012

Charge-based flash memory represents the state-of-the-art non-volatile memory technology but further integration and downscaling will face several fundamental and technological challenges. Resistive Switching Memories are an encouraging alternative to flash memories offering low power consumption, fast switching and the feasibility to fabricate highly dense passive crossbar arrays. In these two terminal devices the data storage is based on differently programmed device resistances, e.g. by the formation/dissolution of a metal filament short circuiting both terminals. However, details on the microscopic structure and chemistry of this filament on the nanoscale are still missing. In particular, quantum size modulation of the conductivity based on integer multiples of atomic point contact between the filament and the terminals is discussed. In this work we report on the resistive switching behavior of several material systems including AgI and SiO₂. Quantum size effects at room temperature imply the filamentary character of the switching effect. The stability of controllable quantized conductance values higher than 78 µS is discussed. The results of the study reveal the prospect of an ultimate atomic scale memory.

Memristor, or resistive switching devices [1] are candidates for application as next-generation memory devices and as artificial synapse-neuron systems. Understanding the mechanism of the switching, however, is still a major challenge. We fabricated resistive switching devices by spin-coating ZnO nanoparticles from solution on ITO-coated glass. The devices exhibit ON/OFF ratios as high as 10^5, depending on their voltage history.[2] We selected [poly(9,9-dioctylfluorene-co-benzothiadiazole)] (F8BT) as a probe polymer doped at low concentrations into the ZnO nanoparticle-based device. We then used the technique of electroabsorption spectroscopy (EA), to characterize the internal field in the device, both in air and in vacuum. We find that in air, the device exhibits hysteresis both in current-voltage measurements and in the d.c. bias dependence of the EA response. In vacuum, both hystereses are absent. In addition, we investigated the resistive switching behavior by X-ray photoelectron spectroscopy (XPS) of devices with the top contact removed. By comparing the chemical bonding of oxygen at the Al/ZnO interface with the bulk, as well as between high and low resistance states, the switching mechanism is confirmed to be dominated by the migration of oxygen vacancies in the film under the external electrical field. This migration of oxygen vacancies is associated with the adsorption of molecular oxygen, which changes the injection barrier at the Al/ZnO interface and consequently alters the resistance state of the device.
[1] L. Chua, Appl. Phys. A 102, 765(2011) [2] J. Wang, et al., Phys. Status Solidi A 207, 484 (2010).

The effect of resistive switching in transition metal oxides is a currently very active field due to the possible applications for non-volatile memory applications. In this work we directly monitor the redox-process during resistive switching in the valence change material SrTiO₃ by spatially resolved spectroscopy. Epitaxial Fe-doped SrTiO₃ thin films were grown on conducting, single-crystalline Nb:SrTiO₃ substrates by pulsed laser deposition. After an initial forming sweep bipolar resistive switching is enabled and several pads were programmed to different resistive states. After removal of the top electrode spatially resolved X-ray photoelectron spectroscopy (XPS) and X-ray absorption spectroscopy (XAS) are employed in order to investigate the influence of the resistive switching process onto the electronic structure and chemical composition of the sample. The measurements have been performed with the NanoEsca at Elettra, Triest, where spectroscopic information with a lateral resolution down to 100nm can be gained.
We compared the Sr-XPS, Ti-XAS and O-XAS signal of a virgin pad with “On” and “Off” pads, which have been set to low and high resistive state respectively. On all electrically treated pads several spots with a Sr-O rich surface component are found, which display a characteristic shift of the Sr 3d spectra to lower binding energies. As this effect is independent of the resistance state the evolution of this new component is assigned to the forming process which involves high voltages and currents. Due to Joule heating during the forming process Sr-diffusion might be enabled allowing the formation of a new Sr phase. Exclusively on the pad in low-resistive state a small feature of 300nm diameter with a Ti³⁺ contribution is found. This is interpreted as a signature of a reduced and therefore conducting filament giving rise to the decreased resistance. We will discuss our results with respect to the nanoscale redox-reactions and phase formations involved in the resitive switching process.

Non-volatile memory devices are extensively studied to enable instant-on electronics with reduced energy consumption. One of the most promising memory concepts is resistive switching random access memory (ReRAM).1Some in-situ observations of prototype ReRAM devices indicate presence of conducting filaments (CFs) in otherwise insulating oxide matrix; however, the nature of the filaments is not always clear.2 It is therefore important to investigate how the oxide film is changed by external voltage in order to understand the mechanism of CF formation in the oxide. In this work, we conduct in-situ studies of the crystallization of amorphous TiO2 film under external field, as well as investigate the defects in crystallized TiO2 (c-TiO2) by atomic resolution annular dark filed (ADF) imaging.
TiO2 thin film was deposited on Pt as a bottom electrode, and STM tip (Pt-Ir) was used as the top electrode. The in-situ I-V curve shows a sudden increase of current level near + 4V applied to tip (top electrode), where the crystallization of TiO2 film was also observed in the image diffractograms. Interestingly, if the voltage is gradually increased, the diffractograms show evidence for crystallization at voltages even lower than +4V. The highest characteristic d-spacing of the initially forming c-TiO2 is about 0.24 nm, which could correspond to the (013) spacing of anatase or (212) spacing of rutile structure. As the voltage is increased, the area of the c-TiO2 is gradually extended from the bottom electrode to the top electrode. In addition to the voltage-dependent crystallization of TiO2, which starts happening at very low voltages, higher voltages (~9V and up) induce stacking faults in grains near bottom electrode, and eventually much higher lattice spacings characteristic of Magneli phases. The formation of these defects is caused by voltage-induced transport of oxygen ions. Spectroscopic examination of these and other related bias-induced defects in TiO2 will also be discussed.
* Research (JHJ, YK, YMK, DNL, SVK, AYB) supported by the U.S. Department of Energy (DOE), Basic Energy Sciences (BES), Materials Sciences and Engineering Division, and through a user project supported by ORNL&’s Shared Research Equipment (ShaRE) User Program, which is also sponsored by DOE-BES and AFM studies (SJ) were sponsored in part by Center for Nanophase Materials Sciences, both supported at Oak Ridge National Laboratory by the DOE-BES. This work was supported by Korea Research Council of Fundamental Science and Technology through KRISS project and in part by Future-based Technology Development Program (Nano Fields) through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (Grant No. 2011-0030200) and JHJ also was supported by NRF (Grant No. 2012-0005637).
References
[1] R. Waser, et al., Adv. Mater. 21 2632 (2009).
[2] Y. Yang, et al. Nat. Com. 3 732 (2012).

Recently, there has been a spurt in research activities to develop next generation low power, high speed, rugged, high density and nonvolatile resistive random access memory (RRAM) devices based on amorphous binary and multinary dielectric oxides. The memory effect in these devices is realized through switching of the resistance of the device between the two states (high and low) of resistances. Amongst other materials currently being explored for the development of RRAM, lanthanum based high-k oxides have emerged as potential candidates. In this paper we report, for the first time (to the best of our knowledge), the growth of RRAM devices based on amorphous thin films of LaGdO₃ (LGO), their resistive switching characteristics, and associated conduction mechanisms.
About 50 nm thick amorphous LGO films were grown on commercial Pt/TiO₂/SiO₂/Si substrates using pulsed laser deposition at a substrate temperature of ~ 300°C and oxygen partial pressure of ~ 2×10^-3 Torr. To construct MIM capacitor the top electrodes of ~ 70 nm thick Pt film with a typical diameter of ~ 80 µm were used. The switching characteristics and endurance of these devices were studied through current-voltage (I-V) measurements in the top-bottom configuration. The as grown devices were found to be initially in high resistance state (HRS) ~ 40 M#8486; and did not show any resistance switching behavior until the applied bias voltage was increased to ~7 V (initial forming voltage) with a current compliance of 5 mA at which the resistance of the device dropped suddenly to a low value of ~ 10Omega;. After this initial forming process, which rendered the device in low resistance state (LRS), as the voltage was swept from 0 to 1 V switching of the device from LRS to HRS (ON state) was observed at a voltage of ~ 0.6 V. The RRAM device again switched to LRS (OFF state) at ~ 2.5 V as the voltage was swept from 0 to 4 volt. The repeatable nonvolatile switching of the resistance of RRAM device between LRS and HRS was obtained with nearly constant resistance ratio ~ 10⁶ and well defined and non-overlapping switching voltages in the range of 0.6-0.75 V and 2.5-4 V respectively for up to 25 test cycles. The current conduction mechanism of the device in LRS and HRS were found to be dominated by the Ohmic behavior and Poole-Frenkel emission respectively. The temperature dependent measurements of the resistance of the device indicated metallic and semiconducting conduction behavior in LRS and HRS respectively. The resistance of LRS and HRS of the device read at 0.1 V, showed no obvious degradation for up to ~ 10⁴ s indicating good data retention. A similar switching characteristic was also observed at elevated temperatures of up to 500K. In summary, the observed reproducible resistive switching, large HRS/LRS ratio, good retention and endurance, nonvolatility, and amorphous structure along with high dielectric constant make LGO as a promising material for the future nonvolatile RRAM devices.

Resistive switching characteristics of the multilayer of Fe2O3 and Pt-Fe2O3 core-shell nanoparticles (NPs) were investigated. The Fe2O3 and Pt-Fe2O3 core-shell NPs were chemically synthesized with a diameter in the range of 10~15 nm. The Fe2Onot;3 NPs were synthesized through decomposition of Fe(CO)5 precursors and subsequent oxidation in the colloidal solution. The Pt-Fe2O3 core-shell NPs were synthesized through the decomposition and reduction of Fe and Pt precursors, and subsequent preferential oxidation of Fe for shell formation and pile-up of Pt into the core in the colloidal solution. First, the structure of Ti-top-electrode/Fe2O3 NPs-layer/Pt electrode was fabricated by assembling Fe2O3 NPs as a continuous layer on Pt electrode by repeated dip-coating and subsequent Ti top electrode deposition by sputtering with electrode diameter of 300 mu;m. Also, the multilayered NPs structure of Ti-top-electrode/Pt-Fe2O3 core-shell NPs-layer/Fe2O3 NPs-layer/Pt electrode was fabricated by the same procedures. The structure with only Fe2O3 NPs layer exhibits the memristive switching with gradually changing resistance as repeating the voltage sweep. On the other hand, the structure with multilayer of Fe2O3 and Pt-Fe2O3 core-shell NPs shows the bipolar switching after forming operation. During bipolar switching, the resistance was also gradually changed in both high and low resistance states. In this presentation, the detailed resistive switching characteristics of NPs layers will be discussed for the nonvolatile resistive memory or switching devices.

ReRAM device is a non-volatile memory based on resistive switching phenomena in a dielectric inserted between two metallic electrodes. Depending on the nature of the oxide and the metallic electrode, the switching is based on a unipolar thermochemical mechanism, a bipolar valence change mechanism, as well as a bipolar electrochemical metallization mechanism. In the last five years, many oxides have been studied and tested in small devices with fast switching for crossbar memory applications. But a large integration density would require improvement of yield and reducing variations in the switching behavior. Difficulty is that set operations are not only strongly modified by the oxide (nature, crystallization, density, doping, and vacancies) but also by metal (morphology, affinity to oxygen, work function) as well as the interfacial layer (role of the electrode, role of the process).
We have already demonstrated the possibility to use HfO2 (deposited by Atomic Layer Deposition) in ReRAM [1]. In this presentation, we propose a global model for the understanding and optimization of mechanisms at the origin of Set and Reset processes in HfO2 ReRAM. Some examples are given hereafter.
1) Oxygen vacancies: CVS (Constant Voltage Stress) experiments present progressive increase of conductivity along time depending of the bottom and top electrodes metal. This increase is identified to stress induced leakage current set by the competition of two reactions at the anode: Vo++ defects generation by hot electron injection and their recombination with O2- [2]. An oxygen depletion layer localized at the anode has been clearly identified using TEM pictures and seems correlated to preferential injections through grain boundaries as proposed by Bersuker et al [3].
2) Reset: a comparative study of several different electrodes has shown that reset phenomenon occurs for materials presenting a moderate affinity to oxygen (Ti, Cu,) and for which the enthalpy of formation of the corresponding oxide is lower than enthalpy of formation of hafnium dioxide. We also found that the electrode morphology (roughness, thicknesshellip;) induced by the deposition process, as well as doping of the top electrode can strongly modify the oxygen reservoir effect, and so the the back diffusion of oxygen ions released at the set voltage.
3) Reliability: CVS measurements for samples with Pt based bottom electrodes have shown a delay in oxide degradation for samples that can be related to a limited electron injection. Hence, the work function criterion is important to prevent high electron injection at the bottom which can totally degrade the oxide. This effect was noticed for samples with TiN bottom electrodes. However, we have shown that NH3 plasma treatment can ward off this effect by changing the metal oxide nature.
[1] P. Gonon et al, J. Appl. Phys.107 (2010) 074507
[2] C. Mannequin et al, J. Appl. Phys.112 (2012) 074103
[3] G. Bersucker et al, J. Appl. Phys.110 (2011) 124518

Resistive random access memory (RRAM), especially transition metal oxide based valence change memory (VCM), has become a leading candidate for next-generation nonvolatile memory due to its high endurance, fast switching speed and excellent scaling potential.^{1, 2} RRAM devices integrated in passive crossbar arrays can potentially offer the highest stacking density in theory and low energy consumption, provided that a select element or some sort of select effect can be introduced to address the “sneak path” problem. As a material system of rapidly increasing research interests, tantalum oxide based VCM which typically consists of a Ta₂O₅/TaO_x bilayer structure as the functional layer has demonstrated very promising performance, in particular endurance.² However previous studies showed that the on-state of these devices has linear current-voltage characteristics,^{3, 4} which make the device susceptible to the sneak path problem. In principle, the sneak path problem can be mitigated by introducing nonlinearity in the on-state of RRAM devices.⁴ In this work, we show promising RRAM performances including write/erase endurance and nonlinearity, which represent two critical performance metrics for RRAM devices, can be effectively obtained by engineering the combination, stoichiometry and thickness of different transition metal oxide films. While Ta₂O₅/TaO_x based VCM showed high endurance and linear on-state, nonlinearity was obtained when the TaO_x layer was replaced by TiO_x to form a Ta₂O₅/TiO_x bilayer structure. However, in this case the endurance was compromised to ~100, similar to conventional TiO_x based RRAM devices. To obtain the desired nonlinearity and high endurance simultaneously, a trilayer Ta₂O₅/TaO_x/TiO_x stacking was developed, where nonlinear on-state and endurance of >55,000 were experimentally demonstrated simultaneously. Devices with different sizes ranging from 50 × 50 nm² to 1 × 1 µm² were fabricated and studied systematically. The results indicated that the superior endurance and nonlinearity are intrinsic to the TaO_x and TiO_x layers and their interfaces. Detailed material analyses through in situ transmission electron microscopy (TEM) and x-ray photoelectron spectroscopy (XPS) have been carried out to illustrate the roles of the different layers during resistive switching and to explain the origin of the endurance and nonlinearity in different device configurations.
References
1. R. Waser, R. Dittmann, G. Staikov, K. Szot, Adv. Mater. 21, 2632 (2009).
2. M.-J. Lee et al., Nat. Mater. 10, 625 (2011).
3. Y. Yang, P. Sheridan, and W. Lu, Appl. Phys. Lett. 100, 203112 (2012).
4. J. J. Yang et al., Appl. Phys. Lett. 100, 113501 (2012).

Among candidates for next generation non-volatile memory, resistive random access memory (ReRAM) has become a strong contender due to superior properties when compared to flash memory. ReRAM devices constituting metal-insulator-metal (MIM) structures, where the insulating material is a transition metal oxide, have been widely investigated to distinguish possible mechanisms that govern controllable resistive switching. The filamentary model, which invokes conductive filaments extending from either metal layer through the insulator, either in the form of extended defects such as dislocations [1] or conductive Magnéli phases [2], is one possible resistive switching mechanism. Evidence for filamentary dislocations has been in the form of conductive spots observed by conductive atomic force microscopy in SrTiO3[3].
In this study, we show that SrTiO3-based MIM devices can exhibit resistive switching with confirmation that no dislocations are present in the device, before and after electrical testing. We do this by tracking dislocation content in lateral MIM devices before and after resistive switching. The lateral MIM structures are Pt thin film pads sputter deposited on SrTiO3 (001) substrates. A SiNx dielectric layer is used to isolate SrTiO3 from the Pt pads that are electrically connected to external electrical probes from the actual Pt electrodes, reducing the electrode area to less than 1µm2. Electron channeling contrast imaging (ECCI) and dislocation selective wet chemical etching are used to track dislocations before and after electrical testing. ECCI is an implementation of diffraction contrast in the scanning electron microscope (SEM), and is directly sensitive to the position of dislocations in SrTiO3.
Results show that by fabricating devices on dislocation free areas of single crystalline SrTiO3, resistive switching devices can be made to function with similar electrical characteristics as devices fabricated on areas with pre-existing dislocations. In both cases we intentionally control the device size, substrate reducing conditions and compliance currents during electrical testing in order to minimize power dissipation and thereby limit new dislocation formation.
All switching devices show bipolar resistive switching with counter-eightwise polarity suggesting charge trapping is not the prevailing mechanism [4]. While this study calls into question the notion of filamentary switching via dislocations for SrTiO3, further TEM investigations are underway to detect possible volumetric filaments such as Magnéli phases [5] or localized oxygen vacancy redistribution.
[1] Szot et al, Physica Status Solidi (RRL) - Rapid Research Letters (2007), Vol 1, Issue 2.
[2] Szot et al, Nanotechnology (2011), Volume 22
[3] Szot et al, Nature Materials (2006), Vol 5, Issue 4.
[4] X. Sun, G. Li, L. Chen, Z. Shi, and W. Zhang, Nanoscale Research Letters (2011) 6, 599.
[5] M. Fujimoto and M. Watanabe, Journal of Materials (1985) 20, 3683

The ultimate scaling limit of resistive memory and prospects for multi-level logic are being actively pursued worldwide. An open question is: “What is the minimum feature size that theory allows so that a large enough ON/OFF ratio is possible?”. To answer this question, we consider alumina with a copper based active electrode [1]. While bare alumina with no copper intercalation has a high resistance, the intercalation of copper atoms in alumina leads to the low resistance state. Our main findings are that the alumina layer can be scaled down to approximately 1.3 nm and yet lead to an ON/OFF ratio of larger than one hundred. A three atom copper filament in a 1.3 nm thick layer of alumina has a low bias resistance of only 21 kilo-Ohms. Increasing the thickness of this filament to seven atoms causes the low bias resistance to increase to 35 kilo-Ohms, which is a counter intuitive result. This means that in the ultimate scaling limit, the detailed control of atom location is essential. When the applied voltage is increased to larger than 100 mV, the differential resistance of the three atom copper filament increases dramatically to over 500 kilo-Ohms while that of the seven atom copper filament decreases to values below 35 kilo-Ohms. The evolution of the differential resistance with bias voltage is surprising. The underlying physics can be rationalized by looking at the transmission between the two metal contacts. The smallest copper atom chains have a large transmission over a narrow energy window, which dramatically drops of, away from the transmission peak. In contrast, the wider atomic filament has a broader transmission peak as a function of energy, which explains the more uniform differential conductance observed with bias voltage. This makes the resistance of these atomic filaments very sensitive to the location of the Fermi energy in the system as demonstrated. Filaments of various lengths and diameters are considered to demonstrate the change in conductance, arising from the movement just a few atoms, which points to the potential for multi-level logic. Methods: We calculate the current-voltage characteristics using a combination of first principles electronic structure and Green&’s function calculations. The transport calculations in the coherent limit use the methods in reference [2]. The material system consists of two copper electrodes with alumina of various thicknesses between them. The system considered is quite large and consists of over 200 atoms. The location of atoms are obtained from a large number of energy minimization calculations using SIESTA [3]. [1] Xu Xu et al, Resistance of atomic scale copper filaments for memory applications, http://www.ee.washington.edu/faculty/anant/publications/XuXuPaper.pdf ; [2] M. P. Anantram and A. Svizhenko, IEEE Trans. Elec. Dev., v. 54, p. 2100-2115 (2007) ; [3] J. M. Soler, et al, J. Phys.: Condens. Matter, 14, 2745 (2002)

Resistive random access memories (ReRAMs) are expected to be a promising candidate for next-generation memories to meet both low electric power consumption and high switching speed [1]. A ReRAM cell often adopts a structure with a transition-metal oxide layer being sandwiched by two metal electrodes [2,3], where formation and destruction of conductive regions in the oxide layer correspond to the “ON” and “OFF” states, respectively, in response to the polarity of bias voltage applied to the metal electrodes. Among theoretical modeling studies of the switching mechanisms, first principles calculations have revealed that the “ON” states originate from the defects in the oxides, including oxygen vacancies [4-7], dual defects of oxygen and metal vacancies [8] and metal interstitials [9], depending on the metal elements in the oxides and combinations of the electrodes and oxides.
In this work, we present the electric current (I)-voltage (V) characteristics (-0.5 eV < V < +0.5 eV) of ReRAM devices with metal-oxide-metal structures, based on first principles nonequilibrium Green&’s function (NEGF) theory. We choose hafnia (HfO₂) as a representative example of the oxides used for ReRAMs. We calculate the I-V characteristics for two kinds of metal electrodes, Ta and W. For Ta, a clear distinction between the “ON” and “OFF” states appears for hafnia with and without oxygen vacancies (V_Os), respectively. For W, however, the electric current hardly flows irrespective of whether or not the V_Os exist in hafnia. We analyze the I-V characteristics using the Breit-Wigner formula with the effective molecular projected state Hamiltonian (MPSH) [10]. Calculated real and imaginary parts of the complex energy terms show that the interaction between the W and HfO₂ layers is much weaker than the Ta-HfO₂ counterpart. Judging from the obtained results, we conclude that not only formation of the conducting regions in HfO₂ but also a substantial coupling between HfO₂ and electrodes is an essential factor to achieve a high ON-OFF contrast at low bias voltages.
[1] H. Akinaga and H. Shima, Proc. IEEE 98, 2237 (2010).
[2] R. Bruchhaus and R. Waser, in Thin Film Metal-Oxides: Fundamentals and Applications
in Electronics and Energy, Springer Science+Business Media, LLC 2010, p.131.
[3] A. Sawa, Mater. Today 11, 28 (2006).
[4] H. D. Lee, B. Magyari-Kope, and Y. Nishi, Phys. Rev. B 81, 193202 (2010).
[5] B. Magyari-Kope et al., Nanotechnology 22, 254029 (2011).
[6] B. Magyari-Kope, S.-G. Park, H. D. Lee, and Y. Nishi, J. Mater. Sci, 47, 7498 (2012).
[7] H. Kishi et al., Jpn. J. Appl. Phys. 50, 071101 (2011).
[8] K. Oka et al., J. Am. Chem. Soc. 134, 2535 (2012).
[9] Y. Y. Chen et al., Appl. Phys. Lett. 100, 113513 (2012).
[10] H. Nakamura et al., J. Phys. Chem. C115, 19931 (2011).

Resistive switching (RS) in transition metal oxides is a subject of growing interest, not least because of the potential RS holds to replace Flash and DRAM as a non-volatile memory storage medium in personal computing. Nanoscale RS components have been studied, but there remain many challenges associated with fabrication on a large scale. Here we form random networks of Ni/NiO core/shell nanowires, a well-known RS material, and demonstrate the facile fabrication of RS devices with on/off ratios of > 10^4. Building upon previous work carried out on random networks of polymer coated metal nanowires, we demonstrate that the behaviour of the network is dependent upon the length scale over which it is interrogated. Helium ion microscopy is utilized to visualize, in a unique way, the connectivity pathways within networks, and to verify this behaviour.

To integrate cross-point (4F^2) ReRAM device array, we need to develop bi-directional selector device to suppress the sneak current path through the unselected devices. Although various candidates with selector properties were recently reported, several problems such as insufficient current density at set/reset operations for nano-scale devices, low selectivity, and poor endurance have been raised.
In this paper, we report two types of selection devices, called the varistor-type bidirectional switch (VBS) and NbOx based threshold switching device with excellent thermal stability.
A highly non-linear VBS showed superior performances including high current density (>3x107A/cm^2) and high selectivity (~10^4). Ultrathin NbO2 exhibits excellent TS characteristics such as high temperature stability (~160C), good switching uniformity, and extreme scalability.

Nowadays, an idea that redox reaction caused by migration of oxygen ions or vacancies is widely received as a resistive switching mechanism of resistive random access memory (ReRAM). However, there are still open issues that should be solved to prove the validity of the idea, such as, "where is oxygen pool, that is, an unbalance introduced into oxygen distribution by forming and set processes?" and "what is a role of electrodes in resistive switching effect?". In addition, memory characteristics of a single filament that is confined in a very small memory cell is important in terms of practical use, since ReRAM is one of a strong candidate for substitution of Flash after generations smaller than 20 nm.
To solve these issues, we established a method to prepare a very small ReRAM cell composed of a Pt-top electrode (Pt-TEL)/NiO structure fabricated on the tip of a cantilever of atomic force microscope (AFM) and a bottom electrode (BEL) that is independent of the (Pt-TEL)/NiO structure. Since this method provides very small ReRAM cell having removable BEL, unique experiments to clarify a location of oxygen pool and a role of electrodes can be performed.
A Pt film with thickness of 50 nm was deposited on a cantilever with the tip radius of 50 nm (SII SI-DF3-R(100)) as a top electrode (TEL), followed by deposition of a NiO film with thickness of 20 nm as a memory layer. Line shaped Pt-BEL with small capacitance of 3 pF and large resistance of 100 kOmega; was prepared as a current limiter with small parasitic capacitance. Pt/NiO/Pt structure is formed by contacting the Pt-BEL with the Pt/NiO structure located on the tip of the cantilever.
Non-polar resistive switching was observed in this Pt/NiO/Pt structure. This result suggests that the resistive switching is not caused by oxygen or moisture in the atmosphere, because it is expected that the atmosphere affects the NiO/BEL interface only. High and low resistance data were programmed and data retention was investigated after changing the position where the tip of the cantilever contacts the BEL from the position where the data were programmed to other position. As a result, both high and low resistances data were retained independent of bias polarity used to program the data. This suggests that oxygen pool does not exist in the Pt-BEL but exists in the NiO film. The unique structure enables acquisition of entirely new knowledge closely related to the resistive switching effect.

Resistive random access memories (RRAMs) have attracted much attention due to its significant features such as high data density, high operation speed and simple structure (metal-oxide-metal). The operation of RRAM is based on the resistive switching (RS) stimulated with the applied electric field; however, the mechanism of RS is highly dependent on the materials and processes.
In this work, the Al/ZnO nanoparticels (ZnO NPs)/ITO RRAM device is fabricated to investigate the influence of temperature on our device and the possible RS mechanism. The solution processed ZnO NPs are nano-crystals with grain size about 3nm confirmed by AFM and TEM and are spin-coated onto ITO substrate as the bottom electrode (BE). The Al top electrode (TE) is deposited by thermal evaporation. At room temperature, the Al/ZnO NPs/ITO device shows a bipolar RS characteristic, which has the set voltage (V_Set) around -1V and the reset voltage (V_Reset) about 0.5~1V. From the I-V characteristics, it is found that the space-charge-limited current (SCLC) is the possible current conduction mechanism at high resistance state. Nevertheless, the currents flowing through our devices are temperature dependent, which is conflict to the SCLC conduction. Accordingly, we propose the possible RS mechanism model using the ion migration to account for the SCLC conduction phenomenon.

Typical bipolar, [1] self-rectifying, [2] and switchable diode [3] current-voltage (I-V) characteristics were reported in all kinds of resistive memory systems under different current compliance. Nevertheless, multimode switching characteristics, i.e., all three types of characteristics appearing in a single memory device have not been realized yet. In this presentation, we report multimode resistive switching in single-crystalline ZnO nanoislands when applying different current compliance.
Self-assembled ZnO nanoislands were grown on Si (100) substrates by plasma-assisted molecular beam epitaxy. Scanning electron microscopy and high-resolution transmission electron microscopy results show that these nano-islands are single crystal with diameter and height around 30nm and 40nm, respectively. There are lots of oxygen vacancies in these nanoislands according to the photoluminescence results.
During I-V characterization, Co/Cr coated conductive atomic force microscopy (C-AFM) tip was used as top contact. The nanoisland firstly underwent a voltage sweep from 0 to 10 V under a current compliance of 5nA. Then the nanoisland underwent four voltage sweep processes sequentially (process (1): 5 to 0V; process (2): 0 to -5V; process (3): -5 to 0V; process (4): 0 to 5V). Under the current compliance of 10 nA, 100nA-10µA, and 50µA-1mA, the voltage sweep processes resulted in three types of resistive switching behavior, namely switchable diode, self-rectifying bipolar and typical bipolar.
When the current compliance is lower than 10µA, C-AFM results show that the current in the ON-state ZnO nanoisland are non-localized. The overall electric fields in the ZnO nanoisland are opposite after process (2) and (4), respectively, according to piezoresponse force microscopy results. These results indicate that the switchable diode and self-rectifying types of switching are controlled by the movement of oxygen vacancies in ZnO nanoisland between the C-AFM tip and Si substrate. The bipolar resistive switching is controlled by the formation and rupture of conducting filaments consisting of oxygen vacancies according to the results of high localized current mapping of C-AFM and transformation of Zn metal onto C-AFM tip during I-V characterization in high space reslution Auger electron spectroscopy.
(1) K. Nagashima, T. Yanagida, K. Oka, M. Taniguchi, T. Kawai, J. Kim, B. H. Park, Nano. Lett. 2010, 10, 1359-1363.
(2) S. H. Jo, W. Lu, Nano Lett. 2008, 8, 392-397.
(3) L. E. Hueso, I. Bergenti, A. Riminucci, Y. Zhan, V. Dediu, Adv. Mater. 2007, 19, 2639-2642.

Resistive switching memory (RSM) has been reported as a prominent candidate of next-generation nonvolatile memory. 1 Recently, nanoscale RSM has also been linked to the reconfigurable logic applications and the concept of memristors for analogue circuit and neuromorphic computing applications. 2 It is generally believed that the crossbar resistive memory array will yield the most cost-effective solid-state memory. However, each memory cell needs a Zener diode to avoid the misreading caused by the sneak current. 3 This situation presents extra challenges for the development of 1D1R-based bipolar resistive memory arrays, especially in 3-dimensional multi-layer stack. Furthermore, a current compliance is indispensable to prevent RSM from hard breakdown. In this presentation, we report current self-rectifying and self-complianced resistive switching in single Na-doped ZnO nanowire, which can suppress sneak current and prevent RSM from hard breakdown in crossbar arrays.
Na-doped and undoped ZnO nanowires were grown on a Si (100) substrate with 10nm Au catalyst on top in a quartz tube furnace system. The single-nanowire devices were fabricated by transferring ZnO nanowires onto an n-type Si substrate capped with thermally oxidized SiO2 layer and depositing 100nm Ag as contacts after standard photolithography process.
Scanning electron microscopy (SEM) and secondary ion mass spectroscopy results show that Na was doped into the ZnO nanowire and Na doping induced the tilted growth of nanowire on substrates. The Na-doped ZnO nanowire has typical ZnO single crystal structure which grows along [0001] direction according to high resolution transmission electron microscopy results.
Typical I-V characteristics indicate that Na-doped ZnO nanowire device shows bipolar resistive switching with excellent retention and DC sweeping endurance, which has the self-compliance property with current around 10 mu;A and self-rectifying property with rectifying ratio of 105 at low resistance state (LRS). Undoped ZnO nanowire device shows typical bipolar resistive switching, which needs external current compliance.
SEM images and high spatial resolution Auger electron spectroscopy results show that Ag atoms were transferred onto ZnO nanowire during I-V characterization, which indicate that the resistive switching was controlled by the formation and rupture of Ag nano-island chain on the surface of the nanowire. The self-compliance is induced by Na-doping and partially retraction of Ag from the nanoisland chain while the self-rectifying behavior is mainly originated from asymmetric contact between nanowire and Ag contact induced by Na-doping and Ag atom segregation and doping.
(1) R. Waser et al, Nat. Mater. 2007, 6, 833.
(2) J. Borghetti et al, Nature 2010, 464, 873.
(3) Q. Zuo et al, J. Appl. Phys. 2009, 106, 073724.

Study and fabrication of nanoscale non-volatile memory is an important subject of current research as the conventional memory is approaching its physical limits. As resistive switching phenomenon observed in various transition metal oxides is highly localized in nature, these resistive switching devices seem to be ideally suited for improving scalability and miniaturization, both in lateral and vertical dimension. In this context it may be mentioned that conductive atomic force microscopy (CAFM) technique provides a direct means to visualize the conducting filaments, ascertain their spatial distribution and measure their I-V characteristics along with nanoscale switching from low resistance state (LRS) to high resistance state (HRS) or vice versa. The present study is based on two sets of measurements and carries out a detailed comparison of the scanning probe resistive switching with the conventional macroscopic pad contact switching by measuring the statistical distribution of size and current level of filamentary regions in LRS and HRS. In the first experiment, switching has been performed over macroscopic pads of dimension 25×25 µm2, and thereafter, focussed ion beam (FIB) has been used to etch out a portion of the pad and expose the underlying Cu2O memory layer. The electrical properties of the LRS and HRS of the Cu2O layer exposed after FIB etching have been studied by employing CAFM only as a nanoscale probe by using a low bias value. Subsequently, in the second experiment CAFM tip has been used directly for electroforming, reading and writing of the Cu2O memory cells. The CAFM study of 25×25 µm2 device in LRS or HRS switched by macroscopic pad I-V shows conductance ratio between LRS to HRS of 2.5 x 104. In comparison, in case of CAFM tip based switching, the conductance ratio between LRS to HRS is found to be 8.3 x 104. These results show that the scanning probe switching is more efficient as compared to macroscopic pad electrode in switching individual filaments. This can be related to the CAFM tip operating in the spreading resistance mode with current path initiating from the tip and spreading towards the bottom electrode, resulting in formation and annihilation of conducting filaments in the close vicinity of tip-sample interface. Statistical analysis of the CAFM images shows that the filaments sizes follow the Gaussian distribution, where the average size is between 40-60 nm for the ON state and for the OFF state the average size reduces to less than 40 nm because of the partial reduction of filaments. The CAFM tip was also used to switch four neighbouring memory cells having dimension 400 × 400 nm2. It was observed that the size and current level distribution of a device depends upon the state (ON or OFF) of the neighbouring device. This study sets the foundation for fabricating nanoscale resistive memory devices.

RRAM is a promising nonvolatile memory with properties such as high speed switching, simple structure, and good data retention. Due to the simple structure and the demand of high integration density, cross-bar arrays are proposed to fulfill the requirements. However, the sneak path would become a serious problem when we apply the structure to application. Thus, a novel oxynitride memristor was fabricated to investigate the properties of RRAM and try to solve the encountered questions. The oxynitride thin film was deposited by reactive sputtering and was tuned under different oxygen partial pressure in order to get a better RRAM characteristic. By controlling the proportion of oxygen and nitrogen, we could control and investigate our RRAM characteristic easily. The reactive sputtering also brought another advantage on the electrical properties, namely, the sputter-formed interface between the oxynitride and electrodes, exhibiting the non-linear I-V behavior. By choosing proper electrodes and insertion layers, we are able to demonstrate the complementary resistive switching (CRS) behavior by merely a single-step process. In addition, the obvious diode characteristic can be found after multi-step sputtering processes. Interestingly, the current difference can be achieved into 3 orders of magnitude by a single layer without any further stackings or designs. The switching mechanisms were proposed based on material analyses of the oxynitride film to realize the cross-bar arrays into industrial applications.

The fabrication of thin (5-10 nm) transition-metal oxide/suboxide heterostructures with well-controlled composition or doping profiles is critical for studying resistive switching processes and for the large-scale fabrication of reliable ReRAM devices. This is normally achieved using techniques such as chemical vapour deposition (CVD) or atomic layer deposition (ALD) but accurate control of the film stoichiometry is nontrivial. Ion-implantation offers an alternative means of fabricating oxide/suboxide heterostructures, either by direct synthesis of the oxides using oxygen implantation of a metal film, or by modification of a pre-deposited oxide film. In this study, ion-implantation was used to fabricate Ta₂O₅/TaO_x heterostructures by high fluence O ion-implantation into sputter-deposited Ta films. Ta films of 20 nm or 50 nm thickness were implanted with 10 keV and/or 2 keV O-ions to fluences in the range 1x10¹⁷-5x10¹⁷ O.cm^-2. Physical characterisation of the implanted layers using transmission electron microscopy and x-ray photoelectron spectroscopy showed that suitable oxide/suboxide heterostructures could be fabricated by appropriate choice of the implantation parameters (energy, fluence). For example, films implanted with 10 keV O⁺ to a fluence of 3x10¹⁷ O.cm^-2 have a stoichiometric Ta₂O₅ layer extending from the surface to around 16 nm and a graded suboxide layer extending from 16 nm to 30 nm. Electrical characterization of the films, included dielectric breakdown tests and resistive switching measurements (set/reset resistance ratios and endurance), confirmed that this approach has promise for high volume manufacturing of resistive switching memory devices based on oxide/suboxide heterostructures.

Resistive Random Access Memory (ReRAM), which makes use of resistive switching (RS) behavior observed in various kinds of oxides such as NiO and HfO_x, is a promising candidate for next-generation nonvolatile memories [1]. In ReRAM operation, one of obstacles is a creation process of defect-related conductive filaments, called forming, because it generally needs larger voltage than set processes [1]. Thus, forming voltage (V_Form) should be reduced. In addition, resistance in the initial state of RS cells (R_Ini) must be large enough to keep sufficient resistance ratio. In previous publications on NiO-based RS cells, the changes of R_Ini and V_Form by varying the oxidation temperature or time of Ni have been reported [2, 3]. In those reports, low-V_Form RS cells generally exhibit low R_Ini, namely low V_Form and large R_Ini are not simultaneously achieved. We present that the O₂ flow in sputtering NiO films as well as post annealing processes significantly influences V_Form and R_Ini of NiO-based RS cells, and that R_Ini can be greatly increased while maintaining low V_Form by controlling these conditions.
NiO films were deposited on Pt/Ti/SiO₂/Si substrates by rf sputtering using a metal Ni target in the Ar+O₂ atmosphere. During deposition, the substrate temperature, total gas flow, and the ambient pressure were kept at 350°C, 9 sccm, and 0.6 Pa, respectively, while the O₂ flow was varied from 1.0 to 1.3 sccm with an increment of 0.1 sccm. The thickness of NiO films is about 80 nm. As top electrodes (TEs), Pt with a thickness of 100 nm was deposited to fabricate Pt/NiO/Pt RS cells with the diameter of 50 mu;m. Hereafter, NiO films sputtered with O₂ flow of X sccm are denoted as NiO(X).
The oxygen composition (O/Ni) of NiO films determined by Rutherford backscattering spectrometry increased with the increase in O₂ flow from 1.04 in NiO(1.0), and was saturated at 1.21 in NiO(1.2-1.3). In a similar manner, R_Ini increased with O₂ flow from about 300 Omega; in RS cells with NiO(1.0), taking a maximum of about 400 kOmega; in RS cells with NiO(1.2). V_Form also increased from about 2 V to about 15 V with the increase in O₂ flow, showing no saturation trend. Concerning RS cells with as-deposited NiO films, RS cells exhibiting low V_Form exhibit low R_Ini as reported in [2, 3]. Then, aiming at increase in R_Ini, NiO films were annealed at 450°C in Ar atmosphere before TE deposition. By the annealing of NiO(1.1-1.3), both R_Ini and V_Form were increased from 10 k - 400 kOmega; to 900 k - 2 MOmega; and from 3-15 V to 6-22 V, respectively. On the other hand, V_Form of RS cells with NiO(1.0) remained low (~2 V), while R_Ini was increased from ~100 Omega; to ~100 kOmega; by the annealing. Furthermore, it has been revealed by conductive-atomic force microscope observation that the increase in R_Ini is due to the increase in resistivity of NiO grains, not grain boundaries.
[1] H.-S. P. Wong et al., Proc. IEEE, 100, 1951 (2012). [2] I. G. Baek, et al., IEDM 2004, 587. [3] L. Goux et al., TED, 56, 2263 (2009).

Hafnium oxide (HfO2) is an attractive material for resistance-change memory (RRAM) due to its demonstrated resistance switching ability and its existing use as a high-k dielectric in current CMOS processes. However, despite extensive experimental investigation of hafnium oxide for use in advanced gate stacks and RRAM cells, much of the underlying physics in HfO2 RRAM is poorly understood.
In this research, factors in the resistive switching of TiN/HfO2/TiN cells were investigated. First, the dependence of HfO2 conductivity upon concentration of oxygen vacancies was examined. Since many reliable devices require oxygen-gettering metallic interlayers, it is important to establish the vacancy concentrations and configurations necessary to lead to switching.
Next, the role of the thickness of the substoichiometric oxide in determining the conductive state of the overall device was investigated. In particular, switching was examined from the perspective of the motion of oxygen vacancies between switching and conductive regions of the oxide.
Finally, the role of hydrogen in resistive switching of TiN/HfO2/TiN cells was investigated. Hydrogen is known experimentally to be an important factor in the switching of TiN/HfO2-based RRAM, but its precise role is not clear. In this work, hydrogen&’s impact on the formation of vacancies and delocalization of vacancy states was simulated, showing the connection between the presence of hydrogen and a devices ability to switch states.
Overall, the impacts of substoichiometry, oxide thickness, and hydrogen have all been observed experimentally in TiN/HfO2/TiN cells, but not understood. Using ab-initio calculations of electron localization and density of states, this investigation helps to shed light on the underlying physics at work.

Simple metal/insulator/metal (MIM) structures composed of a thin oxide layer sandwiched between an electrochemical active electrode and an inert metal electrode have a good potential for use as nonvolatile switching memories in large-scale integrated circuits. From the similarity of the operation mechanism to an atomic switch, whose resistance a nanometer gap between a mixed conductor electrode and an inert metal electrode is controlled by electrical bias [1], this MIM-structured cell is referred to a gapless-type atomic switch. We have proposed the forming and switching mechanisms in a Cu/Ta2O5/Pt atomic switch cell [2]. The forming and SET operations correspond to the formation of a metal filament between the electrodes by inhomogeneous nucleation and growth, and the RESET operation is attributed to the dissolution of the metal filament due to thermochemical reactions assisted by Joule heating. The validity of this switching model was demonstrated by the fact that the temperature variations in the operation voltages and the ON resistance of the cell could be explained in terms of classical nucleation theory [3]. Moreover, the switching behavior was found to depend on the oxide material and be affected by moisture in the ambient air, which enables us to draw a microscopic picture for the anodic dissolution as well as the migration of metal ions in the oxide layer [4].
Here, we observed quantized conductance in an Ag/Ta2O5/Pt atomic switch under the application of small constant voltages and pulse voltages [5]. The observed conductance changes are attributed to the formation and dissolution of an Ag filament with an atomic point contact of different integer multiples in the Ta2O5 layer. The conductance level could be controlled by varying the amplitude of the input voltage pulses. The results demonstrate that atomic point contacts can be realized in a MIM structure that function as a nanogap-based atomic switch [1]. By applying consecutive voltage pulses at periodic intervals of different times, we also observed an effect analogous to the long-term potentiation of biological synapses, which shows that the gapless-type atomic switch has potential for use as an essential building block of artificial neuromorphic systems.
[1] Terabe et al., Nature 433 (2005) 47, [2] Tsuruoka et al., Nanotechnology 21 (2010) 425205, [3] Tsuruoka et al., Nanotechnology 22 (2011) 254013, [4] Tsuruoka et al., Adv. Func. Mater. 12 (2012) 70, [5] Tsuruoka et al., Nanotechnology 23 (2012) 435705.

Resistive switching devices made by different types of nanowires have been investigated in recent years because of the low capacitance and the well-defined path of filaments. However, the lack of easy fabrication techniques for reproducible nanoscale gap with specific positions has limited the applications of the gap type atomic switch. Here we report a new type of the fabrication method of the nanogap between the nanowire and the electrode in nanometer scale. As conducting channels, Ag2S nanowires were prepared by the sol-gel process as diameters in the range of 40-60nm and lengths up to few micrometers, and dispersed onto the SiO2/Si substrate. The Ag electrode is deposited on one side of the nanowire. The vertical gaps were effectively made between the Au electrode and the Ag2S nanowire in a high-contact resistance type and a geometric insulating type. The resistive switching behaviors were ascribed to the formation and the rupture of metallic Ag filament across the gap, enlightening the possible applications as FPGA (Field Programmable Gate Array) devices with long Ag2S nanowires.

Quantized conductance frequently occurs in low temperature experiments; however, this effect has been also reported in air at room temperature settings. One common example uses a MEMS switch under ambient temperatures, opening a metal-to-metal micro-contact until a sub-micrometer metallic bridge is formed between the electrodes.
Crossbar structured nanodevices have also been found to exhibit quantised conductance by forming atomic point contact switches [1]
.
We reported resistive switching in metal-free silicon based devices consisting of a SiOx active layer on a pSi substrate, with ITO/poly-nSi contacts [2]. Switching is caused by formation and annihilation of nano-sized conductive pathway. Given the atomic scale of the conductive filaments, we expect the conductive pathways present in the SiOx active layer to behave as a mesoscopic system, where the absence of scattering gives rise to a ballistic transport regime with the conductance being quantized.
Apart from the abrupt transitions from HRS to LRS states we can observe transitions to intermediate states once the device is set in LRS. About one thousand abrupt conduction steps were recorded. We find that the histogram can be fitted to normal distributions with peaks positioned at half-integer multiples of the quantum conductance unit G0, which confirms the signature of ballistic transport.
If this behaviour can be well controlled, it may lead to multilevel storage for ultrahigh density memory
applications.
[1] Terabe K. et al, Quantized conductance atomic switch, Nature 433, 47-50 (2005)
[2] Mehonic, A. et al. Resistive switching in silicon suboxide films, J. Appl. Phys. 111, 074507 (2012)

Layer-by-layer (LbL) method was reported to be useful for preparing organic and/or inorganic process nanocomposite films with suitable electrical properties and layer thickness as well as various functional components on substrates with different size and shape. LbL method can be achieved by tuning the complementary interactions. And advantages of LbL method into nonvolatile memory devices, electrostatically charged organic materials possessing resistive switching properties that do not require high temperature treatments should be used, and amounts and thickness of the adsorbed material should be quantified at the nanoscale.
We have synthesized MnO nanoparticles in using a nucleophilic substitution reaction for LbL method of organic/inorganic multilayers in nonpolar solvents. We have deposited MnO nanoparticles using LbL method on patterned Pt bottom electrode and top electrodes were deposited using metal transfer process. The fabricated ReRAM structure was cessfully functions to ~ 10² on/off ratio at 0.1V. LbL method and selective deposition of metal and MnO facilitate the formation of the 3-D cross-pointed ReRAMs.

Here we will discuss the investigation of a promising new material for resistive switching, SiO2 co-sputtered with Pt. The occurrence of reversible resistance switching has been widely studied in a vast variety of material systems for applications including nonvolatile memory, logic circuits, and neuromorphic computing. However, determining the cause of switching is non-trivial, especially in a complicated system composed of dielectric medium with a considerable amount of metal inclusions. Striving for a deeper understanding of the physical mechanisms behind this resistive switching will be a focus of this discussion.

Micro-scale and nano-scale devices were fabricated and characterized. We confirmed reversible bipolar switching properties in a wide range (> 6 orders of magnitude) of device areas from 104 µm2 to 10-2 µm2. Atomic concentration of Pt was varied from 6.5% to 17.7% confirmed by Rutherford Back Scattering (RBS). Physical vapor deposition (PVD)-grown Ta and Pt were used as bottom and top electrodes, respectively. Switching speed was verified to the sub-100ps timescale with real-time monitoring of device dynamics. Highly repeatable switching was observed and the micro-scale device readily survived up to 108 cycles. Retention study is ongoing, but greater than six months at room temperature for a nano-scale device. We investigated the conducting channel using Focused Ion Beam (FIB)-Transmission Electron Microscopy (TEM) in micro- scale devices. We will present the conducting channel responsible for the switching behaviors. In addition, we will discuss our study of the correlation between the size of nano-clusters of Pt, composition, and the electrical transport properties using TEM, Small Angle X-ray Scattering (SAXS) and quasi-DC electrical measurements, which will be bridging between engineering micro-structure of materials and tailoring device properties. In this discussion we will focus on the characterization of micro- and nano-sized devices and the potential to produce scalable and reliable bipolar resistive switching devices composed of SiO2 co-sputtered with Pt.

Since the gate pitch size of NAND flash memory has been shrunk into sub-20 nm technologies, a high quality tunnel oxide (Tox) is required to improve endurance characteristics. Generally, Tox has been grown by post-oxidation processed with thermal/radical oxidation and post-annealing in NAND flash memory area. In the previously reported papers, two-step oxidation was introduced to improve the roughness of a Tox/Si interface and electrical properties of Tox [1,2]. The two-step oxidation process is performed with first-half oxidation, intermediate-annealing, and second-half oxidation in consecutive order. In this study, the two-step oxidation process on a Si (100) surface is employed to obtain a high quality Tox and Tox/Si interface with low roughness mean square. Firstly, the Tox growth on the Si surface is calculated using technology computer aided design (TCAD) simulation, thermodynamically. After the two-step oxidation process, the grown Tox is more tensile stressed than that progressed by post-oxidation due to the intermediate-annealing process, while the Si surface is stressed more compressive. To confirm the interfacial state, the samples are analyzed by high resolution transmission electron microscopy (HRTEM), resulting that the Tox/Si interface processed with the two-step oxidation process shows low RMS. Since some defects, such as native vacancy/interstitial, hydrogen, and others, located in Tox (half thickness) and Tox/Si interface after the first-half oxidation process are easily moved to the Tox surface, the number of trap sites in Tox can be diminished. In conclusion, we fabricate a high quality Tox using the two-step oxidation process for NAND flash memory devices and this method shows possibilities for enhancing endurance characteristics.
[1] A. Bhattacharyya, C. Vorst, and A. H. Carim, Solid-State Sci. Tech., 132, 1900 (1985).
[2] J. Kim and S. T. Ahn, IEEE Electron Dev. Lett., 18, 385 (1997).

Since the gate pitch size of NAND flash memory has been shrunk into sub-20 nm technology the Si process condition and time should be controled and managed delicately. Especially, the reliability characteristics such as available program/erase cycles and retention are severely influenced by manufacturing processes. The effects of dopant elimination on reliability are investigated with the delay time during the manufacturing process. Since water (H2O) molecules are adsorbed on the surface when the surface of silicon oxide (SiO2) is exposed in the air, the threshold voltage of the cells is decreased due to the boron dopant elimination as increasing the delay time after capping SiO2 in NAND process. The adsorbed H2O molecules are dissociated to hydroxyl (OH-) and hydrogen ion (H+) on the surface, and then H+ bonds to a neighboring oxygen ion (O-2) to generate another OH- without any activation energy at room temperature [1]. Since a surface of Si active area is oxidized with the diffusion of the generated hydroxyls from the SiO2 surface, boron dopants located at the surface of Si active area are migrated to the SiO2 generated with oxidation enhanced diffusion mechanism [2]. Furthermore, the diffusion of boron dopants to the SiO2 is accelated by H+ of OH-. In summary, the reliability properties of NAND chips can be degraded due to the boron dopant elimination, which is originated from the oxidation of the Si active area with long delay time during the manufacturing process.
[1] M.-H. Du, A. Kolchin, and H.-P. Cheng, J. Chem. Phys., 119, 6418 (2003).
[2] K. Taniguchi, K. Kurosawa, and M. Kashiwagi, J. Electrochem. Soc., 127, 2243 (1980).

The author discusses the market opportunities for Conductive Bridge Random Access Memory (CBRAM) and the technological and business challenges facing all emerging memory technologies. Overcoming many of these challenges, this paper highlights recent material, device and circuit advances leading to a 2nd generation CBRAM technology. Endurance, retention and reliability results are reported for the 2nd generation 130nm 1Mb E2PROM compatible CBRAM product.

Defect generation and soft breakdown are critical reliability issues in high-k gate dielectrics for CMOS application. The same phenomena, on the other hand, are key enablers for resistive switching memory (RRAM) operation, where the resistance of a conductive filament (CF) is modulated by applying voltage pulses [1]. The CF is first generated by the forming operation, namely a controlled, low-current dielectric breakdown. The CF is then activated/deactivated through set/reset processes consisting of voltage-driven ion migration [2]. Both unipolar and bipolar switching operations have been observed, with bipolar switching generally displaying the highest reliability and capability of low-current operation. The details of the switching mechanism, such as the size of the CF and the ion-migration kinetics, dictate not only the RRAM operation, but also the memory reliability and the scaling limits of this technology. Therefore, an accurate physical picture of resistive switching is essential.
This talk will cover the basic concepts of bipolar switching in high-k oxides. First, the main material requirements for high-k oxides in RRAM, as opposed to high-reliability gate dielectric, will be summarized. Then, the switching processes will be illustrated through characterization results of HfOx and simulation results of ion drift/diffusion activated by the applied field and by the local Joule heating at the CF [3]. The universal switching, namely the independence of the characteristic set/reset voltages among most high-k oxides, will be evidenced through data from the literature and modelling results [4]. Complementary switching and the capability to control both the size and the direction of the CF in the set operation will be shown. Finally, the potential scaling issues will be summarized in terms of reliability issues and switching variability [5].
[1] H.-S. P. Wong, et al., Proc. IEEE 100, 1951 (2012).
[2] H. Y. Lee, et al., IEDM Tech. Dig. 297 (2008).
[3] S. Larentis, et al., IEEE Trans. Electron Devices 59, 2468 (2012).
[4] D. Ielmini, et al., IEEE Trans. Electron Devices 58, 3246 (2011).
[5] D. Ielmini, et al., Phase Transition 84, 570 (2011).

Resistive random access memory (RRAM) has attracted much attention because of its potential for high performance, scalability and integration with current CMOS technology. One approach to ensure high density memory devices is to employ a 3-dimensional stackable crossbar structure. Due to their size and exceptional electrical properties, carbon nanotubes (CNTs) may be an appealing choice as electrodes [1,2] for high-density, low-power crossbar RRAM devices.
In this work, we fabricated RRAMs consisting of thin (~5 nm) AlOx sandwiched between a single to a few CNT crossbar electrodes to probe the fundamental scaling limits of RRAMs. Horizontally aligned CNTs were first grown by chemical vapor deposition on ST-cut quartz [3], and then transferred onto SiO2/Si substrates [4]. A second layer of aligned CNTs was transferred perpendicular to the first CNT layer after AlOx deposition by atomic layer deposition.

Remarkably low programming currents (10-100 nA), high ON/OFF ratios (up to 1e5), and reasonable set/reset voltages (4-10 V) are demonstrated. In addition, both metallic and semiconducting CNTs are shown to effectively switch AlOx. The high-resistance state of these memory devices (~100 GOmega;) is independent of CNT electrode resistance and is determined by the OFF-state resistance of AlOx. The low-resistance state scales linearly with the highest resistance CNT electrode until it becomes comparable to the ON-state resistance of AlOx. When the CNT electrode resistance is sufficiently low, these RRAMs suffer from premature breakdown. The CNT resistance can serve as a built-in series resistance that imposes a current compliance helping to prevent permanent breakdown of the AlOx layer.
[1] F. Xiong et al., Science 332, 568 (2011).
[2] Y. Wu et al., IEEE Symp. VLSI Tech. (2011).
[3] S.J. Kang et al., Nat. Nano. 2, 230 (2007).
[4] C.-L. Tsai et al., Appl. Phys. Lett. 99, 053120 (2010).

The use of the nanocrystals embedded high-k dielectric structure in nonvolatile memory devices has the advantages of low leakage current and high reliability [1]. Replacing SiO2 gate dielectric in the nano-size MOSFET with the ZrHfO high-k material can improve bulk and interface properties, such as lowering the EOT, increasing the crystallization temperature, lowering the interface state density, and increasing the effective k value [2]. Light exposure can affect the performance of the nanocrystals embedded high-k dielectric structure, which is critical to applications in commercial products. However, there are few studies on this topic until recently [2,3]. In this paper, the nc-MoOx embedded ZrHfO MOS capacitors were prepared on the p-type Si wafer using the one pump down process followed by the 800omicron;C post deposition annealing process. The ITO material was used as gate electrode because of its relative high band gap, high electric conductivity and high transparency in the visible region of the spectrum [3]. The nonvolatile memory characteristics were investigated using the C-V and J-V hysteresis curves. The fresh C-V curve of nc-MoOx embedded sample changed under light conditions while that of control sample, i.e., ZrHfO without the embedded MoOx, showed negligible change. When the gate voltage was swept from -7 V to +7 V to -7 V, a large flat band voltage of 0.607 V was obtained while a small value of 0.083 V was obtained in the control sample. The flat band voltage slightly increased under the light condition, and the C-V curves shifted to the positive gate voltage direction. The capacitor under green LED light exposure trapped slightly less holes than that under the red light exposure. The J-V curve showed significantly increase under the light exposure condition compared to that in the dark in the positive voltage range. A peak was observed in the J-V curve of the nc-MoOx embedded sample in dark due to the Coulomb blockade effect [4]. The sample under light exposure conditions did not show this phenomenon. The control sample did not show Coulomb blockade either. The leakage current under the green light exposure was lower than that under the red light exposure. A detailed study on the charge storage characteristics under the influence of exposure light wavelength will be included in this paper.
1. S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Cabbe and K. Chan, Appl. Phys. Lett., 68, 1377 (1996).
2. Y. Kuo, X. Liu, C. H. Yang, and C. C. Lin, Mater. Res. Soc. Symp. Proc. 1430, E01 (2012).
3. B. Q. Luo, C. C. Lin, and Y. Kuo, ECS Trans., 41, 93 (2011).
4. X. Liu, C. H. Yang, Y. Kuo, and T. Yuan, Electrochem. Solid-State Lett., 15, H1 (2012).

Resistance switching (RS) in metal/oxide/metal stack structures is a key phenomenon of resistive random access memory (ReRAM). The formation and rupture of conductive filaments have been widely accepted as an origin of RS mechanism in binary transition metal oxides [1]. “Forming” exhibits some analogy with soft breakdown of SiO_2 in Si MOS structures. In this study, Weibull distributions (Weibits) of forming characteristics under both constant voltage stress (CVS) and ramped voltage stress (RVS) in Pt/NiO/Pt stack structures have been investigated.
NiO films were deposited on Pt/Ti/SiO_2/Si substrates by a reactive RF sputtering method. The proportion of O_2 flow rate in the Ar + O_2 gas mixture was 5%. The thickness of NiO films was less than 100 nm. Pt top electrodes (TEs) with thickness of 50 nm were deposited by electron beam evaporation. All of the samples exhibited unipolar RS characteristics. In RVS measurements, the sweep rate R was from 0.1 to 1 V/s.
All the Weibits of time to forming (t_form) under CVS normalized by the TE-area scaling law in samples with different TE diameters (50 um to 500 um) fell in the same line. This result indicates that the formation of conductive filaments at forming follows a weakest link theory, and that weakest spots are randomly distributed in a NiO film according to the Poisson statistics.
In analogy with SiO2 thin films, we assume that the average number of defects responsible for forming (N_form) follows a simple power law of time [2]: N_form=(t/tau;)^α, tau;=tau;_0xV^(-n), where α is independent of V. In RVS experiments, tau; depends on time because of V=Rt. By comparing t_form under CVS to voltage to forming (V_form) under RVS in each sample, the exponent n is fitted to be about 10 in the samples with NiO thickness of at least 20 nm to 50 nm. Furthermore, the Weibull slope of t_form (about 1.5) and that of V_form (about 14) were essentially independent of voltage and the NiO thickness, indicating the origin of defects may be identical.
The total injected charge density before forming (Q_form) in samples was also investigated. The Weibull slope of Q_form under RVS was different from that under CVS, which suggests that forming is a voltage driven process instead of total injected charge density. The Weibull slope of Q_form was independent of NiO thickness. This result means the mechanism of forming is different from that of breakdown in SiO_2 thin films, where the Weibull slope of critical charge density (Q_BD) decreases with decreasing the oxide thickness.
In our hypothesis, a “percolating layer” in which a conductive path percolates by applying voltage stress may exist in NiO films. The thickness of the layer is much smaller than (independent of) NiO thickness. Forming may occur when a conductive path forms throughout the layer according to the percolation model.
[1] H. Akinaga et.al., Proceedings of the IEEE 98, 2237 (2010). [2] E. Y. Wu et.al., Microelectron. Reliab. 45, 1809 (2005).

The demand for high density, low power and high speed performance has been increasing. For the demand, a dynamic random-access memory (DRAM), which consists of one transistor and one capacitor, requires a high stack capacitor or a deep-trench capacitor to satisfy a storage capacitance (around 25fF/cell) in smaller cells. In a 30-nm DRAM, it is difficult to discriminate between the ‘0&’ and ‘1&’ logic states due to severe charge leakage of the capacitor caused by the high inner electric field. Moreover, if the height of the capacitors is too high, they can lean each other. If a capacitor can be replaced to a resistor or eliminated from the DRAM cell structure, scaling down issue can be overcome easily. The capacitor-less using the floating body effect on a silicon-on-insulator (SOI) wafer consists of one transistor structure operated with a charge storage in the silicon body without a storage capacitor. In capacitor-less memory, two states of ‘0&’ and &’1&’ are discriminated using the threshold voltage (VT) difference induced by the kink effect on the SOI. We investigated the effect of the SiGe layer and mobility enhancement on the memory margin of a capacitor-less memory cell. The hole confinement well can be used to insert the SiGe layer. Moreover, mobility is increased by strain in the Si channel. The memory margin of a strained Si SGOI capacitor-less memory cell was 138.6 µA, or 3.3 times greater, at a Ge concentration of 32 at%. Two key phenomena contributing to a higher memory margin were studied. One is the effect of hole confinement, which is well achieved by inserting the SiGe layer. The other is increased mobility resulting from strain in the channel. These two effects enhance the memory margin by factors of 1.85 and 1.74, respectively, compared to that of the SOI cell at a 32 at% Ge concentration. Two factors were split into strain and hole barrier effect through the simulation work with a device simulator ATLAS from Silvaco International Corporation. These simulation results show that the two factors of the strained Si SGOI capacitor-less memory cell improve the memory margin with Ge concentration. We demonstrate the possibility of an extremely long retention time which results from the innovative structure of a capacitor-less memory cell as the strained Si grown on SiGe-on-insulator (SGOI). * This work was financially supported by the grant from the “Next-generation substrate technology for high performance semiconductor devices (No. KI002083)“ of the Ministry of Knowledge Economy (MKE) of Korea and the Brain Korea 21 Project in 2012.

Metal oxide based Resistive Random Access Memories have recently gained significant attention as a potential candidate for future non-volatile memory technology due to their simple structure, ease of 3D integration, very high switching speed and CMOS compatibility[1,2]. However, most RRAM devices need a separate forming process for device initialization. Previous efforts to make forming free devices in HfO2 based systems include use of ultrathin HfO2 layer[3] or use of HfO2/TiO2 multilayer structures[4]. In this work 100 µm x 100 µm forming free devices were fabricated using 5 nm mixed HfTiOx with 25% Ti doping as the dielectric. Devices with mixed HfTiOx dielectric show forming free switching with set/reset voltages approximately +1/-1 V. The control sample with 5 nm pure HfO2 require a separate forming step with a forming voltage of ~ 2V. Generally an external or on-chip transistor is necessary to control the current during a forming process to avoid device damage[5]. In this case, the control devices with pure HfO2 were formed with an external transistor while no transistor is required for switching the forming free devices. DC endurance cycling for 100 cycles both with and without transistor shows comparable performance in the forming free devices. The HfTiOx devices also exhibit multi-level switching with at least four distinct levels. Multi-level switching can be achieved both in 1T-1R and 1R configurations. The best resolution for four - level switching under dc cycling endurance can be obtained with 100 µA, 400 µA and 700 µA compliances. The maximum current level used here is more than 10 times smaller than the previous report in Cu doped HfO2 for similar dc cycling endurance (20 cycles for each level)[6]. The HfTiOx devices also show 10 year data retention for each level. The devices also exhibit incremental resistance change with the application of appropriate +ve/-ve pulses. This can be useful for neuromorphic circuit applications. Investigation of switching mechanism for the forming free devices by TOF-SIMS and conductive AFM will also be presented.
REFERENCES:
1. A. Chen et al., IEDM Tech. Dig., 2005, pp. 746-749.
2. H. Y. Lee et al., IEEE Electron Device Lett., vol. 31, no.1, pp. 44-46, 2010.
3. Y. S. Chen et al., IEEE Electron Device Lett., vol. 31, no.12, pp. 1473-1475, 2010.
4. X. Wu et al., Appl. Phys. Lett., vol. 99, p. 133504, 2011.
5. B. Butcher et al., IEEE IIRW, 2011.
6. Y. Wang et al., Nanotechnology, vol. 21, p. 045202, 2010.

Research on the electronic properties of disordered materials dates back to the original work of Ovshinsky in the 1950s. From 1958 to 1961, he investigated the chemical and the electrical properties of amorphous semiconductors, discovering the existence of reversible switching effects. The first one is related to the reversible switching mechanism between an electrical low conductive state and a high conductive one, without any change in the microscopic structure of the material. Since this mechanism requires a threshold voltage and is usually associated with an SNDCs, it has been named threshold switching (also called Ovonic threshold switching OTS). A second mechanism was also discovered in some chalcogenide compounds, this one related to a thermally activated phase transition of the chalcogenide alloy that can be switched between a high conductive polycrystalline state and a low conductive amorphous one, through proper electrical pulses that cause a Joule heating of the material. Since both the crystalline and the amorphous state are stable, the two phases could be used to store binary information in a nonvolatile memory device, the bit “1” corresponding to the conductive state and the bit “0” to the insulating one. This electrically induced structural change has been thus named Ovonic memory switching (OMS). It is worth noting that the OTS effect is required to get the OMS mechanism but not vice versa. In fact, an amorphous chalcogenide has to be driven in a highly conductive electrical state through OTS to get the transition temperatures without enormous electrical fields. Despite this fundamental role of the OTS effect and the theoretical efforts spent in the past 50 years to explain this crucial phenomenon, the nature of the physical principle responsible for the conductance switching is still controversial.
In this tutorial the main ingredients of the chalcogenide physics are reviewed and analyzed through simplified analytical models, providing a deeper insight on the origin of the threshold switching mechanism in chalcogenide glasses. The electrical properties of phase-change materials, including low-field conductivity, transient behaviors, and resistance drift, will be reviewed and the various models so far proposed will be compared, highlighting their strengths and weaknesses. Finally, some experimental evidences will be reviewed as a possible path to discriminate among the several threshold switching theories.

Carbon Nanotube (CNT) films exhibit electrically switchable resistance change behavior. This resistance change behavior shows a combination of specific properties that makes it suitable for semiconductor memories and has been optimized to uniformity levels that makes CNT-based memory, NRAM, attractive for next generation memories. Specific properties that make NRAM a candidate for semiconductor memory products are CMOS-compatible voltages and low write currents, high endurance, good electrical device uniformity and excellent data retention and read/write disturb immunity combined with a simple fabrication process.
In contrast to widely pursued bottom-up self-assembly approaches for CNTs, NRAM technology uses a top-down integration approach which allows large-scale integration of CNTs using existing fab tool infrastructure and circumvents yield related issues due to incorrectly placed CNTs or low density of CNT devices typical for bottom-up approaches. Using this top-down integration approach of lithographically patterning a spin coated, dense, wafer-scale uniform CNT film sandwiched between upper and lower metal electrodes, high yielding (>99.999%) multi-Mbit NRAM product chips have been fabricated in a standard CMOS fully integrated with decoding logic and an SRAM interface.
A multitude of chemical engineering issues as well as fab process integration and circuit issues had to be optimized to fabricate NRAM samples showing a combination of fast, low current, high endurance cycling behavior as well as data retention and write/read disturb immunity at levels sufficient for commercial products. In this talk we will review specifically the interplay between ultra-high purity CNT material properties and fab process integration issues as well as electrical NRAM device properties. Latest device and CNT materials advances will be discussed as well as specific semiconductor memory applications for this NRAM technology.

Next generation CMOS requires high activation and hyper-abrupt junction formation for low sheet resistance. The primary method of doping, ion implantation, provides excellent spatial control of dose, however a high temperature anneal (>1000 C) is required to remove defects introduced from ion implantation and to electrically activate the implanted specie. A “diffusionless anneal” by which dopant is activated without significantly diffusing, would be ideal for ultra-shallow junction (USJ) formation. This work investigates one such technique, laser annealing, which uses a scanning laser to locally heat the wafer surface. We investigate the laser system via simulation to determine the peak temperature achieved in the active area during processing. We employed the Sentaurus TCAD software by Synopsys to perform a 2D simulation of a laser scanning across the active area of the device, solving the heat equation in both time and space. An absorber layer is deposited on the wafer surface to encourage the absorption of optical power and consequent heating of the wafer surface. An effective absorption coefficient of α=8000cm-1 was calculated for the absorber layer, calibrated with the experimental laser intensity. This absorption coefficient correctly predicts the silicon temperature as a function of power with any arbitrarily defined scan speed. To investigate the role of dopant activation, an SOI wafer was implanted at 25 keV, dose 3e15 /1.5e15 cm-2 and laser annealed in stripes of target temperatures ranging from 1100-1300 C. The sheet resistance was measured on wafer showing Rs improvement with increasing laser temperature. The extracted temperature cycle from the 2D heat simulation was used as an equivalent millisecond RTA in a full 3D finFET process simulation to study dopant distribution and activation using Sentaurus Process Kinetic Monte Carlo (KMC), considering the effect of dopant clusters and point defects. The results of this simulation, show that there is no further activation of arsenic with increasing laser temperature (~ 25%) which suggests healing of the implant crystal damage may be reducing sheet resistance.

Resistive switching in a metal-free silicon-based material offers a compelling alternative to
existing metal oxide-based resistive RAM (ReRAM) devices, both in terms of ease of
fabrication and of enhanced device performance. We report a study of resistive switching in
devices consisting of non-stoichiometric silicon-rich silicon dioxide thin films. Our devices
exhibit multi-level switching and analogue modulation of resistance as well as standard
two-level switching.
We demonstrate different operational modes that make it possible to dynamically adjust
device properties, in particular two highly desirable properties: nonlinearity and
self-rectification. This can potentially enable high levels of device integration in passive
crossbar arrays without causing the problem of leakage currents in common line semi-selected
devices.
Aspects of conduction and switching mechanisms are discussed, and scanning tunnelling
microscopy (STM) measurements provide a more detailed insight into both the location and
the dimensions of the conductive filaments.

Metal gates are replacing polycrystalline silicon gates in CMOS applications to enable integration with high-k dielectrics and further scaling of devices. However, work function (WF) variation due to grain orientation has become a significant problem as the gate dimensions scale and become comparable to the grain size. Amorphous metal gates have the potential to eliminate WF variability due to their lack of grains, and have drawn attention in the past few years. For future MOSFETs, the following properties are required for the metal gate: thermal stability, suitable WF, low resistance, compatibility with high-k dielectrics, and conformal deposition.
In this study, we investigated binary amorphous metal gate systems since the simple structures make them promising candidates for conformal deposition systems such as ALD. Metals and metal alloys tend to crystallize due to their simple crystal structures. However, certain binary metal systems can form a metastable amorphous structure, although most do not meet all the requirements listed above. In our study TaNi was selected as the candidate because of it provides a potential tunable work function range from 4.3eV (WF of Ta) to 5.1eV (WF of Ni). Crystal structure, thermal stability, and electrical properties of various compositions (Ta, Ta25Ni75, Ta50Ni50, Ta75Ni25, and Ni) were investigated. All the metal gates were deposited by DC sputtering onto SiO2 substrates for film characterization and onto SiO2/HfO2 substrates for WF extraction using C-V. As determined by grazing XRD, all alloys are amorphous as-deposited and are stable after annealing at at least 400°C for 30 mins, which makes them suitable for gate-last application. In addition, Ta/Ni multi layers with thickness of 1.2nm were sputtered and are amorphous as-deposited due to mixing during deposition, lending them to ALD processes. The resistivity of all the amorphous films are around 200mu;Omega;*cm.
While one might expect the WF to vary linearly with composition to first order, for the TaNi alloys in this study the WF is pinned at the Ta WF value until pure Ni. XPS depth profiles reveal that the Ta atoms seem to segregate to the metal/HfO2 interface to some degree, perhaps due to the higher Ta-O bond enthalpy compared to Ni-O, thus resulting in the WF/composition behavior. These properties enable us to have a thermally stable amorphous metal with the WF of one component (Ta), which provides flexibility in fabrication and the ability to optimize other properties (stability of amorphous phase, resistivity, etc.) while maintaining the WF. In addition, due to the absence of grain boundaries, amorphous TaNi can act as a good diffusion barrier for other metals, which makes it more attractive for use in gate stacks since this reduces the need for an additional diffusion barrier layers for the metal fill. Based on the above characteristics, amorphous TaNi has great potential for use in advanced CMOS gate structures.

Transition metal oxide ReRAM has been identified as one of the most promising candidates for next generation non-volatile memories. One of the key challenges in modeling ReRAM operations is the prediction of their conduction behavior, which has been shown previously to be very sensitive to the atomic profile of oxygen vacancies. The conduction mechanism was found to vary from metallic in the “ON” state, to quantum tunneling and hopping in the “OFF” state. Since resistive switching is a gradual transition between the two states, quantitative prediction of I-V characteristics through an arbitrary vacancy configuration is desirable. In the present study, we systematically calculated the electron transport properties of pristine and defective TiO2, by introducing isolated oxygen vacancies and oxygen vacancy chains in a prototypical TiN/TiO2/TiN device structure. The relaxed atomic configurations were obtained from ab-initio density functional theory (DFT) calculations, and the transport characteristics were calculated by the DFT-based non-equilibrium Green&’s function (NEGF) approach. The formation of filaments by clustered oxygen vacancies were linked to the experimentally observed large conductivity increase, and the I-V characteristics of both “ON” and “OFF” states can be reproduced well. It was also found that oxygen atom diffusion into to the vacancy sites, which reduces the conductivity, is strongly affected by the interface with metal electrodes. Based on the results of transport calculations, a 3D analytical model was constructed and parameterized to allow the detailed prediction and discussion of device characteristics.

High dielectric constant (k) oxides are important elements of devices such as MOSFETs, DRAMs, and non-volatile memories and will continue to be used for new technology nodes. Electrical measurements on metal-insulator-metal (MIM) capacitors with different types of high k oxides were used to develop a model for defect generation that explains the electrical leakage as well as reliability of a wide range of high k oxides. The breakdown fields (Ebd) of thin films (5-10nm) of different binary and ternary oxides decreased with increasing k over a wide range of k values (9-80). The values were accurately described by the function Ebd=A*k-0.5 similar to that predicted from Macpherson&’s Thermochemical model [1].
The dependence of the breakdown field on temperature was also determined. The increase in leakage currents as a function of time for different combinations of constant-voltage-stress/temperature were measured on a few samples with different k. By modeling the I-V curves at different points of the stress cycle, it was shown that the increased leakage current was caused by creation of additional oxygen Frenkel defects by the electrical stress. The rate of defect formation for a given applied field increased with k, indicating that high “local” fields at the lattice position (which are enhanced at high k) were responsible for lowering the energy barrier for defect creation. The model of electrical field induced defect generation explains the breakdown of high k dielectrics and in particular the dependence on k. Films under different stress conditions (voltage, temperature, time) were annealed at different temperatures and times.
The reduction of leakage current as a function of time for different annealing temperatures was measured and in all cases followed a fractional power law with respect to time. This allowed the determination of the spatial separation of Oxygen Interstitials and Vacancies after electrical stress and an estimation of the diffusion rate of the defects. Defects created by electrical stress at room temperature recombined within a few seconds for anneal temperatures around 90C. This indicates that electric fields at low temperatures create defects within a lattice distance. In contrast, if the samples were stressed at temperatures >90C but annealed at temperatures lower than the stress temperature, a large fraction of the defects remained active even after several hours. This could be explained by the larger separation of field-induced Interstitials and Vacancies due to diffusion of these defects at higher temperatures.
1. J. McPherson, J. Kim, A. Shanware, H. Mogul and J. Rodriguez, IEEE Transactions on Electron Devices, 50 (8), pp 1771 - 1778 (2003).

In recent years, nanoscale atomic switches [1], which are constructed based on the metal-insulator-metal structure, have attracted much attention due to its high scalability, low power consumption and potential application in memory cell. The most accepted switching mechanism is the formation/annihilation of metal atomic bridges in the electrolyte between two electrodes. However, the atomistic details of the mechanism of the atomic switches are still not well understood.
In the present study, we have examined the conduction mechanism in Cu/Ta₂O₅/Pt atomic switch from first principles. For the Ta₂O₅, both crystalline (c-Ta₂O₅) and amorphous (a-Ta₂O₅) phases are considered. We have found that the alternant Cu-Ta bonding plays a crucial role in the formation of conductive path in Ta₂O₅ in the crystalline case [2], but not in the amorphous one. In the amorphous case, we have found that Cu single atomic chains are unstable. On the other hand, Cu nanowires with widths larger than the single atom are stable during the molecular dynamics simulation at 500 K for 15 ps, and can form conductive paths. In this case, the Cu-Cu bonding mainly contributes to the conductive, delocalized defect state. Subsequent analyses of transmission spectra performed using nonequilibrium Green&’s function method further confirm the formation of conductive path in the Cu/a-Ta₂O₅/Pt atomic switch.
[1] Tsuruoka, T.; Terabe, K.; Hasegawa, T.; Valov, L.; Waser, R.; Aono, M. Adv. Funct. Mater. 2012, 22, 70.
[2] Gu, T. K.; Tada, T.; Watanabe, S. ACS Nano. 2010, 4, 6477.

We present here experimental results and analysis of the interface states and defect density for AlGaN / GaN heterostructures with AlN, Al2O3 and SiN insulators. The conventional AlGaN / GaN Schottky-gate high electron mobility transistor suffers from problems such as high gate leakage and current collapse. Transistor structures with insulated gates have been developed to suppress gate leakage and passivate surface states. Insulator materials such as SiO2, Si3N4, Al2O3, HfO2 and AlN have been reported as the gate dielectric and passivation layers. The ideal candidate material should have high bandgap (Eg > 5eV), high dielectric constant comparable to AlGaN (k ~ 9.5), high breakdown field (E > 10 MV / cm) and high thermal conductivity. The dielectric material also has to form a good interface with AlGaN since good gate control of the transistor depends on the dielectric / AlGaN interfacial properties. We have studied and characterized the dielectric / AlGaN interface to better understand the relative importance of these issues.
In this work we characterized the interface of three dielectric materials deposited on AlGaN/GaN heterostructures: Al2O3, AlN, and SiN. The Al2O3 and AlN layers were deposited by atomic layer deposition (ALD). Trimethylaluminum (TMA) and water vapor were used as the Al and O sources for the Al2O3 films. TMA and NH3 were used as Al and N sources for AlN. SiN deposition was performed by plasma-enhanced chemical vapor deposition (PECVD) using the SiH4 and NH3 reaction. Metal / dielectric / AlGaN / GaN MIS diodes were fabricated. Ti / Al / Ni / Au (20 / 50 / 20 / 100 nm) stacks were evaporated and annealed at 800 °C for 20 s to form ohmic contacts. Ni / Au was used as gate contact on the dielectric layer. AlGaN / GaN Schottky diodes were also fabricated for comparison. Electrical characterization, including current-voltage (I-V) measurements, shows that the MIS structure has superior suppression of gate leakage current. Capacitance-voltage characterization of the dielectric / AlGaN and AlGaN / GaN interfaces are also reported with three stages of the voltage sweeping range. The 2DEG is first depleted below the threshold voltage, and then forms at the AlGaN / GaN interface above the threshold voltage. At a high positive gate voltage, electrons at AlGaN / GaN interface partially transfer to dielectric / AlGaN interface. Multiple frequency C-V was used to investigate interface states at both the dielectric / AlGaN and AlGaN / GaN interfaces. Our conclusion is that ALD-grown Al2O3 / AlN forms superior interfaces with AlGaN compared to PECVD SiN / AlGaN interfaces.

Amorphous TiO2 films were grown at low temperatures (le;300oC) on the various electrodes by pulsed laser deposition using a TiO2 ceramics target and the effects of electrodes on the resistive switching properties have been investigated. Unipolar switching behavior was observed in the Pt/TiO2/Pt device but bipolar switching behavior was observed in the Pt/TiO2/TiN device. Linear fitted current density- applied field results show that LRS and HRS conductions in unipolar switching are dominated by Ohmic behavior and Schottky effect, respectively. Forming process was required for the unipolar switching behavior of the Pt/TiO2/Pt device and the conducting filaments were considered to be formed during the forming process. However, for the Pt/TiO2/TiN device, which shows the bipolar switching behavior, the conduction mechanism of LRS and HRS was explained by Ohmic behavior and the space charge limited current mechanism, respectively. In addition, the effects of the current compliance and voltage control on their resistive properties were also investigated in this work.

The narrow gap Mott insulators GaM4X8 (M=V,Nb,Ta ; X= S,Se) exhibit very interesting electronic properties when pressurized or chemically doped [1]. We have recently discovered that the application of short electrical pulses on these compounds induces a new phenomenon of volatile or nonvolatile resistive switching [2]. The volatile transition appears above threshold electric fields of a few kV/cm, while for higher electric fields, the resistive switching becomes non-volatile. The application of successive very short electric pulses enables to go back and forth between the high and low resistance states. All our results indicate that the resistive switching discovered in the AM4X8 compounds does not match with any previously described mechanisms [3]. Conversely, our recent work shows that the volatile resistive switching is related to a purely electronic mechanism [4] which suggests that the AM4X8 compounds belongs to a new class of Mott-memories for which joule heating is not involved [3]. Finally, it is possible to deposit a thin layer of GaV4S8 and to retrieve the reversible resistive switching on a metal-insulator-metal (MIM) device which proves the potential of this new class of Mott-memories for applications [5].
[1] M M Abd-Elmeguid et al., PRL 93 026401 (2004). E. Dorolti, et al., JACS 132, 5704 (2010)
[2] C. Vaju et al., Adv. Mat. 20, 2760 (2008). ] L. Cario et al., Adv. Mat. 22, 5193 (2010).
[3] R. Waser and M. Aono, Nature Mat. 6, 833 (2007); Emerging Research Devices (2011) - http://www.itrs.net/
[4] V. Guiot et al. under revision for Nat. Commun. (2012); ITRS
[5] E. Souchier et al., PSS-RRL 5, 53 (2011) ; E. Souchier et al., Thin Solid Films, accepted (2012) ; J. Tranchant et al Thin Solid Films, accepted (2012).

High-resolution Z-contrast scanning transmission electron microscopy (STEM) images show that the 100% spin polarized MnMn/O interface termination is the dominant interface structure in CoFe/MgO/Co₂Mn_1.29Si (CMS) magnetic tunnel junctions (MTJ) [1]. The Z-contrast is complicated by interface strain, but the measured distance from the STEM images between the interface plane and the MgO plane is consistent with the value calculated by Hüslen et al. [2] and inconsistent with other terminations. Steps in the MgO barrier induce switching of the interface termination to CoCo/O in some areas. Simulations show that Heusler alloys like CMS have 100% spin polarized conduction electrons [3], but only the metastable MnMn/O interface termination gives 100% spin polarization across the CMS/MgO interface [2]. The metastable MnMn/O termination may be created by nonequilibrium sputter deposition with co-sputtered Mn for the CMS electrode [1]. The preponderance of MnMn/O termination and lack of MnSi/O or other interface terminations in this MTJ may be related to the excess Mn concentration. The mixed interface terminations may also explain the high TMR and its strong temperature dependence in these CoFe/MgO/CMS MTJs [1].
[1] H. Liu, Y. Honda, K.-I. Matsuda, M. Arita, T. Uemura, and M. Yamamoto, Jpn. J. Appl. Phys., 51, 093003, (2012)
[2] B. Hülsen, M. Scheffler, and P. Kratzer, Phys. Rev. Lett. 103, 046802 (2009).
[3] V. Irkhin and M. Katsnel'son, Physics-Uspekhi, 37, 659-676 (1994).

Ferroelectric materials including Led Zirconate Titanate (PZT) have two distinct polarization states which can be switched by applying corresponding electrical field (coercive field). This feature can be used for verity of practical applications including energy independent (nonvolatile) memory chips (FERAM). This type of memory stores information as state of polarization in ferroelectric capacitor which ensures energy independent storage of information. Readout of information stored in FERAM is usually accomplishing by switching this polarization state and detecting released in the process electrical charge. This type of readout obviously destroys stored information, so regeneration cycle must be added in readout procedure. Different physical properties of ferroelectric material can be used for detecting polarization state without switching of polarization, i.e. for nondestructive readout of information stored in FERAM. In particular, nonlinearity of reversible part of polarization at low bias (less than coercive field) can be potentially used for nondestructive readout. Special technique based on electrical pulses was used in this investigation to separate different components of the polarization (including switching, reversible, and generated by space charge distribution). It was found that reversible part of polarization is significant in PZT films (up to 30% of remnant polarization) which can be used for nondestructive readout in FERAM. Investigation of this type of nondestructive readout using pulse based techniques showed that amplitude of readout field can be as high as coercive field without destruction of polarization state at least for 10^6 readout cycles. Possible advantages and disadvantages of this type of readout also discussed as well as connection with particular properties of ferroelectric material used as a storage media.

Uniform monolayer of alkanethiol-protected gold nanoparticles array with utra-high density have been utilized as microcontact printable charging trapping layer for the application in flash memory. Large-area closely packed 2D Au NPs array has been formed on the concave surface of deionized water after complete evaporation of binary solvent mixture. The floating monolayer was first transferred intact to the poly(dimethysiloxane) (PDMS) stamp pad by the Langmuir-Schaefer method and then to a flexible PET substrate by conformal contact of the stamp pad and substrate. Compared with two reference devices based on Au NPs charge trapping layer created by thermal evaporation and electrostatic layer-by-layer self-assembly method, largest memory window (16.5 V) was obtained by using this technique due to the enhanced trapping site and almost no laterally leakage. In addition, the memory device showed long retention time (> 10^5 s) and good endurance property (> 1000 cycles). These results suggest that this printable Au NPs monolayer through microcontact print technique has great potential for scaling down the current state-of-art flash memory devices. Furthermore, the key device elements (Au NPs monolayer and Al2O3), are fabricated via low temperature processes, which can be readily adopted for flexible memory devices.

Resistive switching, i.e. the reversible modulation of electronic conductivity, is of interest for prospective memory devices that could be a perfect electronic memory. Among different types of RRAM (Resistive Random Access Memory), the organic-based RRAM is an object of special interest due to ability to produce high performance devices using relatively simple technology.
We report on demonstration of a rewritable memory device structure based on polymer films doped with metal particles. This structure demonstrates the on/off ratio of resistances of non-volatile states up to 10⁶ with the switching time on the order of several ns.
We present two types of devices: a sandwich structure metal/polymer blend/metal, which could be used for crossbar arrays, and a coplanar structure with two parallel contacts usable for cheap and simple memory devices. A number of different metals: Cu or Al sheets, ITO on glass, silver paste, were used as electrodes. Organic films were spin coated from a solution or prepared by lamination. Two different polymers polystyrene (PS) and polyvinyl chloride (PVC) were used as a base component of the polymer blend, both undoped and doped with different concentration of metal particles. Zinc, aluminum and silver particles with a characteristic size from 1 to 5mu;m were used as a dopant. The thickness of the polymer blend layer varied from 1mu;m to 50mu;m. The minimal electrode area was on the order of 100 mu;m².
Resistive switching was observed even for undoped polymer layers with thickness below 20 mu;m. Switching voltages and maximum device dimensions could be controlled by changing the concentration of metal particles. The optimal device behavior for the practical electronic application was observed near the percolation limit.
A bistable operating mode was achievable with the ratio of nonvolatile on/off resistances varying from 2 to 10⁶ for devices of different thickness and prepared using different materials. Minimal obtainable switching voltages are on order of few volts, with the device with switching voltages below 3V at the best. For some of the devices, a good stability of states for more than 10⁶ switching cycles was observed.
The most possible explanation of the effect observed is a filament formation. The filaments could be possibly originating from metal particles used as a dopant and metal particles injected into an organic film from metallic contacts during the initial device electroforming. However, states not only with different resistances, but also with different capacitances were observed. This effect cannot be explained only in terms of the filament formation. It is necessary to consider additional charge trapping mechanisms that may affect the device properties.

Clarification of memory characteristics of tiny cell is important for practical use of resistive random access memory (ReRAM). However, limitation of semiconductor micro-fabrication technology hinders to obtain memory characteristics caused by one and only filament confined in tiny cell with area of smaller than 20 x 20 nm².
In this paper, we established a method to prepare a very small memory cell by fabricating ReRAM structure on the tip of a cantilever of atomic force microscope (AFM). We also established a method to operate the small cell at a reset current low enough to avoid serious damage to the cantilever due to Joule heat generated by high current density at the tip of the cantilever.
A Pt film with thickness of 50 nm was deposited on a cantilever with the tip radius of 50 nm (SII SI-DF3-R(100)) as a top electrode (TEL), followed by deposition of a NiO film with thickness of 20 nm as a memory layer. Pt/NiO/Pt structure was formed by contacting Pt line, which was formed on a SiO₂/Si substrate as a bottom electrode, with the Pt/NiO structure located on the tip of the cantilever.
Current-voltage (I-V) characteristics of the Pt/NiO/Pt structure that was formed between the cantilever and the Pt-BEL was measured for BEL with area and thickness of 14×14 mm² and 100 nm, respectively. In this structure, reset current was more than 10 mA even when compliance current, I_comp, was set to 100 µA. Secondary electron image after the reset showed that the tip of the cantilever was melted due to high current density. Kinoshita et al. reported that I_reset-I_comp characteristics approached asymptotically to I_reset = I_comp as parasitic capacitance between a sandwiched structure of Pt/NiO/Pt and a current limiter, Cp, is reduced, even for low I_comp of smaller than 100 µA [1]. We made the width of the BEL narrow and thin, and Pt line with small capacitance of 3 pF and large resistance of 100 kOmega; was obtained. Reset current decreased to approximately 100 µA by limiting the set current using the Pt line, which played a part of a current limiter with small Cp. In this case, no morphological change of the tip of the cantilever was observed between before and after the reset processes.
Electric field distribution in the Pt/NiO/Pt structure that was formed between the cantilever and the Pt-BEL was calculated based on finite element method. Effective area of the memory cell was estimated to be 20 nm when radius of Pt-coated cantilever and thickness of the NiO layer were 15 nm and 10 nm, respectively. The proposed method enables not only preparation and operation of tiny ReRAM structure but also unique experiments by making the most of the structure having removable BEL.
[1] K. Kinoshita et al., Appl. Phys. Lett. 93, 033506 (2008).

Based on the strongly increasing demand for memory capacity a lot of effort from industrial as well as academic side is spent on the exploration and the development of novel memory concepts. Until now several different classes of devices such as transistors, capacitors and resistors, comprising inorganic as well as organic materials, have been investigated, and demonstrated their general suitability for non-volatile memory elements and integration into memory element networks.
Resistive memory elements have turned out to be a promising class of devices due to their relatively simple architecture and their minimal device feature size (4F²).
So far several different mechanisms causing the resistive change have been identified, ranging from phase changes and redox reactions to diffusion of particles through the active layer. Resistive bistable device characteristics have been demonstrated for inorganic active layer materials as well as for different systems based on organic semiconductors (OSCs). So far, single organic layers sandwiched between two electrodes, polymer - nanoparticle blend systems, trilayer (OSC/metal/OSC) as well as organic donor-acceptor systems have been extensively investigated. Due to the fact that OSCs are highly suitable for novel solution based production techniques like R2R printing or inkjet printing, they might be ideal candidates for low-cost large-area applications.
In this contribution we present a detailed study of the influence of inkjet printing based production techniques onto the electrical characteristics of printed bistable organic resistive devices. In particular we will demonstrate the impact of the interaction between the individual ink solvents and different organic layers onto the relevant electrical device parameters like the ON/OFF ratio.

Poly(vinyldene fluoride-co-hexaflouropropylene), a high κ dielectric and high energy density material, is examined for FET application . PVdF-HFP has 4 polymorphs namely α(non-polar), β, γ and δ (polar) as for PVDF. Depending on the processing conditions the polymer can exhibit one of these forms. In this work we have compared the FET made with PVdF-HFP and PVdF-HFP/clay nanocomposite. We have made nanocomposite of PVdF-HFP with different weight fraction of clay. The spin coated pure PVdF-HFP film goes into non-polar phase whereas the composite film goes into polar phase. These transistors were made with zinc oxide as channel layer. The ZnO layer was grown by RF sputtering. The electrical characterizations involved measurements of Impedance spectroscopy, C-V and current voltage characteristics. All the transistor were made on glass substrate with operating voltage of 100V. The pure PVdF-HFP based FET showed the on-off ratio of > 103 and mobility of about 2 cm2/V-1s-1 whereas nonvolatile memory transistors with nanocomposites showed mobility of 1cm2V-1s-1 with bistability of 103 .The addition of clay led to ferroelectric γ phase in the polymer nanocomposite as well as the clay can traps the charge carrier The dynamic nonvolatile memory property of the PVdF-HFP/clay nanocomposite FET is also studied

Organic semiconductors are gaining increasing importance as materials for (opto-) electronics, and their combination with inorganic materials is also appealing. Low cost, flexibility, easy processing on large area are the main reasons for research on realizing devices, such as organic light emitting diodes, thin film transistors, and photovoltaic cells ; to also implement data storage nonvolatile memory devices are attracting interest.
Among the different types of organic-based memories, resistive switching devices are promising for their simple structure, which typically comprises a hybrid organic/inorganic active layer, i.e., metal nanoparticles (NPs) embedded in an organic semiconductor, sandwiched between two electrodes. A bistable electrical switching behavior has been reported for a wide range of combination of materials, Nonetheless, the switching mechanism is still debated. In one model, the metal NPs act as charge traps, thus changing the device's conductance state via space charge limitation. The metal NPs discharging supposedly occurs upon injection of charges with opposite sign.
Optical addressing might be an approach to change the charge state of the metal NPs and could allow improved functionality and reduced writing time. We used ultraviolet photoelectron spectroscopy (UPS) to investigate charging and light-induced decharging of Au NPs imbedded in a matrix of organic semiconductors, i.e., aluminum tris(8-hydroxyquinoline) (Alq3) and 4,4-bis[N-(1-naphthyl)-N-phenyl-amino]diphenyl (α-NPD). Depending on the density and size of Au NPs, as determined by transmission electron microscopy, we find a reduced photoelectron kinetic energy in dark, indicative of trapping of positive charges on the NPs. Upon light irradiation, photoelectrons resume the initial higher kinetic energy, evidencing that the charges on the Au NPs can be de-trapped by optical means. This mechanism may lead to the realization of novel organic/inorganic memory elements.

We demonstrate how to electrically modify the connectivity of silver nanowire networks to create materials with tunable electrical conductivity. Spray-deposition of nanowires creates dense, two-dimensional films of randomly oriented nanowires that are addressable using shadow mask electrodes. The junctions between nanowires initially act as capacitors with a random distribution of electrical properties, but can be activated to become conductive. The connectivity between individual nanowires determines what path is most favorable for charge traversing the network, as well as the sheet resistance of the material. We study silver nanowires whose polymer coating can break down irreversibly under an electric field. Under electrical stressing, the network self-selects the lowest resistance paths to be activated first, with subsequent voltage cycling activating additional conduction paths. Passive voltage contrast imaging is used to visualize the activation and evolution of connectivity within these networks, and is correlated with I-V measurements to match changes in connectivity to changes in device resistance. Electrostatic force microscopy is also used to modify and visualize connectivity cells in nanowire networks. We simulate these nanowire networks as leaky resistor-capacitor networks with a random distribution of junction activation voltages, and find a universal scaling behavior relating the size of the connectivity cell to the applied voltage. Finally, we show that local connectivity within these networks can be programmed to create materials whose properties evolve and adapt in response to external stimuli.