High Etch Selectivity for Dry Etching (Zn,Sn)O Thin Films to SiO₂ for Fabricating The Thin Film Transistor and 3-Dimensional Dynamic Random Access Memory

Current 2D dynamic random access memory (DRAM) faces the scaling down limitation, so developing 3D DRAM is necessary to improve the integration density without relying solely on lateral device scaling. The semiconductor industry studied polycrystalline silicon as a channel material for 3D DRAM, similar to that used in 3D NAND flash memory. However, adopting polycrystalline silicon poses a critical problem due to its grain boundary effect, leading to degraded cell-to-cell uniformity. Therefore, amorphous oxide semiconductors are suggested as a potential candidate for the 3D DRAM channel materials. Amorphous zinc tin oxide (a-ZTO, Zn:Sn ratio ~ 50:50) can be a suitable channel material for 3D DRAM due to its promising electrical characteristics, such as high electron mobility, low off-current, and wide band gap. Also, it can be readily deposited by the atomic layer deposition (ALD) process, which is inevitable for 3D DRAM integration.<br/>In fabricating 3D DRAM, etching a-ZTO film is required, but it must have a high selectivity to a sublayer, such as a gate insulator (i.e., SiO₂). Also, in 3D DRAM integration, the a-ZTO film is deposited by an ALD along the vertical channel structure, and the a-ZTO film deposited on the top portion of the pattern should be removed using the dry etching process while minimizing the damaging effect on the underlying structures. In the fabrication of a peripheral transistor, a-ZTO film out of the active region should be etched entirely while minimizing damage to the underlying thin gate insulator. The wet etching of ZTO thin films using hydrochloric acid can be used for specific cases. However, its isotropic and selective-grain boundary etching properties can pose several integration issues. Therefore, a stable dry etching process with high etch selectivity is needed. This study reports a stable dry etching process with high etch selectivity of ALD a-ZTO thin films with SiO₂ using the CH₄/N₂/Ar (30/15/31 sccm) plasma. The achieved etch selectivity was as high as 20:1.<br/>This study also verified the possible issues in the electrical characteristics when the above recipe with high selectivity is adapted to fabricate the a-ZTO thin film transistor (a-ZTO-TFT) having TiN source and drain, 100nm-thick thermal SiO₂ gate insulator, and p⁺⁺ Si gate. For the stable operation of the TFT, a-ZTO film other than the channel region must be etched entirely away while minimizing the etching of the underlying SiO₂ layer. It is usual to over-etch the a-ZTO channel layer for this purpose. In this study, the ZTO channel etching was attempted by adopting BCl₃/N₂/Ar (15/5/30 sccm) gases, a previously reported method, and using CH₄/N₂/Ar (30/31/15 sccm) gases, a newly developed method. The over-etch was performed from 20% to 100% at intervals of 20% for each gas condition. Compared to the results of 5 over-etch conditions of applying BCl₃/N₂/Ar gases, less variation of on-current (1.27x10^-4A → 4.76x10^-5A at 20.1V of gate voltage), better average subthreshold swing (0.224V/dec → 0.182V/dec), and less variation of threshold voltage (1.00V → 0.70V) were obtained from the 5 over-etch conditions with the CH₄/N₂/Ar gases. This improvement was attributed to the improved etching selectivity of the latter compared with the former method. The presentation will report more detailed fabrication steps and electrical characteristics of the a-ZTO-TFT for their use in 3D DRAM.