Apr 23, 2024
2:15pm - 2:30pm
Room 436, Level 4, Summit
Hans Kleemann1,Ali Solgi1
Photonic Materials (IAPP) and Institute for Applied Physics, Technische Universität Dresden1
Hans Kleemann1,Ali Solgi1
Photonic Materials (IAPP) and Institute for Applied Physics, Technische Universität Dresden1
Organic electrochemical transistors (OECTs) have garnered significant interest due to their ease of fabrication, flexibility, biocompatibility, and suitability for biosignal sensing, including applications in neuromorphic computing. However, power consumption is pivotal in neuromorphic computing and logic circuit applications. The central challenge in these applications lies in identifying the optimal balance between the operational speed of the device and the magnitude of current flowing through the channel, which is ultimately all defined by the transistor geometry. Consequently, much effort has been put into miniaturizing the OECTs, which unfortunately comes with the disadvantage of increasing integration complexity and cost.<br/>Here, we propose a novel top-gate architecture for OECTs in pursuit of higher operational frequencies, power efficiency, and the ability to integrate using low-cost printing techniques seamlessly. We analyze the scaling of these printed, all-solid-state top-gate devices vs. side-gate structures, and we define a figure of merit describing how efficiently transconductance is utilized for device speed, which is most relevant for integrated circuits. Using this figure of merit, we should reduce the channel length and increase charge carrier mobility, or the mobility capacitance product does not make device operation more efficient. Instead, sub-millisecond device operation can be obtained even for devices with a channel length as long as 200µm, enabling, e.g., the design of fast and power-efficient spiking neurons using the top-gate architecture.