Direct Metal Etch of Ruthenium: Enabling Sub 20nm Pitch Interconnects

The realisation of Moore’s law, which predicts that the number of transistors in an integrated circuit will double every 2 years, has been achieved by countless innovations in the semiconductor industry over the last 60 years. As device dimensions shrink the innovation in transistor design often grabs the headlines but of course this must be supported by innovation in the interconnect technology as the minimum metal line pitch shrinkage follows that of the gate.<br/> <br/>Around 25 years ago the semiconductor industry made the radical transition from subtractive aluminium patterning to copper damascene, which required significantly different materials and fabrication techniques. This transition was necessary to increase the processing speed of the microchips; as the resistivity of Cu is 40% lower than Al, the RC delay is reduced, which is the performance indicator in BEOL.<br/> <br/>In the present day, we are approaching the end of Cu damascene scaling and thus there is the requirement for another disruptive technology change to keep the RC delay at acceptable levels. Below 2nm node it is predicted that the minimum metal pitch will be &lt; 20nm, at which point Cu damascene is not an option; even if it were possible to fill 10nm lines with Cu, the need for a metal barrier means the resistance would become too high. Therefore, we must look for an alternative interconnect material. One strong candidate is Ru, which has the convenience of having low resistivity and can be used without a barrier, giving an immediate resistance benefit for line dimensions below 12nm. Another advantage is that it can be patterned subtractively, giving access to higher aspect ratio lines than can be achieved with damascene integration schemes.<br/> <br/>In this talk we will discuss how the subtractive patterning of Ru can realise the semi-damascene scheme which is proposed by imec as the alternative to Cu damascene at advanced logic nodes.