Load Line Analysis of The Memory Window in Amorphous Indium-Gallium-Zinc Oxide-Based Ferroelectric Thin-Film Transistor

Ferroelectric thin-film transistors (FeTFTs) attract a great deal of interest for their potential to reduce operating voltage and enhance durability in non-volatile memories by minimizing the interfacial layer through the use of amorphous oxide semiconductors (AOS) instead of silicon (Si). Especially, FeTFTs with amorphous indium-gallium-zinc oxide (<i>a</i>-IGZO) channels offer high on-off ratios, fast operation speed, and compatibility with complementary metal-oxide-semiconductor (CMOS) technology. The Memory Window (MW) of FeTFTs holds significant importance, particularly in applications such as multilevel cell non-volatile memory and neuromorphic systems. However, there have been limited reports on the MW achievable with n-type <i>a</i>-IGZO, primarily due to the scarcity of hole carriers necessary for polarization switching.<br/>This study investigates the attainable MW through load line analysis in FeTFTs. Load line analysis is a widely used technique that enables a comprehensive graphical representation of the intricate operation of solid-state circuits with nonlinear charge-voltage or current-voltage responses. In contrast to ferroelectric field-effect transistors (FeFETs) based on Si, which can secure an MW at the twice coercive voltage (2<i>V</i>_c) level, the inherent characteristics of FeTFTs based on AOS material result in an inevitably smaller MW due to the absence of an inversion mode.<br/>Furthermore, the influence of various process conditions in FeTFTs is explored, including the atomic layer deposition temperature of the aluminum-doped hafnium oxide (HAO) ferroelectric layer, rapid thermal annealing temperature for crystallization of the HAO layer, and the thickness of the <i>a</i>-IGZO channel. Aluminum is selected as the impurity for hafnium oxide due to its thermal stability and compatibility with CMOS processes. The impact of these process variables on ferroelectric performance in metal-ferroelectric-semiconductor-metal capacitors and the FeTFT structures is analyzed by evaluating polarization-voltage, capacitance-voltage, and current-voltage characteristics under various conditions. In addition, load line analysis is performed at each process condition based on these characteristics. These findings can potentially guide the development of high-performance FeTFTs with optimized MW for various applications.