Experimental Characterization and 1D KMC-Based Simulation of the Reliability of 28nm BEOL Integrated VCM ReRAM

Valence change memory (VCM) cells are promising candidates for non-volatile memory applications and neuromorphic computing [1]. Typically, they consist of a simple metal-insulator-metal (MIM) structure, where the insulating oxide layer can be manipulated by an externally applied voltage. Thereby, oxygen vacancies can be incorporated and redistributed in a way that the resistance of the oxide layer can be switched between a high resistive state (HRS) and a low resistive state (LRS). These states can be read out non-destructively and switched very fast. Furthermore, the cells show a great scalability, CMOS (complementary metal-oxide-semiconductor) compatibility and low power consumption [2,3].<br/><br/>Despite their excellent characteristics, a few questions and challenges concerning the key parameter reliability are still open. During the experimental characterization of the generally great endurance of 2Mbit VCM cells, we found a rare failure mechanism in a few ppm of the cells after about 500k cycles, where the cells could not be switched back into the HRS (RESET) [4]. The investigated cells are integrated back-end-of-line (BEOL) in a 1-transistor-1-resistor (1T1R) configuration in a 28nm CMOS technology.<br/><br/>Based on the JART VCM 1.0 model of La Torre [5], we developed a 1D KMC simulation model to physically explain the observed failure mechanism. We show that the interplay of the transistor and the VCM cell plays an important role. In rare cases of a combination of a high resistive transistor and a very low resistive cell, the voltage dropping over the cell is not sufficient to originate the RESET. Additionally, we experimentally investigate the RESET kinetics and their dependence on the used transistor. Here again, we can explain our findings with the help of the developed 1D KMC simulation model. In conclusion, we want to point out the importance of the interplay of transistor and resistor and its understanding for the improvement of the reliability.<br/><br/>[1] R. Waser, R. Dittmann, G. Staikov and K. Szot, <i>Adv. Mater.</i>, 21: 2632-2663, 2009.<br/>[2] Y. Chen, <i>IEEE Trans. Electron Devices</i>, vol. 67, no. 4, pp. 1420-1433, 2020.<br/>[3] M. von Witzleben, T. Hennen, A. Kindsmüller, S. Menzel, R. Waser and U. Böttger,<i> J. Appl. Phys.</i>, 127 (20): 204501, 2020.<br/>[4] N. Kopperberg, S. Wiefels, K. Hofmann, J. Otterstedt, D. J. Wouters, R. Waser and S. Menzel<i>,</i> <i>IEEE Access</i>, vol. 10, pp. 122696-122705, 2022.<br/>[5] C. La Torre, A. F. Zurhelle, T. Breuer, R. Waser and S. Menzel, <i>IEEE Trans. </i><i>Electron Devices</i>, vol. 66, no. 3, pp. 1268-1275, 2019.