Cryogenic Bistable Current-Voltage Dependence in a Silicon pn-Junction formed by wafer-bonding

As the semiconductor industry readies itself for the 'post-Moore' era, it is already challenging to achieve further performance improvements through miniaturization alone. As a result, leading semiconductor companies like Intel, Samsung, and TSMC are developing 2.5D packaging technology with direct wafer bonding, which connects chips directly without bumps. The substantial benefits in minimizing the transmission delays and parasitics as well as in efficient power management and heat dissipation make direct wafer bonding an essential technology for development of high-performance chips. In parallel, the drive for higher-performance as well as quantum computing has extended exploration of silicon electronics into the cryogenic regime.<br/>Here, we report on a novel phenomenon, a bistable current-voltage dependence, found in the cryogenic operation of a Si pn-junction. The pn-junction was formed by direct wafer-bonding of a heavily doped p-type silicon wafer to an n-type silicon wafer. Electrical property was measured with metal ohmic contacts on the top and bottom surfaces. The measurement results showed normal diode I-V characteristics at room temperature. However, when the device is measured at cryogenic temperatures below 30K, an S-shaped I-V dependence emerges and becomes more pronounced with decreasing temperature. This results in a bistable current switching response when sourcing voltage, due to the negative differential resistance between the two stable states. Underlying this interesting and potentially useful novel functionality is the presence of a 2nm thick SiO2 barrier layer formed right at the metallurgical interface between the two wafer during the particular wafer-bonding process. Our study aided by computational model simulation provides insights into switching mechanism(s) in relation to the structural features of the wafer-bonded pn-junction and suggests potential innovative uses of the functionality.