Dec 5, 2024
9:15am - 9:30am
Sheraton, Second Floor, Back Bay C
Chloe Leblanc1,Yinuo Zhang1,Hyunmin Cho1,Seunguk Song1,Chen Chen2,Shalini Kumari2,Joan Redwing2,Roy Olsson1,Deep Jariwala1
University of Pennsylvania1,The Pennsylvania State University2
Chloe Leblanc1,Yinuo Zhang1,Hyunmin Cho1,Seunguk Song1,Chen Chen2,Shalini Kumari2,Joan Redwing2,Roy Olsson1,Deep Jariwala1
University of Pennsylvania1,The Pennsylvania State University2
The continued evolution of Silicon-based CMOS technology has reached its physical limits with regards to energy consumption and density. This is an increasing concern for computations and algorithms that involve large amounts of data processing and multivariable optimization.<sup> </sup>The invention of new devices and architectures that emphasize low-power consumption is therefore needed.<sup> </sup>At the architecture level, access to memory and readout are the major bottlenecks of the traditional von Neumann computing architecture in commercial technology today. Ferroelectric-based non-volatile memories (NVM) could be an answer to this challenge. Ferroelectric materials share the ability to maintain a stable polar state in the absence of an electric field over long periods of time. This adjustable polarization can be used store, erase, and reprogram information in a non-volatile manner. Ferroelectric NVM enables in-memory computing applications, leading to vastly more energy efficient systems and architectures. But to be of interest in industrial applications, these ferroelectric devices must be highly scalable and operate at low switching voltages.<br/>In this study, we demonstrated non-volatile ferroelectric field-effect transistors (FeFETs) based on Aluminum Scandium Nitride (Al<sub>1-x</sub>Sc<sub>x</sub>N) and two-dimensional van der Waals (2D vdW) semiconductor channels. In 2D vdW FeFETs, the remnant polarization of the ferroelectric material strongly controls the conductance of the atomically thick vdW semiconductor channel. Al<sub>1−x</sub>Sc<sub>x</sub>N stands out for its numerous beneficial properties such as low dielectric loss, low deposition temperature compatible with modern CMOS production methods and high remnant polarization <i>P<sub>r</sub></i> (80–115 μC/cm<sup>2</sup>). We showed operational FeFETs with channel lengths of 500, 250, 100 and 50 nm templated on 10 nm thick Al<sub>0.68</sub>Sc<sub>0.32</sub>N and 5 nm thick Al<sub>0.72</sub>Sc<sub>0.28</sub>N layers. We find that the voltage required to activate these devices is reduced to < 1V, while maintaining an ON/OFF ratio up to 10<sup>6</sup>. Our devices are highly scalable, with channel lengths ranging from 500 nm to 50 nm. We found that the effect of charge trapping in the FeFETs was altered by ferroelectric film thickness and channel length. Our 2D channel of choice was monolayer MoS<sub>2</sub> and the underlying template for the Al<sub>1-x</sub>Sc<sub>x</sub>N films was 〈111〉 Al. Measurements were performed in ambient, vacuum (<10<sup>-5</sup> Torr) and cold (300 K to 150 K) environments to further characterize the effects of charge trapping on device behavior. Piezoelectric force microscopy scans were able to confirm that Al<sub>1-x</sub>Sc<sub>x</sub>N switches uniformly between polar states below the entire channel area after a voltage pulse is applied to the FeFETs. These devices display a very low coercive field, which capacitor measurements also confirmed. Retention measurements further proved that the devices could maintain their polar state for at least 1000s. Finally, equivalent FeFET structures with p-type monolayer WSe<sub>2</sub> channels illustrated the behavior of the devices related to the choice of channel.<br/><br/>Acknowledgements: The authors acknowledge primary support from the Intel SRS program. The MOCVD grown TMDC monolayer samples were provided by the 2D Crystal Consortium Materials Innovation Platform (2DCC-MIP) facility at Penn State which is funded by NSF under cooperative agreement DMR-2039351.