December 1 - 6, 2024
Boston, Massachusetts

Event Supporters

2024 MRS Fall Meeting & Exhibit
CH05.03.02

High-Resolution 3D Imaging of Gate-All-Around (GAA) Devices Using Multislice Electron Ptychography

When and Where

Dec 2, 2024
4:00pm - 4:15pm
Sheraton, Third Floor, Fairfax B

Presenter(s)

Co-Author(s)

Shake Karapetyan1,Ta-Kun Chen2,Duen-Huei Hou2,David Muller1

Cornell University1,Taiwan Semiconductor Manufacturing Company2

Abstract

Shake Karapetyan1,Ta-Kun Chen2,Duen-Huei Hou2,David Muller1

Cornell University1,Taiwan Semiconductor Manufacturing Company2
Advances in semiconductor technology have highlighted the need for imaging techniques to visualize the intricate atomic structures of buried interfaces and potential defects in Gate-All-Around (GAA) transistors. This is explicitly called out as a grand challenge in the CHIPS Advanced Metrology for Future Microelectronics Manufacturing roadmap. We demonstrate how this need can be met by imaging modern GAA devices with multislice electron ptychography (MEP). Our method provides sub-Angstrom in-plane and only a few nm in-depth resolution, significantly surpassing the capabilities of conventional (S)TEM imaging techniques, and revealing structural details that were previously inaccessible.<br/>Generating a 3D image using conventional Scanning Transmission Electron Microscopy (STEM) imaging modes like annular dark field (ADF) or integrated differential phase contrast (iDPC) requires acquiring a through-focal series from multiple scans of the same area at different defocus values, reducing the available electron dose budget per scan. These methods are susceptible to multiple scattering and tilt artifacts, reducing the reliability and interpretability of features in depth. In contrast, MEP, a relatively new 4D-STEM technique, enables a 3D reconstruction with better resolution in all dimensions from just a single scan and in a more dose-efficient manner.<br/>Experimentally, we utilize MEP to image GAA transistors, revealing channel irregularities and stacking defects in the crystalline silicon channel. These critical features, essential in the performance and reliability of the devices, are not discernible with traditional methods and could easily be missed without MEP. Through simulations, we validate MEP's accuracy under realistic experimental conditions by successfully recovering critical features from a known atomic model of a transistor.<br/>By offering deep sub-Å lateral resolution and a few nanometers of depth resolution, MEP enables detailed visualization and analysis of both crystalline and amorphous materials, interfaces, and buried defects. This level of depth-resolved detail is not only essential for modern device imaging but also necessary for advancing our understanding of defect formation and behavior in materials.<br/><br/><b>Acknowledgements:</b> Work supported by TSMC JDP. Microscope facility support from NSF DMR-1719875, DMR-2039380. R. Aveyard and B. Rieger provided an atomic model of a GAA transistor. Dr. Glen Wilk, ASM and IMEC provided the GAA sample. Eurofins Nanolab Technologies prepared the GAA TEM lamella.

Keywords

metrology | scanning transmission electron microscopy (STEM)

Symposium Organizers

Miaofang Chi, Oak Ridge National Laboratory
Ryo Ishikawa, The University of Tokyo
Robert Klie, University of Illinois at Chicago
Quentin Ramasse, SuperSTEM Laboratory

Symposium Support

Bronze
EKSPLA 
Protochips
Thermo Fisher Scientific, Inc.

Session Chairs

Miaofang Chi
Robert Klie

In this Session