December 1 - 6, 2024
Boston, Massachusetts
Symposium Supporters
2024 MRS Fall Meeting & Exhibit
EL05.11.03

Processing and Characterization of Polycrystalline Silicon for Ultra-Low-Power Neuromorphic Applications

When and Where

Dec 5, 2024
8:00pm - 10:00pm
Hynes, Level 1, Hall A

Presenter(s)

Co-Author(s)

Soomin Kim1,Seongjae Cho1,Woo Young Choi2,Hyungcheol Shin2

Ewha Womans University1,Seoul National University2

Abstract

Soomin Kim1,Seongjae Cho1,Woo Young Choi2,Hyungcheol Shin2

Ewha Womans University1,Seoul National University2
Polycrystalline silicon (poly-Si) is increasingly incorporated not only in logic devices but also in memory devices towards the low-power neuromorphic systems. Its full compatibility with Si complementary metal-oxide-semiconductor (CMOS) makes it crucial in the recent semiconductor device and system technologies. Although poly-Si has been utilized in fabricating the thin-film transistors (TFTs), its microstructure and electrical characteristics need to be intensively studied for the application in the nanoscale device and circuit implementations. In this study, processing and characterization of poly-Si thin film are conducted in depth with the help of various analysis approaches including high-resolution transmission electron microscopy (HR-TEM), X-ray diffraction (XRD), energy dispersive spectroscopy (EDS), and atomic force microscopy (AFM). Furthermore, advanced dynamic random-access memory (DRAM) and charge-trap flash (CTF) memory based on the poly-Si channels were fabricated and their electrical performances have been closely investigated with an emphasis on their low-power operation capabilities. The reason that two different types of memories are studied lies in the fact that the traps and low crystallinity might provide the keys to performances improvements of DRAM and CTF flash memory with regard to data retention and inference energy. While researches have been dedicated to truncation of the bulky capacitor from the conventional DRAM cell, relatively short data retention of the capacitorless DRAM has been regarded as its drawback. In the poly-Si capacitorless DRAM, the grain boundary acts as transient charge trap sites, which allows for a substantially extended retention time without requiring complicated operation schemes to hold the carriers stored in the floating body. By reducing the frequency of refresh operation, lower power consumption and wider memory bandwidth are achieved at the same time. The processing conditions for the poly-Si channel were established and the thin-film characterizations were conducted in various aspects. 20-nm poly-Si thin films were deposited by low-pressure chemical vapor deposition (LPCVD) and annealed at different temperatures ranging from 500 °C to 1,000 °C for 24 hours to examine the change in morphology and crystallinity. It was confirmed by TEM and XRD analyses that the crystallite size increased with temperature. Annealing at 600 °C resulted in a grain size of 26.2±1.4 nm, which revealed that change in morphology could be expected while the atomic diffusion was experimentally minimal. Under the annealing condition, the crystallinities in the <111>, <220>, and <311> directions were notable. Poly-Si DRAM cell with a gate length of 500 nm and a channel thickness of 50 nm was fabricated. The critical dimensions and species were identified by HR-TEM and EDS, respectively. XRD and AFM were employed to identify the grain size and surface roughness of the poly-Si channel, which were 26.2 nm and 0.634 nm, respectively. Transient measurement results from the fabricated poly-Si capacitorless DRAM show that holes can be trapped and de-trapped by a set of gate and drain voltages, with a significantly increased data retention time reaching 1.2 s which is about 20 times longer than the industry reference of 64 ms. The prepared poly-Si thin film can be also introduced for the channel of CTF flash memory cell. The nonvolatile memories can be adopted in the hardware-driven ultra-low-power neuromorphic applications. The inference current was greatly reduced down to pA level in the poly-Si channel and the resultant inference energy was calculated to be below 10 fJ. A small change in electrical weight was obtained by precisely controlling the amount of change over the potentiation and depression, and a highly linear weight tunability was obtained over 20 levels from a CTF synaptic device. This research was supported by the Ministry of Science and ICT (MSIT) of Korea under the Grant 2020-0-01294.

Keywords

thin film | x-ray diffraction (XRD)

Symposium Organizers

Paschalis Gkoupidenis, Max Planck Institute
Francesca Santoro, Forschungszentrum Jülich/RWTH Aachen University
Ioulia Tzouvadaki, Ghent University
Yoeri van de Burgt, Technische Universiteit Eindhoven

Session Chairs

Sahika Inal
Ioulia Tzouvadaki

In this Session