Even as conventional Cu/ULK interconnect technology has slowed in recent years due to challenges in both ultra-low k integration and metal barrier scaling, a plethora of options are being investigated for technology nodes below 10 nm, including new conductors, dielectrics, barrier layers, and process integration methods. In parallel, emerging packaging technology such as 2.5D/3D ICs integration are demonstrating means to improve circuit density and performance. Technologies including Through Silicon Vias are increasingly utilizing recent interconnect material and process advances to further packaging innovations. Finally, using interconnects as a backbone, the introduction of additional functionality in the BEOL has constituted new areas of research and opportunity. This session will focus on both continued advances in conventional interconnect technology and new emerging areas. Topics will include advances in ILD materials and integration, novel etch stop and hard-mask materials, advanced metallization materials and processes, area selective deposition and supervia scaling boosters, alternatives to conventional interconnect technology (3D, optical interconnects) and the introduction of additional functionalities in the BEOL.

atomic layer deposition chemical vapor deposition (CVD) (deposition) CMP (chemical mechanical processing) dielectric electrodeposition metallic conductor metrology microelectronics packaging physical vapor deposition (PVD)