Bi₂Te₃/Ge van der Waals Heterostructure for Unpinning Fermi-Level of n-Ge

Recently, Ge FinFET CMOS has shown very promising results at cryogenic temperatures, such as extremely suppressed off-leakage current and significantly improved subthreshold swing, which make it a strong candidate for High-Performance-Computing (HPC) applications as well as space technology.[1] However, the contact resistance of Ge nFET is still a big hindrance, preventing Ge CMOS inverters from achieving even better gain under 10 K. It is well known that metal/n-Ge interfaces exhibit strong Fermi-level pinning (FLP),[2] resulting in a large contact resistance. For the past decades, tremendous efforts have been put to solve this issue, but achieving Fermi-level depinning on n-Ge is still beset with difficulties.
In this work, the material and electrical properties of Bi₂Te₃ on Ge have been investigated under different annealing temperatures. Surprisingly, an atomically aligned Bi₂Te₃/Ge quasi vdW interface can be attained after 400 °C annealing as confirmed by X-ray diffraction (XRD) and scanning transmission electron microscope (STEM) observation. Besides, the Bi₂Te₃/n-Ge junction diode exhibited clear Ohmic behavior. A very low Schottky barrier height of ~ 0.1 eV was also extracted from temperature dependence of I-V characteristics, suggesting the Fermi-level depinning between Bi₂Te₃ and Ge. This work indicates that Bi₂Te₃ has a strong potential to open a new era for Ge CMOS devices as a S/D contact material.


Acknowledgement: This work is supported by Kakenhi Grants-in-Aid (JP23H01474) from the Japan Society for the Promotion of Science (JSPS)

References: [1] X. Yu et al., IEDM 6-2 (2023). [2] T. Nishimura et al., Appl. Phys. Lett. 91, 123123 (2007).