Apr 9, 2025
4:45pm - 5:00pm
Summit, Level 4, Room 425
Andrew Mannix1,2
Stanford University1,SLAC National Accelerator Laboratory2
Atomically thin van der Waals materials offer precise layer-by-layer control over composition, interfacial symmetry, moiré superlattices, and interlayer coupling. However, scaling these innovations for practical applications remains challenging. In this talk, I will present our development of versatile synthesis and characterization techniques to advance the growth and device fabrication of 2D semiconductors and their heterostructures.
Optimizing the growth of transition metal dichalcogenides (TMDCs) such as MoS
2 and WSe
2 is crucial for high-performance devices. We have developed a hybrid metal-organic chemical vapor deposition (HyMOCVD) process for precise compositional control, enabling tunable WS
2 growth through doping, alloying, and the use of growth-promoting additives [1]. By adjusting the growth chemistry and kinetics, we achieved polytype-selective growth of ferroelectric 3R-phase TMDC films on dielectric substrates [2], opening avenues for ferroelectric devices and nonlinear optics.
Improving electrical contacts to 2D semiconductors is another critical challenge. Although Ni has a suboptimal work function, it forms effective contacts with n-type WS
2. We have observed that mechanical strain induced by Ni electrode deposition can significantly enhance device performance, resulting in up to a 2.7× increase in transistor on-state current and a 78% reduction in contact resistance [3]. This often-overlooked effect shows great potential for further device engineering. Making contact to p-type TMDCs has proven more challenging than for n-type devices. We have demonstrated that doping monolayer WSe
2 transistors with chloroform significantly enhances p-type performance, achieving up to a 100× improvement in drain current, high on/off ratios (>10
10), low contact resistance (2.5 kΩ), and stability over several months. The chloroform doping method is straightforward, clean, and stable approach for high-performance
p-type 2D semiconductor devices at room and cryogenic temperatures.
[1] Z. Zhang, L. Hoang., et al.,
ACS Nano 18, 25414 (2024).
[2] Z. Zhang, et al.,
Nano Letters,
24, 12775 (2024).
[3] L. Hoang, et al.,
Nano Letters,
24, 12768 (2024).