Apr 10, 2025
11:15am - 11:30am
Summit, Level 4, Room 424
Robert Bennett1,Harmon Gault1,Asir Intisar Khan1,Kathryn Neilson1,Lauren Hoang1,Tara Pena1,Zhepeng Zhang1,2,Andrew J. Mannix1,Eric Pop1
Stanford University1,SLAC National Accelerator Laboratory2
Robert Bennett1,Harmon Gault1,Asir Intisar Khan1,Kathryn Neilson1,Lauren Hoang1,Tara Pena1,Zhepeng Zhang1,2,Andrew J. Mannix1,Eric Pop1
Stanford University1,SLAC National Accelerator Laboratory2
Two-dimensional (2D) semiconductors have emerged as promising candidates for next-generation field-effect transistors (FETs), offering both low leakage and high drive currents in nanoscale devices [1]. However, the performance of these devices is strongly influenced by the quality of the 2D semiconductor, which is affected by factors such as defect concentrations, stress/strain profiles, and the number of grain boundaries. Additionally, the fabrication techniques used to process 2D semiconductors into FETs can further impact material quality; for example, depositing high-κ insulators on 2D semiconductors can introduce interfacial defects [2]. As a result, it is crucial to monitor the material properties of 2D semiconductors after their integration into FETs.
To assess the quality of the FET channel material, parameters such as mobility, contact barriers, and defect energy levels are frequently estimated by fitting current-voltage (
I-
V) and/or capacitance-voltage (
C-V) measurements to technology computer-aided design (TCAD) simulations (e.g., Sentaurus) or compact models, allowing for the simultaneous characterization of multiple material parameters post-integration. However, these fitting procedures can be labor-intensive and often require expert-level knowledge to manually calibrate numerous parameters. Thus, while powerful and thorough, this approach remains out-of-reach for many researchers who wish to gain deeper insights into the behavior of 2D semiconductors.
In this work, we address these challenges by using machine learning to autonomously estimate the material properties of 2D semiconductors
via TCAD fitting. Unlike similar machine learning approaches used to calibrate TCAD models for silicon-based devices (that abstract material-level parameters into device-level metrics, such as lumped contact resistances and parasitic capacitances [3–5]), we demonstrate that our approach is suitable for extracting fundamental material parameters such as mobility, band alignment to contact metals, defect concentration, and band tail distributions directly from
I-
V measurements of individual devices.
Our approach explicitly treats
I-
V data sequentially by employing recurrent neural networks, which we find greatly improves the model training efficiency compared to feed-forward neural networks used in recent works [6]. Consequently, unlike previous reports for silicon-based devices, which often require training sets with tens of thousands of devices [3–5], we find that we can accurately train our model using relatively small data sets with just a few thousand unique devices. This approach allows us to fit a wide range of parameters using a training set that can be generated much more quickly compared to those necessitated by other recent efforts.
We validate our trained model by reverse-engineering seven key material parameters (mobility, contact work function, and five additional parameters used to characterize the defect energy distributions and band tail profiles) from TCAD-simulated 2D semiconductor FETs, finding close agreement between the predicted
vs. actual quantities in our test set. Further, we find that the extracted parameters allow the input
I-
V characteristics to be closely matched, yielding a median coefficient of determination
R2 > 0.99 across the test set of 100 unique devices. We anticipate that this approach will significantly streamline the evaluation of 2D semiconductor material quality by automating the measurements of critical material parameters.
References:
[1] K. P. O’Brien
et al.,
Nat. Commun. 14, 6400 (2023)
[2] Y. Y. Illarionov
et al.,
Nat. Commun. 11, 3385 (2020)
[3] M. Kao
et al.,
IEEE TED 69 (2022)
[4] F. Chavez
et al.,
Solid-State Electronics 209 (2023)
[5] A. Singhal
et al.,
IEEE TED 71 (2024)
[6] R. Ghoshhajra
et al.,
IEEE DevIC (2021)