Apr 10, 2025
5:00pm - 7:00pm
Summit, Level 2, Flex Hall C
Soohwan Yoo1,Yong-Young Noh1
Pohang University of Science and Technology1
Soohwan Yoo1,Yong-Young Noh1
Pohang University of Science and Technology1
Heterostructure-based flash memory has garnered significant attention due to its potential for rapid operation and lower power consumption.
1, 2 However, the fabrication of 2D materials-based channels and charge trapping layers in these devices, typically synthesized via mechanical exfoliation or CVD growth, encounters challenges regarding yield and scalability. Halide perovskites offer promising alternatives for the channel and charge trapping layers in heterostructure memory devices, providing advantages such as scalability to large areas and the ease of heterostructure formation through compositional modulation.
3, 4, 5 In this work, we report a transistor-type memory that employs tin halide perovskite thin films, where heterostructures are formed through the incorporation of ethylenediammonium (EDA). The regions containing EDA function as charge trapping centers, thereby inducing the memory characteristics in the device. The optimized memory device with 1mol% EDA exhibits memory window of 2.892 V and an on/off current ratio (I
on/I
off) over 10
5 repeatedly in transfer characterization under
VGS sweep range of ±5 V. The device demonstrates stable data storage, with retention time surpassing 2000 seconds and endurance exceeding 250 cycles while maintaining I
on/I
off over 10
3. Multi-level data storage capability is also achieved through the application of various programming/erasing voltages.
References1. X. Huang et al.,
Nat.
Nanotech.
18, 486-492 (2023).
2. L. Liu et al.,
Nat.
Nanotech.
16, 874-881 (2021).
3. J. Li et al.,
Nat.
Photon.
17, 435-441 (2023).
4. H. Zhu et al.,
Nat. Electron.
6, 650-657 (2023).
5. W. Ke et al.,
Science Advances 3, e1701293 (2017).