Flexible Dual-Gate Field-Effect Transistors and Circuits Based on Hybrid MOCVD-Grown WS₂ Monolayers

Two-dimensional (2D) semiconductors have gained significant interest in flexible and wearable electronics applications due to their atomically thin structure, good charge carrier mobility, and potential for heterogenous integration with diverse substrates [1]. However, the utility for 2D semiconductors in wearable electronics has not been fully explored. Tungsten disulfide, WS₂, is a 2D semiconductor that can be readily synthesized and is sensitive to environmental stimuli, making it a candidate for wearable intelligent sensing applications [2]. While some previous work has emerged on integrating 2D semiconductors into flexible substrates, most work has focused on single-gated devices.

Here, we present dual-gated field-effect transistors and inverter circuits fabricated on 125-µm thick flexible polyethylene naphthalate (PEN) substrates. We first deposit a patterned back-gate stack of Cu/Au, then perform atomic layer deposition of Al₂O₃ at 130 °C. We transfer monolayer WS₂ grown by hybrid metal-organic chemical vapor deposition (MOCVD) on sapphire onto the PEN substrates using a polymer-assisted process [3], [4]. For contacts, we pattern and deposit Ni/Au using e-beam evaporation. Lastly, for the top-gate stack, we use an Al seed layer followed by ALD Al₂O₃, and the Au/Cu/Au metal gate.

We measured 32 dual-gated devices on the PEN substrate with a Keithley 4200 semiconductor parameter analyzer in air. Our dual-gate devices show a maximum drain current between 3 and 23 µA/µm at V_DS = 1 V and V_BG,S = V_TG,S = 5 V. Our best device, with channel width W = 20 µm and channel length L = 2 µm, reaches a maximum drain current of 17.3 µA/µm at V_DS = 1 V and V_BG,S = V_TG,S = 5 V, a maximum transconductance of 4.85 μS/μm, and a maximum output current of 37.7 µA/µm at V_DS = V_BG,S = V_TG,S = 5 V. In the subthreshold region, we achieve a minimum subthreshold slope of 200 mV/decade and hysteresis of 0.64 V at a threshold current of 100 nA/µm. By sweeping the back-gate and top-gate separately, we observe a larger threshold voltage shift when sweeping the top-gate at fixed back-gate voltage compared to sweeping the back-gate at fixed top-gate voltage. We attribute this effect to contact gating of the back-gate during the top-gate sweep, causing a different threshold voltage in the contacts.

For inverters, we pattern and etch vias through the oxide layers with plasma reactive ion etching, filling them with 60 nm evaporated Au to form a unipolar NMOS depletion-load circuit. In our topology, the load inverter is a dual-gate device, whereas the drive inverter is a top-gate device. This enables the inverter to be controlled by shifting the load transistor from depletion to enhancement mode. Our inverters show switching behavior at V_TG = -4 V, with a maximum DC gain of 3 V/V. The switching voltage increased by 1.5 V as V_BG increased from 0 V to 6 V, while the DC gain remained stable. The V_TG dependence on V_BG indicates our ability to operate the inverter in either a high-gain state or an always-off state, as desired.

This work represents the first report of dual-gate monolayer WS₂ devices on flexible substrates, showcasing the utility of 2D materials in wearable electronics. Future work will focus on optimizing the device topology for inverter circuit performance, and investigating the effects of strain on these circuits. This work was supported in part by the ARCS Foundation (J.A.Y.) and by the Stanford SystemX Alliance (other authors).

[1] Y. Pang, et al., Small, 16, 1901124 (2020).
[2] J. A. Yang et al., ACS Nano, 18, 18151 (2024).
[3] Z. Zhang et al., ACS Nano, 18, 25414 (2024).
[4] S. Vaziri et al., Sci. Adv., 5, eaax1325 (2019).