Ferroelectric-Dielectric Superlattice Engineering Enabling Ultra-High-Density Capacitors for On-Chip Adaptive Voltage Conversion

High-density on-chip capacitors can transform the landscape of efficient power management for processor power delivery, size-constrained autonomous artificial intelligent systems, and high-performance edge computing units [1]. Superlattices based on HfO₂/ZrO₂ have recently been introduced for storing energy at a high density by utilizing the negative capacitance phenomenon [2]. However, realization of on-chip power converters requires materials design optimization aimed at improving efficiency, minimizing power losses, and increasing the overall system reliability.
Here, we report an ultrahigh capacitance density exceeding 50 fF/µm with a breakdown voltage of ~8 V. This is enabled by fine-tuning the Hf:Zr ratio in the HfO₂/ZrO₂ superlattice stack deposited in a trench shaped structure on metal bottom electrodes with a combined deposition approach using atomic layer deposition and magnetron sputtering. Grain size control using Al₂O₃ interlayers further ensures a balance between voltage handling capability and capacitance density. The interface between the bottom metal electrode and the superlattice stack was optimized to achieve lower contact resistance further minimizing power loss.
These results demonstrate the potential of engineering ferroelectric-dielectric superlattice materials and their interfaces towards enabling more efficient and reliable power electronics.

References:
[1] N. C. Brooks, J. Zou, S. Coday, T. Ge, N. M. Ellis and R. C. N. Pilawa-Podgurski, “On the Size and Weight of Passive Components: Scaling Trends for High-Density Power Converter Designs,” IEEE Transactions on Power Electronics, 39, 7, 8459-8477, (2024).
[2] Cheema, S.S., Shanker, N., Hsu, SL. et al. Giant energy storage and power density negative capacitance superlattices. Nature 629, 803–809 (2024).