Ultra-Low Saturation Voltage Source-Gated WS₂ Transistor with Self-Aligned Tunnel Contact

Conventional silicon-based semiconductor devices are reaching their scaling limits due to short-channel effects. To overcome these limitations, transition-metal dichalcogenides (TMDs) have emerged as promising alternatives to silicon. With their atomically thin structure and surfaces free of dangling bonds, field-effect transistors (FETs) based on TMDs demonstrate excellent electrical properties, including high field-effect mobility and excellent on/off ratio, making them promising candidates for next-generation devices.
As devices become miniaturized and integrated, the demand for low-power electronics has significantly grown. The key to minimizing power consumption is achieving a low saturation voltage, which is challenging in conventional FETs. Source-gated transistors (SGTs) have been developed to address these limitations by utilizing the Schottky barrier at the source contact, which lowers the saturation voltage compared to traditional FETs. While SGTs have shown significant progress with conventional semiconductors, integrating 2D TMDs into SGTs remains challenging due to Fermi-level pinning, which limits proper Schottky contact formation.
In this work, a WS₂-based tunnel contact source-gated transistor (TCSGT) was fabricated using a self-aligned deposition process. A high-work function metal, Ni/Au, was used for the source electrode to induce a Schottky contact, resulting in a pinch-off near the source region. In addition, inserting a thin dielectric layer between the electrode and channel in our TCSGT mitigates Fermi-level pinning, facilitating the formation of an optimal Schottky barrier at the source contact. This design enables source-controlled operation, further reducing the saturation voltage and lowering power consumption compared to conventional FETs. This dielectric layer also passivates the channel, protecting it from external impurities and enhancing device stability.
For the fabrication process, WS₂ flakes were mechanically exfoliated and dry-transferred onto a Si/SiO₂ substrate, followed by a 1 nm Al₂O₃ dielectric layer deposition using atomic layer deposition (ALD). A T-shaped source electrode was then defined using electron beam lithography (EBL) with electron beam resists of different sensitivities, followed by Ni/Au (50/100 nm) deposition. Ti/Au (20/30 nm) drain electrodes were deposited using the T-shaped electrode as a mask, avoiding the need for additional lithography steps. The structure and precise formation of the T-shaped electrode were confirmed using scanning electron microscopy (SEM) and cross-sectional transmission electron microscopy (TEM).
In our WS₂ TCSGT, the channel is defined by the separation between the head and foot of the T-shaped electrode, with its length (L_ch) controllable down to 150 nm by adjusting the head-to-foot ratio. This unique structural design simplifies device fabrication across various channel lengths and enables the production of highly integrated, low-power devices. Our WS₂ TCSGT showed a significant reduction in saturation voltage (V_SAT), down to 0.2 V, and minimized power consumption to as low as 0.6 μW. The resulting TCSGT device demonstrates significant potential for developing low-power electronics based on 2D semiconductor materials.