Oxide-Oxide Vertically Aligned Nanocomposite Memristor as High-Performance Electronic Synapses via Interface Engineering

With the ongoing surge in demand for computing power driven by machine learning (ML) and artificial intelligence (AI), modern computers based on the von Neumann architecture are facing significant challenges related to power consumption, latency, limited parallelism and the constraints of Moore’s law, despite their success in general computing. To meet the growing demand for computing power, neuromorphic computing architecture, inspired by the human brain, has emerged as a promising alternative. It offers higher power efficiency, lower latency, and inherent parallel processing, making it well-suited for ML and AI. Unlike the von Neumann architecture, a typical neuromorphic computing architecture integrates its processing unit with the memory unit, similar to biological neurons and synapses, where each neuron can be connected to more than 1000 other neurons through synapses. A key challenge in realizing neuromorphic computing systems lies in developing scalable electronic synapses that can operate with low power consumption, exhibit high reliability, and show minimal device-to-device variation, while also demonstrating the plasticity required to mimic the learning and forgetting processes of the human brain. Oxide-based memristors have attracted considerable research interest due to their resistive switching properties, promising device plasticity and compatibility with existing CMOS technologies, making them promising candidates for electronic synapses in neuromorphic computing systems. However, challenges remain in implementing and scaling memristor-based neuromorphic computing systems due to limitations including poor device reliability, severe device-to-device variation, and relatively high set/reset voltage. Recent advances in oxide-oxide vertically aligned nanocomposite (VAN) memristors offer a potential solution by using vertical interfaces as vertical channels to facilitate oxygen vacancy () migration and leveraging strain along interfaces to tune the activation energy E_a. In this study, a novel SrTiO₃-CeO₂ (S-C) VAN memristor was successfully demonstrated. The interface density and strain along interfaces were successfully tuned by varying the deposition parameters. The effect of interface density and strain on device performance was systematically explored. Microstructural analysis, including X-ray diffraction (XRD), transmission electron microscopy (TEM) and atomic force microscopy (AFM), confirmed the VAN structure of the device. Device performance, including set/reset voltage, device reliability, device-to-device variation, were evaluated through a series of electrical characterizations using a semiconductor analyzer. The results show that devices with higher interface density and tensile strain exhibited improved power efficiency (up to 50% reduction in set/reset voltage), superior device reliability (endurance of up to 10¹⁰ cycles and retention of 10⁴ seconds), and reduced device-to-device variation. The switching mechanism of the S-C memristor was thoroughly investigated using COMSOL simulation, which provides a deep understanding of the underlying physics. Additionally, the device plasticity of the S-C VAN memristor was evaluated through long-term-potentiation/depression (LTP/LTD), paired-pulse-facilitation (PPF), and spike-time-dependent-plasticity (STDP). The results indicated excellent linearity in the conductance change of S-C VAN memristor, with a linearity of 0.93 for LTP and 0.99 for LTD, positioning the S-C VAN memristor as a promising candidate for electronic synapses. Finally, the spiking neural network (SNN) built on the S-C VAN memristor achieved a high recognition rate (~94%) on the MNIST dataset after training, highlighting its potential for large-scale neuromorphic chips.