Self-Aligned Fabrication of Sub-50 nm Top Gate Coplanar ITO/IGZO Thin-Film Transistors without Nanoscale Patterning

Amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) are attracting interest due to their wide bandgap, low leakage, and capacity for low-temperature processing and have been effectively commercialized particularly in display backplane applications. One significant approach to improving the TFT’s performance involves reducing the channel length to sub-micron levels. However, to fabricate nanoscale TFTs for large-scale display applications, traditional nanoscale pattern definition methods may not be applied and require the development of methods that would produce nanoscale patterns without nanolithography. We introduce a high-throughput nanoscale patterning method for fabricating top gate coplanar oxide semiconductor TFTs. Our method involves the angled thermal evaporation of an aluminum etch mask layer, taking advantage of shadowing effects induced by SiO₂ stepped spacers. First, the active channel layer, an ITO/IGZO bilayer, was sputter deposited. Then a 50 nm Mo contact metal layer was sputter deposited. Normally at this stage, a nanogap in the Mo would be introduced by nanolithography followed by reactive ion etching (RIE). However, our method defines a nanogap in the etch mask by Al angled deposition. A layer of SiO₂ is deposited on the Mo layer and an optical lithography step is used to mark the position of the SiO₂ step that will be formed by RIE down to the Mo surface. When Al is thermally evaporated at an angle on the SiO₂ step, the shadowing effect will introduce a nanogap between the Al on top of the SiO₂ step and on top of the Mo layer. Using the discontinuous Al layer as the hard mask, sub 100 nm gap in the Mo layer can be inserted by RIE, thereby forming a nanogap between the source/drain contacts. After the Al layer is removed chemically, the Al₂O₃ gate insulator and Mo top gate layers were self-aligned to the nanogap position by ALD and sputtering, respectively. By controlling the Al deposition angle and the SiO₂ step height, the nanogap width was controlled between 40 nm ~ 100 nm. Utilizing this technique, we successfully fabricated a top gate coplanar ITO/IGZO TFT with a gate length of 50 nm. Measurements showed that at a drain-source voltage of 40 mV, the device exhibited an on current of 1.3 × 10^-6 A/µm at a gate voltage of 20 V. And the off-current levels were below 10^-14 A/cm² with a threshold voltage of -2.1 V, and a sub-threshold swing of 301 mV. The results demonstrate that this technique has the potential for broad application in large-scale nanoscale metal oxide TFT fabrication.