Towards CMOS-Integrated Graphene Hall Sensor Arrays with Individually Tunable Elements for High Sensitivity and Enhanced Uniformity

Graphene Hall-effect sensors exhibit high performance comparable to state-of-the-art devices made from III-V semiconductors, with the added advantage of CMOS-compatible fabrication. These properties make graphene Hall sensors (GHSs) an attractive choice for implementing high-density magnetic sensing arrays for imaging and biosensing applications. [1] The size and effectiveness of GHS arrays are presently limited by a) low uniformity across the array arising from variable doping and fabrication mismatch, and b) the increasing need for co-integrated GHS control and readout electronics as the array size is upscaled. In this work we present and validate strategies to address both challenges, achieving progress towards large-scale GHS arrays.<br/>We first studied the effectiveness of per-device tuning to improve response uniformity between graphene Hall elements. The conventional technique of varying the substrate voltage to tune all devices simultaneously has been shown to improve uniformity, at the expense of overall sensitivity. [2] We hypothesized that individual GHS tuning would greatly relax the tradeoff. An array of 16 GHSs was fabricated on a silicon chip, with an insulated backgate terminal underneath the active region of each sensor (10 mm x 10 mm). 10 nm HfO₂ was chosen as the insulation dielectric to enhance tuning efficacy. A CMOS-compatible voltage range of 5 V was sufficient to access all relevant regions of device operation, including the Dirac point and the maximum sensitivities in the electron and hole regimes. Characterization of multiple devices on the same chip showed non-uniformity in the optimal operating point of each GHS, arising from variations in doping across the chip. Individual backgate tuning was then used to align the responses of the sensors. The post-tuning results confirmed our hypothesis, as individual tuning improved the Hall sensitivity coefficient of variation (CV) by up to 95% compared to the scenario where all sensors shared the same backgate, with a small degradation to sensitivity (9.5%). The best-performing GHS array in our study achieved an average response of 1.17 kΩ/T with a CV of 3.4%.<br/>We then developed techniques to monolithically integrate a GHS array within the back-end-of-line (BEOL) layers of a custom CMOS chip (designed in a 180nm foundry process) for scalable sensor control and readout. Two key challenges in graphene-CMOS BEOL integration are a) surface roughness on the uppermost layers of the chip leading to graphene tears b) surface oxidation on BEOL metals leading to non-ohmic device contacts. [3-4] To circumvent these issues, the entire sensing region of the 1.6mm x 1.2mm chip was covered with a top-metal fill in the design, with a foundry layer added to remove passivation over the top-metal fill. Sensor terminals were defined by instantiating tungsten vias between the top fill and the underlying metal layer. During post-processing, the top-metal fill was removed using a wet etch, leaving behind a planarized surface with exposed oxide-free sensor terminals. After insulating the backgate terminal, CVD-grown graphene was transferred onto the CMOS chip surface and patterned into Hall crosses at the predefined sensing sites. SEM, AFM, and Raman analysis were used to confirm successful patterning of high-quality monolayer graphene. Electrical measurements of 32 sites within the sensing surface were performed through on-chip multiplexing and indicated high yield (75%) with a measured sensitivity of 480 Ω/T. Ongoing measurements using on-chip circuitry for backgate tuning and lock-in detection of the Hall signal will also be discussed.<br/>References:<br/>[1] Collomb et al., <i>J. Phys. Cond.Matt. </i>(2021)<br/>[2] Chen et al., <i>Carbon </i>(2015)<br/>[3] Dai et al., <i>ACS Nano </i>(2020)<br/>[4] Mortazavi Zanjani et al., <i>npj 2DM</i> (2017)