April 22 - 26, 2024
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May 7 - 9, 2024 (Virtual)
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2024 MRS Spring Meeting & Exhibit
EL04.01.07

Effect of High-k Oxide Materials on Amorphous Indium Gallium Zinc Oxide (α-IGZO) Channel in Top Gate Field Effect Transistors

When and Where

Apr 22, 2024
3:15pm - 3:30pm
Room 345, Level 3, Summit

Presenter(s)

Co-Author(s)

Reem Alshanbari1,Oliver Durnan1,Huaiqian Guo1,Moshe Eizenberg2,Ioannis Kymissis1

Columbia University1,Technion–Israel Institute of Technology2

Abstract

Reem Alshanbari1,Oliver Durnan1,Huaiqian Guo1,Moshe Eizenberg2,Ioannis Kymissis1

Columbia University1,Technion–Israel Institute of Technology2
The gate dielectric material plays a significant role in high-speed transistor operation and low power consumption in field-effect transistors (FETs). A small conduction band offset energy and a large interface trap density are common problems with high-<i>k</i> dielectrics with high permittivity. For that, in this work, the integration of high-<i>k </i>dielectrics with PECVD dielectrics has been reported to show improvements in electrical performance. Here, we integrated a high-<i>k</i> dielectric with (~10 nm) amorphous indium gallium zinc oxide (<i>α</i>-IGZO) FET with different gate dielectrics PECVD (SiO<sub>2</sub> and Si<sub>3</sub>N<sub>4</sub>). In addition, using a high-<i>k</i> dielectric can help overcome the problem of plasma contamination and diffusion, which can impact the device's threshold voltage and power consumption. For that, we use two of the most promising high-<i>k </i>dielectrics (HfO<sub>2</sub> and Al<sub>2</sub>O<sub>3</sub>). Our results showed that <i>α</i>-IGZO with optimized HfO<sub>2</sub>/SiO<sub>2 </sub>dielectrics has a superior electrical performance with high-field effect mobility (50 cm<sup>2</sup> V<sup>-1</sup>s<sup>-1</sup>) and an on-current of 10<sup>-6</sup> A, and the value of the off-current was 10<sup>-13</sup> A under 0.1 V<sub>DS</sub> without any dielectric leakage. These results support the idea that increasing the gate capacitance density will improve the electrical performance and material conductivity. Integrating HfO<sub>2</sub> with SiO<sub>2</sub> improves the interface quality between the gate dielectric/channel and reduces the charge trap density and gate leakage. In contrast, there is a degradation in the electrical performance of <i>α</i>-IGZO FETs with Al<sub>2</sub>O<sub>3</sub>/SiO<sub>2</sub>, related to the oxygen diffusion where more oxygen atoms diffuse from Al<sub>2</sub>O<sub>3</sub> to the <i>α</i>-IGZO layer.

Symposium Organizers

Hideki Hirayama, RIKEN
Robert Kaplar, Sandia National Laboratories
Sriram Krishnamoorthy, University of California, Santa Barbara
Matteo Meneghini, University of Padova

Symposium Support

Silver
Taiyo Nippon Sanso

Session Chairs

Robert Kaplar
Sriram Krishnamoorthy

In this Session