Impact of Interface Chemistry and Crystalline Defects on The Reliability of 4H-SiC MOSFETs

The growing silicon carbide (4H-SiC) device demand in applications with high reliability constrains (i.e. automotive etc) imposes the scientific community to acquire a deeper comprehension of the physical phenomena affecting the device integrity under prolonged stress, with a particular focus on the impact of the crystalline defects in the semiconductor epitaxial layer. However, threshold voltage (V_th) instability phenomena and poor field effect channel mobility (µ_FE) are still observed in 4H-SiC MOSFETs, and can be only partially mitigated by post-oxidation (POA) or post-oxide deposition annealing (PDA) processes.<br/>In this context, in this invited talk, some reliability concerns affecting the performances of 4H-SiC MOSFETs are discussed. In particular, the following aspects will be addressed: the SiO₂/SiC interface chemistry and the impact of the device fabrication processes on the MOSFET threshold voltage (V_th) stability, and the impact of the semiconductor crystalline defect on the device lifetime.<br/>4H-SiC MOSFETs were characterized by means of current voltage (I_D-V_G) transfer characteristics and capacitance–voltage (C-V) measurements. Furthermore, on selected failed devices, Scanning Transmission Electron Microscopy (STEM) analyses combined to electron energy loss spectroscopy (EELS), and electrical Scanning Probe Microscopy (SPM) analyses have been used to elucidate the physical mechanisms affecting their reliability.<br/>An important aspect is related the breakdown of 4H-SiC MOSFETs correlated to the presence of different crystalline defects in the 4H-SiC epitaxial layer. Of particular interest are the wafer level characterization of both the failed devices at t=0s, and of the devices showing an anomalous Fowler-Nordheim (FN) gate bias conduction. In fact, it is possible to correlate devices failing under high temperature gate bias (HTGB) stress with the presence of an anomalous FN behavior and the presence of a surface bump on the semiconductor. Moreover, the role of the threading dislocation (TD) in high temperature reverse bias (HTRB) failures was demonstrated employing high-resolution SPM techniques. These nanoscale methods elucidated the physical mechanism of the dielectric breakdown, revealing an increase of the minority carrier concentration close the insulator/semiconductor interface.Furthermore, a method to monitor the V_th variation from single point drain current (I_D) measurement using a single gate bias (V_read) value is presented. This method allowed to probe the interface states close to the 4H-SiC conduction and valence band edges and the amount of trapped charge at the interface close to 4H-SiC band edges (N_it) an inside the near interface oxide region (NIOTs).<br/>These finding demonstrated that the threshold voltage instability of 4H-SiC MOSFETs, associated to different trapping mechanisms, is directly related to the SiO₂/SiC interface chemistry and can be mitigated by an accurate control of the nitridation conditions of deposited oxides.<br/> <br/>[1] P Fiorenza, F. Giannazzo, S. Cascino, M. Saggio, F. Roccaforte. Appl. Phys. Lett. 117, 103502 (2020)<br/>[2] P. Fiorenza, C. Bongiorno, F. Giannazzo, M. S. Alessandrino, A. Messina, M. Saggio, F. Roccaforte; Appl. Surf. Sci. 557 149752 (2021)<br/>[3] P. Fiorenza, M S Alessandrino, B Carbone, C Di Martino, A Russo, M Saggio, C Venuto, E Zanetti, F Giannazzo, F Roccaforte Nanotechnology 31 (2020) 125203<br/>[4] P. Fiorenza, S. Adamo, M. S. Alessandrino, C. Bottari, B. Carbone, C. Di Martino, A. Russo, M. Saggio, C. Venuto, E. Vitanza, E. Zanetti, F. Giannazzo, F. Roccaforte, IEEE IRPS (2021)<br/>[5] P. Fiorenza, M. Zignale, M. Camalleri, L. Scalia, E. Zanetti, M. Saggio, F. Giannazzo, F. Roccaforte Mater. Sci. Semicon. Proc.169 (2024) 107866