Apr 24, 2024
8:00am - 8:30am
Room 344, Level 3, Summit
Jeehwan Kim1
Massachusetts Institute of Technology1
The integration of electronics in three dimensions has gained significance in modern electronics due to limitations in scaling nanoscale devices. Vertical chip stacking reduces RC delays, leading to lower power consumption and more efficient data exchange in system-on-chip designs. Despite huge technical challenges, through-silicon-via (TSV) has been an only viable solution. A more concise and effective approach for connecting electronic devices is wafer-free monolithic 3D (M3D) integration. However, the scarcity of methods for locating single-crystalline thin film device layers at low temperatures has limited experimental demonstrations of M3D with single-crystalline devices. We now present our pioneering demonstration of single-crystal growth of TMD channel materials at 350°C on an amorphous layer-coated silicon wafer. This breakthrough allows seamless integration of single-crystalline n-type MOS devices on top of amorphous insulation layers of underlying single-crystalline p-type MOS chips. Our work establishes a foundation for advancing Moore's law. Furthermore, successfully growing single-crystalline devices on finished circuitry holds the promise of true wafer-free vertical monolithic integration of electronics and photonics in the future.