High Thermal Stability of Negative Capacitance HfO₂-ZrO₂ Superlattice Gate Stack Towards Improved Reliability and Work Function Engineering

Negative capacitance (NC) [1] gate oxides have emerged as a new route towards energy-efficient transistors as it can increase the gate capacitance, i.e. lower equivalent oxide thickness (EOT), which reduces the operating voltage and therefore power. We have previously demonstrated a 1.8 nm ferroelectric-antiferroelectric HfO₂-ZrO₂ superlattice (HZH) gate stack boasting a capacitance enhancement over the 8 Å SiO₂ IL layer via the NC effect [2]. Furthermore, once the HZH gate stack was integrated into 90 nm <i>L_g</i> silicon-on-insulator (SOI) nMOS transistors, gate leakage, electron mobility, and the PBTI reliability were unchanged relative to a conventional high-κ dielectric HfO₂ gate stack [2,3].<br/>In this work, we investigate the thermal stability of the NC HZH gate stack at high temperatures. In particular, in advanced transistor processing, the gate oxide is subjected to several high temperature (&gt;900°C) rapid thermal anneals in order to, for example, diffuse metal dopants (e.g. La) to adjust the effective work function, generate oxygen vacancies in the high-κ layer to lower effective work function, and improve device reliability [4,5]. After the NC HZH gate stack capped with TiN/amorphous silicon was subjected to high temperature rapid thermal anneals, we observe the EOT is unchanged before and after the high-temperature anneal, suggesting that the mixed ferroelectric-antiferroelectric structure is unaffected by the high temperature anneal and the interfacial SiO₂ did not increase in thickness. Additionally, a corresponding decrease in effective work function, consistent with prior work with high-κ HfO₂[5], is observed, likely due to the generation of oxygen vacancies.<br/>Overall, this work confirms the high-thermal stability of the NC HfO₂-ZrO₂ superlattice gate stack and that conventional high-κ work function tuning and reliability enhancement strategies are also compatible with the NC HZH superlattice gate stack. This takes a key step towards the integration of NC HZH superlattice gate stack in advanced transistors in semiconductor foundries.<br/>[1] S Salahuddin & S Datta. “Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices." <i>Nano Lett</i>. 8, 405–410<br/>[2] S Cheema <i>et al</i>. “Ultrathin ferroic HfO₂–ZrO₂ superlattice gate stack for advanced transistors.” <i>Nature </i>604, 65 (2022).<br/>[3] N Shanker <i>et al.</i> “On the PBTI Reliability of Low EOT Negative Capacitance 1.8 nm HfO₂-ZrO₂ Superlattice Gate Stack on L_g =90 nm nFETs.” in <i>2022 IEEE Symposium on VLSI Technology and Circuits</i> (IEEE, 2022).<br/>[4] H. Arimura <i>et al.</i> "Dipole-First Gate Stack as a Scalable and Thermal Budget Flexible Multi-Vt Solution for Nanosheet/CFET Devices." <i>2021 IEEE International Electron Devices Meeting</i> (IEDM, 2021)<br/>[5] T Ando <i>et al.</i> "Simple Gate Metal Anneal (SIGMA) stack for FinFET Replacement Metal Gate toward 14nm and beyond." in <i>2014 IEEE Symposium on VLSI Technology and Circuits</i> (IEEE, 2014)