April 22 - 26, 2024
Seattle, Washington
May 7 - 9, 2024 (Virtual)

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2024 MRS Spring Meeting
EL04.02.04

pn GaN Regrowth Vertical Diodes Displaying Ten Orders of Magnitude Memory Window

When and Where

Apr 23, 2024
11:45am - 12:00pm
Room 345, Level 3, Summit

Presenter(s)

Co-Author(s)

Sujitra Pookpanratana1,Stephen Moxim1,Ory Maimon2,1,Behrang Hamadani1,Wei-Chang David Yang1,Andrew Winchester1,Emily Bittle1,Qiliang Li2,1,Albert Davydov1,Travis Anderson3,Jennifer Hite3,Jason Campbell1,Jason Ryan1

NIST1,George Mason University2,U.S. Naval Research Laboratory3

Abstract

Sujitra Pookpanratana1,Stephen Moxim1,Ory Maimon2,1,Behrang Hamadani1,Wei-Chang David Yang1,Andrew Winchester1,Emily Bittle1,Qiliang Li2,1,Albert Davydov1,Travis Anderson3,Jennifer Hite3,Jason Campbell1,Jason Ryan1

NIST1,George Mason University2,U.S. Naval Research Laboratory3
The large bandgap of GaN enable advancements in power electronics. pn GaN vertical diodes offer improved efficiency, size, and performance over traditional Si-based power devices making them essential components for next generation power electronic systems. pn GaN diode fabrication typically requires regrowth of the p-GaN layer, which is known to introduce Si impurities at the pn GaN interface.<sup>1-3</sup> While this does impact the performance of power devices,<sup>2, 4, 5</sup> the presence of impurities at the regrowth interface has also been shown to display memristor behavior.<sup>6</sup> Memristor-like behavior in GaN and other nitride device structures has also been reported.<sup>7-9</sup> It is appealing to develop GaN-based memory technologies which could be integrated with GaN high electron mobility transistors. Here, we find that regrown pn vertical diodes display an exceptionally large memory-like hysteresis loop exceeding a previous report.<sup>6 </sup><br><br/>The pn diodes were fabricated on dot-core GaN substrates. For the regrowth diode, a 5 μm unintentionally-doped drift layer (n between 8E15 and 2E16 cm<sup>-3</sup>) was first deposited, followed by ex-situ 400 nm p-layer (N<sub>A</sub> ≈ 4E17 cm<sup>-3</sup>). For the in-situ grown diode or “control,” a 8 μm drift layer (n ≈ 1.7E16 cm<sup>-3</sup>) was first deposited, and subsequently followed by 400 nm p-layer (N<sub>A</sub> ≈ 4 E17 cm<sup>-3</sup>). Metallization were identical on both sets of devices with Pd/Pt/Au on the p-GaN and Ti/Al/Ni/Au on the GaN substrate.<br><br/>The regrowth pn diode displayed memory or hysteresis effect at forward bias with 10 orders of magnitude larger on-state current (I<sub>ON</sub>) than the off-state current (I<sub>OFF</sub>), while the “control” pn GaN vertical diodes with an <i>in-situ</i> grown interface, display no such hysteresis effect. We find that the memory endurance and retention characteristics are robust, with no appreciable degradation in I<sub>ON</sub>/I<sub>OFF</sub> ratio after 60k set-reset cycles. To evaluate these devices for potential use as a high temperature memory element, the presence of a reduced switching window was confirmed at temperatures up to 275 °C. To investigate the electronic differences of these two diode structures, electroluminescence (EL) measurements before and after endurance cycling were performed. While the control sample is clearly dominated almost entirely by a single spectral peak at about 3.25 eV (likely a conduction band to Mg acceptor transition), the memory-like devices have three additional strong spectral peaks whose relative contributions evolve with cycling. These three extra peaks are located at 3.1 eV (V<sub>N</sub> to Mg acceptor), 2.9 eV (blue luminescence, BL), and 2.3 eV (yellow luminescence, YL). With increasing cycles, the 3.1 eV peak increases in relative contribution while the BL and YL features decrease. We speculate that the BL and YL defects are not critical to the memory effect. TCAD simulations of both the memory and control devices were performed, and the simulated IV characteristics of the control devices agreed with the measured electrical data. The structure of the memory devices for TCAD modelling is currently in development with transmission electron microscopy analysis to identify the regrowth pn GaN interface. We plan to propose a model on the origin of the memristor-like behavior in ex-situ formed pn GaN diodes.<br><br/> <br/>1. K. Fu, et al., Applied Physics Letters <b>113</b> (23) (2018).<br/>2. K. Fu, et al., Applied Physics Letters <b>118</b> (22) (2021).<br/>3. M. Noshin, et al., Semiconductor Science and Technology <b>37</b> (7), 075018 (2022).<br/>4. G. W. Pickrell, et al., Journal of Applied Physics <b>126</b> (14) (2019).<br/>5. K. Fu, et al, IEEE Journal of the Electron Devices Society <b>8</b>, 74-83 (2020).<br/>6. K. Fu, et al, IEEE Electron Device Letters <b>40</b> (3), 375-378 (2019).<br/>7. J. L. Gomes, et al, physica status solidi (b) <b>256</b> (5), 1800387 (2019).<br/>8. T. Chen, et al, IEEE Electron Device Letters <b>43</b> (5), 697-700 (2022).<br/>9. H. Sánchez-Martín, et al, Applied Physics Letters <b>123</b> (10) (2023).

Keywords

electrical properties | nitride

Symposium Organizers

Hideki Hirayama, RIKEN
Robert Kaplar, Sandia National Laboratories
Sriram Krishnamoorthy, University of California, Santa Barbara
Matteo Meneghini, University of Padova

Symposium Support

Silver
Taiyo Nippon Sanso

Session Chairs

Sriram Krishnamoorthy
Jingyu Lin

In this Session