Modulation of Synaptic Functions via Charge Trap Layer in Oxide Semiconductor-Based Synaptic Transistor by Light Irradiation

Due to advancements in artificial intelligence (AI) technologies, such as machine learning, deep learning, and computer vision, computing systems are increasingly required to manage vast amounts of data storage and fast computational processing. However, current computing systems face limitations such as the bottleneck phenomenon associated with von Neumann architecture. To address these limitations, artificial synaptic transistors have emerged, emulating the intricate neural systems of humans, enabling them to store vast amounts of data while maintaining high-speed operation with low power consumption in computing systems. Nonetheless, as computing systems progressively demand enhanced learning capabilities in various environments of data, a necessity arises to distinguish the simple and complicated tasks by adjusting the modification of their synaptic properties as desired. Among the diverse research of synaptic transistors, oxide semiconductor-based synaptic transistors have attained prominence due to their relatively low off current, which contributes to low power consumption.<br/>In this study, we propose a synaptic weight modulation layer (SML) in oxide semiconductor-based synaptic transistors by adjusting the quantity of charge trapping depending on the light irradiation. SML is comprised of ultra-violet (UV)-treated hafnium oxide (HfO_x), which generates varying amounts of oxygen vacancy (V_o) sites, acting as charge trap sites, simply by modifying the UV lamp (wavelength of 184.9 nm & 253.7 nm) exposure time. The devices are based on indium-gallium-zinc oxide (IGZO) thin film transistor (TFT) with two types of SMLs: low-synaptic weight modulation layer (L-SML) with 10 min UV-treated HfO_x and high-synaptic weight modulation layer (H-SML) with 1-hour UV-treated HfO_x located between the channel of a-IGZO and thermally grown silicon dioxide (SiO₂) from a heavily boron-doped p-type silicon substrate (p+-Si).<br/>The hysteresis characteristics are measured to confirm the charge trapping phenomenon by threshold voltage shift (ΔV_th). IGZO TFT w/ L-SML and IGZO TFT w/ H-SML showed the ΔV_th of 5.15 V, and 10.10 V respectively. This result implies that the increment of ΔV_th is clearly influenced by UV treatment time, which occurs by the difference in charge trap density. To verify the UV effect on the HfO_x dielectric film, the current density versus electric field (J-E) curve is obtained in metal-insulator-metal (MIM) capacitors. The HfO_x dielectric film shows a dielectric strength of 10.13 MV/cm, L-SML shows 8.88 MV/cm and H-SML shows 7.35 MV/cm. The breakdown electric field decreases while UV exposure time increases. This phenomenon is expected by bond dissociation and X-ray photoelectron spectroscopy (XPS) analysis is performed to investigate the difference of chemical bonds in the HfO_x between L-SML and H-SML.<br/>In general, the inhibitory post-synaptic current (IPSC) was measured to verify the synaptic characteristics of IGZO w/L-SML and IGZO w/H-SML-based synaptic transistors. These devices showed different synaptic characteristics through the ratio of post-synaptic current/pre-synaptic current in different pulse amplitudes. At 5 V, 6 V, and 7 V, the IGZO TFT w/H-SML ratios are 43.7%, 58.0%, and 75.0%, respectively, compared to the IGZO TFT w/L-SML ratios of 19.7%, 32.6%, and 49.8%. Additionally, potentiation and depression characteristics of IGZO TFT w/L-SML and IGZO TFT w/H-SML according to 128 consecutive pulses are measured to verify the difference in learning capability. The post-synaptic current (PSC) change in IGZO TFT with L-SML and H-SML exhibits a remarkable difference, with an increase from approximately 140 nA to 323 nA (2.3-fold) and 18 nA to 117 nA (6.5-fold), respectively. As a result, it was confirmed that the different characteristics of synaptic transistors via simple light irradiation method might be a candidate for enhancing the learning capability and computational efficiency of neural computing.