Apr 24, 2024
9:00am - 9:15am
Room 344, Level 3, Summit
Muhammed Juvaid Mangattuchali1,Hao Tan1,Hippolyte Astier1,Chandan Das2,John Sudijono2,Silvija Gradecak1
NUS Singapore1,Applied Materials, Inc.2
Muhammed Juvaid Mangattuchali1,Hao Tan1,Hippolyte Astier1,Chandan Das2,John Sudijono2,Silvija Gradecak1
NUS Singapore1,Applied Materials, Inc.2
The progressive miniaturization of silicon integrated circuits necessitates the exploration of alternative materials for both the front-end-of-line (FEOL, transistors) and back-end-of-line (BEOL, interconnects) circuitry. Currently, the efficacy of traditional liners and barriers (e.g., Ta/TaN) requires an approximate thickness of 30-40 Å. In forthcoming sub-5 nm nodes, these components will occupy a significant portion of the interconnect cross-section, leading to a substantial increase in the resistivity of Cu interconnects. Conversely, the reduction in thickness of liner and barrier layers would result in a decrease in Cu blocking efficiency. Two-dimensional (2D) transition metal dichalcogenides (TMDs) were recently demonstrated as promising candidates for bifunctional ultra-thin liner and diffusion barrier materials in the sub-nanometer-scales. However, the majority of 2D TMDs are synthesized <i>via</i> chemical vapor deposition processes at elevated temperatures (>800°C). This makes it difficult to use them in BEOL integration, where the temperature limit is 450°C. While plasma-assisted growth offers the potential to mitigate the high-temperature requirement, it also implies poor conformality in deposition, and the emergence of plasma-induced defects in the TMDs as limitations.<br/>Here, we present a thermal atomic layer deposition (ALD) approach that does not require plasma assistance to grow crystalline WS<sub>2</sub> at temperatures below 400°C, on dielectric materials, including low- k and SiO<sub>2</sub> substrates. This growth approach does not alter the stoichiometry of the low- k material and retains its k value, making it a suitable method for BEOL integration. The process results in layer-controlled, conformal (>95%) wafer-scale growth of WS<sub>2</sub> on 200 mm dielectric substrates. Furthermore, the single-layer WS<sub>2</sub> helps reduce Cu resistivity >70% compared to the reference low- k and SiO<sub>2</sub>/Si substrates. Thermal and electrical stress tests on the monolayer WS<sub>2</sub> film reveal a high blocking efficiency against both types of stress. This low- k -compatible ALD-grown monolayer WS<sub>2</sub> not only addresses the downscaling challenge but also serves as an efficient bifunctional (liner and barrier) layer grown using a directly industry-compatible process.