Investigation of Temperature-dependent Hysteresis and Interface Trap Density in E-Beam Evaporated NiO_x/β-Ga₂O₃ p-n Diodes

β-Ga₂O₃, an ultra-wide bandgap (UWBG) material with a bandgap of 4.9 eV and a high breakdown field of ~8 MV/cm, holds promise for power, optical, and RF electronics. However, due to the absence of p-type Ga₂O₃, most demonstrated devices have been unipolar. This limitation is attributed to the lack of shallow acceptors and the presence of holes trapped in localized polarons. To address this, p-NiO_x has been utilized to create p-n heterojunctions with β-Ga₂O₃, resulting in devices such as p-n diodes and junction barrier Schottky (JBS) diodes. While these devices exhibit desirable properties, they also exhibit charge trapping, hysteresis in forward and reverse bias, and induced interface states at the heterojunction. This study aims to comprehensively investigate the temperature-dependent hysteresis and interface trap density in NiO_x/β-Ga₂O₃ p-n diodes on (-201) Ga₂O₃ crystal orientations.<br/>The edge-defined film-fed grown β-Ga₂O₃ substrates were sourced from Novel Crystal Technology, Inc. (Japan) and had a n-type doping concentration of [Sn] = 5×10¹⁸ cm⁻³, with uniform thickness and polished front sides. Prior to device fabrication, substrate cleaning involved sequential treatments with acetone, isopropyl alcohol (IPA), and deionized (DI) water. Subsequently, electron beam (E-beam) evaporation was used to deposit Ti/Au (20/130 nm) back contacts, followed by rapid thermal annealing at 500 °C in an N₂ environment. Photolithography was employed to define circular areas of 300 µm in diameter for NiO_x and anode material deposition (Ni/Au, 20/130 nm). Layers of NiO_x (200 nm) were deposited using e-beam evaporation, and a liftoff process was executed to isolate individual devices. Post-fabrication, devices underwent annealing at 350 °C in an N₂ atmosphere for 1 minute to improve performance by reducing the number of interface states at the NiO_x/β-Ga₂O₃ heterojunction.<br/>Preliminary findings indicate hysteresis during forward and reverse bias, but none in C-V measurements. With increasing temperature, forward bias hysteresis decreases, while reverse bias hysteresis remains constant. The experiment covers a voltage range of +3 V to −10 V. Concurrently, capacitance-frequency measurements were conducted to evaluate trap density, which varied between 5×10¹¹ and 2×10¹¹ eV⁻¹cm⁻² as the temperature ranged from room temperature to 395 K. These results suggest that temperature-dependent interface trap states contribute to the observed hysteresis in the devices. Future investigations will extend to NiO_x/β-Ga₂O₃ devices on (010) crystal orientation. Previous studies have indicated distinct electronic properties between (-201) and (010) devices due to crystal anisotropy. This study will provide valuable insights into transport properties of NiO_x/β-Ga₂O₃ p-n diodes and pave the path for device optimization by reducing interface trap states.