Advancements in 2D Semiconductor CMOS: Length Scaling, Gate Dielectric, Doping Engineering and Machine Learning Co-Optimization

This research presents recent advancements in 2D Transition Metal Dichalcogenides (TMD) Ribbon Field-Effect Transistors (RibbonFETs) as potential successors to Silicon RibbonFETs. These advancements include the scalable fabrication of ultra-narrow TMD nanoribbons, as narrow as 30 nm, leading to an impressive on-current <i>I</i>_ON of approximately 700 µA/µm at <i>V</i>_DS= 1 V. The improved electrostatics and heat distribution contribute to a significant 40% enhancement in both on-state and off-state performance. In terms of dielectric interface engineering for monolayer MoS₂ (1L-MoS₂) FETs, the integration of a high-κ TaO_x interfacial layer reduces active interface trap states and acts as an effective doping layer. This results in a superior <i>I</i>_ON of 861 µA/µm at <i>V</i>_DS= 1.5 V and reduced contact resistance (<i>R</i>_C) of 230 Ω µm. Dual-gate (DG) FETs achieve subthreshold swing (<i>SS</i>) values of approximately 70 mV/dec. Despite its small bandgap, hexagonal boron nitride (hBN) serves as a passivation and crystalline interfacial layer, improving device reliability and achieving an ideal <i>SS</i> of 62 mV/dec. The study also addresses reliability concerns of 1L-MoS₂ FETs on thin high-κ HfO₂, indicating that optimized ALD processes can ensure notable stability. Furthermore, the study introduces a novel nitric oxide (NO) doping approach for monolayer tungsten diselenide (1L-WSe₂) transistors, addressing issues with high-resistive metal contact and threshold voltage. This molecular doping technique enables unipolar p-type transport and reduces Schottky barrier, resulting in a record-low <i>R</i>_C of 875 Ω µm, the highest transconductance (<i>g</i>_m) of 400 µS/µm, and the lowest <i>SS</i> of 90 mV/dec. Additionally, a hybrid p-doping strategy combining tungsten oxide (WO_x) charge transfer with NO molecular doping achieves record-high <i>I</i>_ON and <i>g</i>_m while maintaining intrinsic channel properties. To improve the performance of 2D transistors, we propose a design and process co-optimization framework using Machine Learning (ML), similar to conventional Design of Experiments (DOE) for process optimization. Overall, these findings highlight significant progress in 2D semiconductor CMOS transistors, with a focus on length scaling, gate dielectrics, innovative p-doping techniques, and Machine Learning Co-Optimization.