Short Top-Gate Length in 2D p-FETs achieved via Van der Waals Integration

The lack of high-performance p-type field effect transistors (p-FETs) is impeding the potential of 2D materials in upcoming CMOS technology. One potential solution to this challenge is the use of a top-gate (TG) structure with a p-doped spacer area.[1-3] However, designing and processing the device to create gate stacks presents significant obstacles in realizing ideal p-FETs and PMOS inverters. In this research, we propose a novel method for achieving high-performance lateral p⁺– p – p⁺ junction WSe₂ FETs with controlled TG length. Our approach involves the integration of self-aligned TG stacks through van der Waals (vdW) integration, followed by oxygen plasma doping in the contact spacer regions. Unlike traditional techniques, we demonstrate effective electrostatic control of 2D p-FETs by implementing the TG stacks. The use of self-aligned TG as a doping mask yields a high on-off current ratio of >10⁷, a small subthreshold swing (SS) of 98 mV dec^-1, and a nearly zero threshold voltage (V_th) in WSe₂ p-FETs. Scaling down the TG length to 300 nm results in a high on-state current of approximately 100 µA µm^-1, preserving on/off ratio of 10⁴. Additionally, we validate the effectiveness of our method by demonstrating a PMOS inverter with a remarkably low power consumption of ~4.5 nW.