Applications of Topological Semimetals for Post-Cu Interconnects

Conduction via the surface states in topological semimetals yields unconventional scaling behavior such that resistivity decreases with reduced device dimensions down to ~nm. This may provide a solution for the interconnect bottleneck in highly scaled integrated circuits. In the first half of the talk, we will present first-principles-based electrical transport calculations of a Si-CMOS compatible topological semimetal CoSi and a prototypical Weyl semimetal NbAs. We will summarize the simulation results of pristine films and films with point defects, line defects, or grain-boundaries. We will also report the contact resistance scaling between a topological semimetal and a conventional liner material.<br/><br/>In the second half of the talk, we will report detailed experimental studies of CoSi. We first present resistivity scaling data of both polycrystalline and highly textured thin films down to ~5nm. Our magneto-transport measurements reveal coexisting high-mobility surface carriers with low-mobility bulk carriers and their temperature dependence. Most notably, we observe that the room-temperature resistivity in nanoscale CoSi thin films can drop below the ideal bulk single-crystal limit. Last, we present the resistance scaling of wafer-scale CoSi nanowires, both polycrystalline and highly textured. Our proof-of-principle studies demonstrate the potential of topological semimetals as post-Cu interconnect conductors and lay out the key challenges to tackle next.<br/><br/><b>Acknowledgements </b><br/>We thank Teodor Todorov, Jean Jordan-Sweet, Lerato Takana and Yuri Suzuki for the technical support in materials characterization. We thank Pavlo Sukhachov, Arun Bansil, Tay-Rong Chang, Judy Cha, and Chris Hinkle for the illuminating discussions.