April 22 - 26, 2024
Seattle, Washington
May 7 - 9, 2024 (Virtual)

Event Supporters

2024 MRS Spring Meeting
QT07.11.04

Applications of Topological Semimetals for Post-Cu Interconnects

When and Where

Apr 25, 2024
2:15pm - 2:45pm
Room 448, Level 4, Summit

Presenter(s)

Co-Author(s)

Ching-Tzu Chen1,Hsin Lin2,Christian Lavoie1,Nicholas Lanzillo3,Guy Cohen1,Oki Gunawan1,John Bruley1,Peter Kerns1,Franco Stellari1,Nathan Marchack1,Vesna Stanic1,Utkarsh Bajpai3,Ion Garate4,Gengchiau Liang5,Yi-Hsin Tu6,Shang-Wei Lien6,Ravishankar Sundararaman7,Sushant Kumar7,3,Cheng-Yi Huang8,En-De Chu9,Jason Tran9,Peng Wei9,Asir Intisar Khan10

IBM T.J. Watson Research Ctr1,Academia Sinica2,IBM Research3,Université de Sherbrooke4,National Yang Ming Chiao Tung University5,National Cheng Kung University6,Rensselaer Polytechnic Institute7,Northeastern University8,University of California, Riverside9,Stanford University10

Abstract

Ching-Tzu Chen1,Hsin Lin2,Christian Lavoie1,Nicholas Lanzillo3,Guy Cohen1,Oki Gunawan1,John Bruley1,Peter Kerns1,Franco Stellari1,Nathan Marchack1,Vesna Stanic1,Utkarsh Bajpai3,Ion Garate4,Gengchiau Liang5,Yi-Hsin Tu6,Shang-Wei Lien6,Ravishankar Sundararaman7,Sushant Kumar7,3,Cheng-Yi Huang8,En-De Chu9,Jason Tran9,Peng Wei9,Asir Intisar Khan10

IBM T.J. Watson Research Ctr1,Academia Sinica2,IBM Research3,Université de Sherbrooke4,National Yang Ming Chiao Tung University5,National Cheng Kung University6,Rensselaer Polytechnic Institute7,Northeastern University8,University of California, Riverside9,Stanford University10
Conduction via the surface states in topological semimetals yields unconventional scaling behavior such that resistivity decreases with reduced device dimensions down to ~nm. This may provide a solution for the interconnect bottleneck in highly scaled integrated circuits. In the first half of the talk, we will present first-principles-based electrical transport calculations of a Si-CMOS compatible topological semimetal CoSi and a prototypical Weyl semimetal NbAs. We will summarize the simulation results of pristine films and films with point defects, line defects, or grain-boundaries. We will also report the contact resistance scaling between a topological semimetal and a conventional liner material.<br/><br/>In the second half of the talk, we will report detailed experimental studies of CoSi. We first present resistivity scaling data of both polycrystalline and highly textured thin films down to ~5nm. Our magneto-transport measurements reveal coexisting high-mobility surface carriers with low-mobility bulk carriers and their temperature dependence. Most notably, we observe that the room-temperature resistivity in nanoscale CoSi thin films can drop below the ideal bulk single-crystal limit. Last, we present the resistance scaling of wafer-scale CoSi nanowires, both polycrystalline and highly textured. Our proof-of-principle studies demonstrate the potential of topological semimetals as post-Cu interconnect conductors and lay out the key challenges to tackle next.<br/><br/><b>Acknowledgements </b><br/>We thank Teodor Todorov, Jean Jordan-Sweet, Lerato Takana and Yuri Suzuki for the technical support in materials characterization. We thank Pavlo Sukhachov, Arun Bansil, Tay-Rong Chang, Judy Cha, and Chris Hinkle for the illuminating discussions.

Keywords

electrical properties

Symposium Organizers

Rafal Kurleto, University of Colorado Boulder
Stephan Lany, National Renewable Energy Laboratory
Stephanie Law, The Pennsylvania State University
Hsin Lin, Academia Sinica

Session Chairs

Stephan Lany
Stephanie Law

In this Session