Apr 25, 2024
2:30pm - 2:45pm
Room 342, Level 3, Summit
Nirmaan Shanker1,Suraj Cheema1,Sayeef Salahuddin1,2
University of California, Berkeley1,Lawrence Berkeley National Laboratory2
Nirmaan Shanker1,Suraj Cheema1,Sayeef Salahuddin1,2
University of California, Berkeley1,Lawrence Berkeley National Laboratory2
With the exponentially increasing demand for high-performance computing, the energy efficiency of transistors must continue to improve [1]. In particular, negative capacitance (NC) [2] in ferroelectric materials has emerged as a route to increase the gate capacitance, i.e. lower equivalent oxide thickness (EOT), of a transistor which can reduce the operating voltage and therefore power. However, integration of NC gate oxides in advanced silicon transistors requires ferroelectric stabilization in the ultrathin (sub-2 nm) regime on silicon, which is a significant materials challenge for conventional ferroelectrics. To overcome this, we stabilized ferroelectricity on silicon down to 1 nm [3-4] and 0.5 nm [5] in doped HfO<sub>2</sub> and undoped ZrO<sub>2</sub>, respectively, which are the high-κ dielectrics used in today’s advanced logic and memory devices. Notably, these ultrathin ferroelectrics demonstrate signatures of ultrathin-enhanced polarization [3-5], in strong contrast to conventional perovskite oxide-based ferroelectrics.<br/><br/>Next, we leveraged the competing atomic-scale antiferroelectric-ferroelectric orders to design NC in 1.8-nm HfO<sub>2</sub>-ZrO<sub>2</sub> superlattices [6-8] and 1-nm ZrO<sub>2</sub><sub> </sub>[9], the thicknesses used in today’s advanced transistors and future node transistors, respectively. In contrast to the conventional ferroelectric-dielectric picture for NC stabilization, the microscopic origin of NC in these gate oxides is mixed antiferroelectric-ferroelectric order, which broadens the materials space for NC realization. Furthermore, this work establishes the first demonstrations of capacitance enhancement [6-9] in the technologically-relevant HfO<sub>2</sub>-ZrO<sub>2</sub> system, resulting in record-low EOT down to 5 Å [6-9]. Accordingly, when these NC gate oxides were integrated within transistors [6-9], due to the increase in gate capacitance without degradation in carrier velocity and reliability [6-7], record high ON current and transconductance was obtained at 90 nm channel lengths [8-9]. Additionally, there are early indications of industrial adoption as the 1.8-nm HfO<sub>2</sub>-ZrO<sub>2</sub> superlattice gate stack has successfully been integrated within a US Defense CMOS R&D Foundry [8] and an advanced FinFET transistor process in an industrial semiconductor foundry [10]. Overall, the materials breakthroughs in this work—ultrathin ferroelectricity and negative capacitance—in the simple CMOS-compatible HfO<sub>2</sub>-ZrO<sub>2</sub> material system provides a new route towards energy-efficient computing.<br/><br/>[1] S Datta <i>et al.</i> “Toward attojoule switching energy in logic transistors.” <i>Science</i> 378, 733 (2022).<br/>[2] S Salahuddin & S Datta. “Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices. <i>Nano Lett</i>. 8, 405–410<br/>[3] S Cheema, D Kwon, <u>N Shanker</u> <i>et al</i>. “Enhanced ferroelectricity in ultrathin films grown directly on silicon.” <i>Nature</i> 580, 478–482 (2020).<br/>[4] S Cheema*, <u>N Shanker*</u> <i>et al</i>. “One nanometer HfO2-based ferroelectric tunnel junctions on silicon.” <i>Adv. Electron. Mater.</i> 8, 2100499 (2022).<br/>[5] S Cheema*, <u>N Shanker*</u> <i>et al</i>. “Emergent ferroelectricity in subnanometer binary oxide films on silicon.” <i>Science</i> 376, 648–652 (2022).<br/>[6] S Cheema*, <u>N Shanker*</u> <i>et al</i>., “Ultrathin ferroic HfO<sub>2</sub>–ZrO<sub>2</sub> superlattice gate stack for advanced transistors.” <i>Nature </i>604, 65 (2022).<br/>[7] <u>N Shanker</u> <i>et al</i>. “On the PBTI Reliability of Low EOT Negative Capacitance 1.8 nm HfO<sub>2</sub>-ZrO<sub>2</sub> Superlattice Gate Stack on L<sub>g</sub> =90 nm nFETs.” in <i>2022 IEEE Symposium on VLSI Technology and Circuits</i> (IEEE, 2022).<br/>[8] <u>N Shanker</u> <i>et al</i>. “CMOS Demonstration of Negative Capacitance HfO<sub>2</sub>-ZrO<sub>2</sub> Superlattice Gate Stack in a Self-Aligned, Replacement Gate Process”. in <i>2022 International Electron Devices Meeting </i>(IEEE, 2022).<br/>[9] <u>N Shanker</u> <i>et al.</i> “Ultralow equivalent oxide thickness via one nanometer ferroelectric negative capacitance.” <i>In preparation</i><br/>[10] S Jo <i>et al</i>. “Negative differential capacitance in ultrathin ferroelectric hafnia.” <i>Nature Electronics</i>. 6, 390 (2023).