Apr 25, 2024
2:30pm - 2:45pm
Room 436, Level 4, Summit
Eng Kang Koh1,2,Putu Andhita Dananjaya1,Han Yin Poh1,2,Lingli Liu1,Calvin Lee1,2,Young Seon You2,Wen Siang Lew1
Nanyang Technological University Singapore1,GlobalFoundries2
Eng Kang Koh1,2,Putu Andhita Dananjaya1,Han Yin Poh1,2,Lingli Liu1,Calvin Lee1,2,Young Seon You2,Wen Siang Lew1
Nanyang Technological University Singapore1,GlobalFoundries2
With the amount of digital data growth in recent years, although the von Neumann architecture-based processors can efficiently conduct logic computations on structured data, they do poorly in image recognition and natural language processing for unstructured data. This leads to a paradigm shift towards a Neuromorphic computing architecture. The Resistive Random Access Memory (RRAM), or in particular its integration with a transistor, 1T1R (1 Transistor - 1 RRAM) structure, is a popular solution to this problem. These devices emulate storing synaptic weights in terms of the conductance of the devices. However, an innate problem is that the RRAM’s switching mechanism typically involves an abrupt switching current response. This means that its ability to be used as a neuromorphic computing memory device is hindered because the total number of states that can be stored within a single device is restricted. In this work, using different voltage schemes, the Ta<sub>2</sub>N/Ta<sub>2</sub>O<sub>5</sub>/Pt RRAM device demonstrates both filamentary (digital) and interfacial (analog) resistive switching within a single device. A thorough evaluation of the underlying principles governing both switching modes revealed that the anomalous gradual switching is linked to the modulation of interfacial oxides that form between the active electrode and the oxide switching layer. The coexistence of the two switching mechanisms means it is possible to operate the filamentary switching RRAM as a storage device and the interfacial switching RRAM as a neuromorphic device element within a chip fabricated using the same fabrication process steps. The devices also demonstrate good scalability (<150 nm), low operational voltage (< |2.5 V|), endurance (>10<sup>6</sup> cycles), good retention (85<sup>o</sup>C at 10<sup>4</sup>s), and the possibility of reversibility of the mechanisms while having good multi-level cell properties. With the duality of these two switching modes, our device is poised for application in both memory storage and synaptic weight-storing applications.