Selective Processes to Enable Scaling: Progress, Challenges and Opportunities

Selective deposition has been used in microelectronics industry for many years. These processes are mostly done at high temperature. As scaling continues, device architecture has evolved from planar to FinFET, gate all around and vertically-stacked-Complementary Field Effect Transistors (CFETs). With the stacking of devices, it is desirable to enable low temperature selective processes. In this paper we discuss three examples of selective processes which are used to help extend scaling: (1) Dielectric on Metal (DoM) to enable advanced interconnect, (2) Dielectric on Dielectric (DoD) to enable Fully Self-Aligned Via (FSAV), and (3) Combining selective deposition and etch to extend EUV scalability. These three processes are well established and not too far from high volume manufacturing (HVM). Beyond these processes, challenges in selective deposition on similar surfaces and high aspect ratio structures will be discussed.