Dielectric Integration and interface defect engineering for β-Ga₂O₃ MOS devices

Dielectric integration is always challenging for any semiconductor material when used in a metal-oxide-semiconductor (MOS) configuration. SiO₂ offers the best oxide interface on Si, mainly because the SiO₂/Si interface was carefully engineered by the pioneering works of Atalla et al. Interfacial defect engineering is currently being investigated for wide-bandgap semiconductor such as SiC. Such defect engineering solutions are, however, missing for other oxide/semiconductor interfaces involving wide or ultra-wide bandgap semiconducting materials.<br/><br/>The newest semiconductor β-Ga₂O₃ can be grown from melt, has a high critical electric field, a low switching loss that can be obtained at a high breakdown voltage, and an efficient high frequency performance. β-Ga₂O₃ has therefore already demonstrated promises for power switching applications with drive current &gt; 100A and high temperature electronics with operating temperature T &gt;500 ^oC. The dielectric/semiconductor interface of β-Ga₂O₃ however has large interface defect density (N_IT) mainly due to the deposition of dielectrics after many process steps in a device fabrication process. A dielectric-early process flow is preferred for reducing N_IT; to enable this process, dielectrics will have to withstand all the remaining semiconductor process steps, some of which (such as dopant activation anneal) involves &gt;900 ^oC process temperature. Such high T processes induce poly-crystallization (resulting in electrical and mass transport through the grain boundaries) in most dielectrics formed using atomic layer deposition (ALD) – a deposition process that is routinely used for all semiconductor device processes.<br/>Till 2020, most of the MOS devices made on β-Ga₂O₃ substrates exhibited N_IT &gt; 10¹² cm^-2 and, therefore, devices exhibited large hysteresis and frequency dispersion during the capacitance-voltage (C-V) and current-voltage (I-V) characteristics. Using conventional crystalline semiconductor wisdom, crystallization of dielectrics via high T annealing were considered for defect reduction (and hence hysteresis and dispersion reduction); this however had limited success as the resultant poly-crystalline suffered from grain boundary conduction and materials diffusion. Therefore, dielectrics with low N_IT and good thermal stability still remained elusive for establishing electronic-grade semiconductor process flow for β-Ga₂O₃ devices.<br/>In this work, we will highlight the general challenge for integrating dielectrics on β-Ga₂O₃, address the associated requirements for obtaining high-quality dielectric with low N_IT, and in particular discuss the integration of Al₂O₃ and SiO₂ dielectrics on (010) β-Ga₂O₃ substrates. We will discuss the role of surface roughness, surface cleanliness (using piranha treatment), surface defective layer removal (using buffered HF), and post-deposition annealing on interface defect density. We will also compare the thermal stability and interface quality of SiO₂ and Al₂O₃ dielectrics formed on β-Ga₂O₃. We will explain how interfacial crystallization of monolayer Al₂O₃ (during a low temp ALD deposition at 250 ^oC) enabled formation of high-quality interfaces at the Al₂O₃/β-Ga₂O₃ interface – therefore, showed the lowest interface defect density. This is mainly because the crystal structures of γ-Al₂O₃ and β-Ga₂O₃ resembles each other and hence promotes the formation of monolayer γ-Al₂O₃ at the Al₂O₃/β-Ga₂O₃ interface even at 250 ^oC deposition temperature.<br/>All these considerations have enabled us to envision pathways towards electronic-grade integration of dielectrics on β-Ga₂O₃ substrates needed to attain high breakdown voltage in power electronics applications and also to attain low frequency dispersion and high operating frequency in radio frequency applications.