Dopant-selective photoelectrochemical etching of 4H-SiC for wafer-scalable SiCOI integrated photonics

Usable quantum networks with long distance baselines requires quantum repeaters with integrated quantum memories. 4H-SiC hosts a variety of optically addressable defects, can yield low-loss photonics while being compatible with CMOS fabrication processes, and has a highly mature wafer-scale supply chain. However >3”, total thickness variation (TTV) of SiC thin film during the SiC-on-insulator (SiCOI) fabrication impedes scalable fabrication of integrated photonic devices with acceptable propagation loss and efficient coupling of optical elements. While the high chemical stability of SiC makes traditional wet processes ineffective, we have demonstrated dopant-selective photoelectrochemical (PEC) etching of SiC epitaxial layers using n-type SiC as a sacrificial layer with a p-type etch stop. We apply the concept of selective PEC to a realistic SiC-on-insulator (SiCOI) stack for highly effective TTV reduction. We show that by using selective PEC etching to etch a sacrificial n-type layer and stop selectively on an intrinsic photonic layer, we are able to reduce the TTV of the SiC by over an order of magnitude. We show that the reduced TTV results in a dramatically improved yield and propagation loss of waveguides compared to the standard polishing process. The results presented here represent a step forward in realization of scalable 4H-SiC integrated photonic devices toward long-distance quantum networking.